The only difference between ecs p6stmt MB and winfast6300 is that they use the different sis chipset. P6stmt use sis630ET, winfast6300 use sis630. So Doc2001 which can work on winfast6300 can't work on P6stmt. Is it right?
thanks
zhu
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I've got elitegroup MB P6STMT based sis630e. It's hard for me to setup the correct value of dll.inc(0x8c~0x8f).
(1) I copy the value from winfast6300. My Doc2001 can boot but linux kernel will hangup.
(2) I copy the value from pcchips/m787cl+. MB halt.
(3) I copy the value from elitegroup/p6stp-fl. It is just the same as winfast6300.
who know how to guess the four values in dll.inc?
thanks
zhu
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----- Message Text -----
There is some work going on here and I will not be available for technical
discussions.
I hope to be back in a bit.
thanks
ron
I've got two kind of sis630e motherboard, one is winfast 6300 Max pro, the other is from ellite group.
(1) for winfast 6300
I've burned one DOC2001 to boot it, for some SDRAM it works well, for some other SDRAM it can't boot, it hangup on jmp spl_vector(after my debug testing ).
(2) for ellite board
The same doc2001 chip which works well on winfast 6300 can't boot ellite board. It also hangup on jmp spl_vector. For some SDRAM it can boot linux, but linux will hangup at anytime.
(3) conclusion
I think IPL SDRAM initialization has some problem. So the SDRAM can't work stably. Who has sis630 manual? I can check if I can adjust the SDRAM control parameters. Or someone can point out what's the exact reason causing the problem.
tks
zhu
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I find winfast 6300 Max pro using Sis630e chipset. The problem of reading spd RAM type byte is also return 01 or 00 for different SDRAM but no 04. Is it a problem?
thanks
zhu
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ron minnich wrote:
> no, it's worse than that.
>
> If the copy fails, and you're uncompressed, and you don't map ram over
> flash, the table is still there.
>
> Yeah, it sucks all right.
>
>>There must be some sort of ELF section alignment thats missing in the
>>linking of irq_tables.o
>
> We have to fix this. I just never had time.
Can't ELF do alignments? If so then we can just create this table into
a seperate section and tell the linker to align it properly or perhaps
locate it absolutly.
Eric,
When can you commit cpu releated changes in the public tree?
Please advise if I could commit E7501/P62h2/82801EB-R into the v2 now or
after you commit CPU stuffs.
Regards
YH
-----邮件原件-----
发件人: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com]
发送时间: 2004年6月25日 17:27
收件人: YhLu
抄送: ron minnich; Stefan Reinauer; LinuxBIOS
主题: Re: E7501 support in V2
YhLu <YhLu(a)tyan.com> writes:
> Eric,
>
> I find the problem, need to call init_timer in p6 cpu fixup. It works well
> now.
>
> Some code should be moved to p6 or even p5.
>
> For example:
> apic_timper.c
> enable_mmx_sse.inc/disable_mmx_sse.inc
Except for the Opteron init_timer is really not appropriate as a
cpu thing. In general it is a motherboard type decision. It is
one of the rough areas in V2 right now.
For the rest you can see why I am in the process of reworking
the cpu initialization code.
Eric
Hello,
I got the testbios built and tried it and got the following error
doing:
./testbios -d 0x200 -t vgabios.bin
I made my vgabios.bin by doing:
dd if=/dev/mem of=vgabios.bin skip=1536 count=128
The error is:
c000:00dc 6e OUTSB
AX=1cff BX=ffff CX=ff00 DX=60ac SP=fff4 BP=0000 SI=0002
DI=0002
DS=0040 ES=0000 SS=0030 CS=c000 IP=00de NV UP DI PL NZ NA
PE NC
c000:00dd f4 HALT
halt_sys: file ops.c, line 9804
halted
AX=1cff BX=ffff CX=ff00 DX=60ac SP=fff4 BP=0000 SI=0002
DI=0002
DS=0040 ES=0000 SS=0030 CS=c000 IP=00de NV UP DI PL NZ NA
PE NC
c000:00de 6e HALT
Can someone please explain this error to me and how to possibly fix it?
I have a Tyan mb with a 2885 chipset. AMD64 chip. And an Nvidia FX
5950 video card.
Any help would be appreciated:)
Thank you,
Dave
Dear All,
I am new to this list and have been emailing Ron a few
times about the SiS530.
Ron sugested that I use FILO for my project and
I have had a trawl around to find filo, and have
downloaded a BZ from a fairly unreputable looking web
site. Does anyone have the "official" website
address at all?
Also Ron said to configure LinuxBIOS for the 530, but
I thought that it was not supported by the LinuxBIOS
project.
I understand (basically) the idea of having payload
code (which is filo from your advice), but I think I
may need some more explicit instructions: do I assume
correctly that I need to flash my current 530 board
bios with LinuxBIOS with a payload of filo and have
filo point to boot off HDA1?
Then this leads me onto another question: can I pull
a bios chip from another PC and use that to flash LB
onto to use with the 530, or are some regions of the
BIOS chip un-writable and/or mobo specific? If the
latter then would it not be safer to get a small DoC
and flash that, as I only have one 530 Mobo.
Thanks
andy
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