coreboot June 2004

coreboot@coreboot.org

43 participants
102 discussions

Re: E7501 support in V2
by YhLu 15 Jul '04

15 Jul '04

Eric, When can you commit cpu releated changes in the public tree? Please advise if I could commit E7501/P62h2/82801EB-R into the v2 now or after you commit CPU stuffs. Regards YH -----邮件原件----- 发件人: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] 发送时间: 2004年6月25日 17:27 收件人: YhLu 抄送: ron minnich; Stefan Reinauer; LinuxBIOS 主题: Re: E7501 support in V2 YhLu <YhLu(a)tyan.com> writes: > Eric, > > I find the problem, need to call init_timer in p6 cpu fixup. It works well > now. > > Some code should be moved to p6 or even p5. > > For example: > apic_timper.c > enable_mmx_sse.inc/disable_mmx_sse.inc Except for the Opteron init_timer is really not appropriate as a cpu thing. In general it is a motherboard type decision. It is one of the rough areas in V2 right now. For the rest you can see why I am in the process of reworking the cpu initialization code. Eric

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qemu target
by Stefan Reinauer 30 Jun '04

30 Jun '04

Hi LinuxBIOS hackers, I checked in a new target: emulation/qemu-i386 It allows to exchange the BIOS image of the multi target CPU emulator QEMU (http://fabrice.bellard.free.fr/qemu/) with a LinuxBIOS image. Since failsafe handling does not make much sense in an emulator, I only have one image built, with more space being available for the payload. The payload is about 155k, the image is 256k and LinuxBIOS occupies 64k, so there's quite some room left. Now, LinuxBIOS starts and executes all the romcc generated code in auto.c. But after that output suddenly stops. All of the resource allocation seems completely skipped. The first thing I get after this is when the payload has taken over. What can I do to get the output of the gcc compiled code again? In the beginning it did show these messages, but I was unable to reproduce this behaviour, unfortunately. I would guess it is not really skipped, since otherwise the payload is not executed. Attached see a log of the serial console and a log of port 80 activity. Can anyone point me into how to debug this? I am a bit confused. Am I using crappy compilers again? LinuxBIOS-1.1.6-OpenBIOS Mon Jun 28 16:54:53 CEST 2004 starting... Copying LinuxBIOS to ram. Jumping to LinuxBIOS. boot eax = 0xe1fb007 boot ebx = 0x3ff5878 boot arg = 0x3ff5878 Bootloader: elfboot Version: 1.3 Searching for LinuxBIOS tables... Found canidate at: 00000500 header checksum o.k. table checksum o.k. record count o.k. Found LinuxBIOS table at: 00000500 0x00000000000000 0x00000000000000 1748 0x000000000006d4 0x00000000000000 67107116 00000000000006d4-0000000004000000 RAM 64 MB Current location: 0x100000-0x1982e7 Relocating to 0x3f67d10-0x3fffff7... ok forth started. initializing memory...done Initializing PCI devices... 0:0.0 - 8086:1237 - /pci/pci8086,1237 - host 0:1.0 - 8086:7000 - /pci/pci8086,7000 - isa 0:1.1 - 8086:7010 - /pci/pci8086,7010 - ide 0:2.0 - 1234:1111 - /pci/pci1234,1111 - display 0:3.0 - 10ec:8029 - /pci/pci10ec,8029 - ethernet ide0: [io ports 0x1f0-0x1f7,0x3f6] drive0 [ATA disk]: QEMU HARDDISK ide1: [io ports 0x170-0x177,0x376] drive0 [ATAPI cdrom]: QEMU CD-ROM Welcome to OpenBIOS v1.0.RC1 Built on Jun 28 2004 17:29 Type 'help' for detailed information [x86] Booting default not supported. 0 > ok 0 > ---------------------------------------------- Port80 log: outb: 0080 10 outb: 0080 05 outb: 0080 11 outb: 0080 12 outb: 0080 13 outb: 0080 fe outb: 0080 80 outb: 0080 39 outb: 0080 40 outb: 0080 5f outb: 0080 24 outb: 0080 25 outb: 0080 55 outb: 0080 66 outb: 0080 88 outb: 0080 89 outb: 0080 70 outb: 0080 60 outb: 0080 6a outb: 0080 92 outb: 0080 9b outb: 0080 75 outb: 0080 9a outb: 0080 96 outb: 0080 f8 outb: 0080 fe

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答复: E7501 support in V2
by YhLu 30 Jun '04

30 Jun '04

Just check in E7501/ICH5R support into V2. the MB is tyan/s2735 Regards YH Intel E7501 P64H2 ICH5R support CVS: ---------------------------------------------------------------------- CVS: Enter Log. Lines beginning with `CVS:' are removed automatically CVS: CVS: Committing in . CVS: CVS: Modified Files: CVS: src/cpu/p6/Config.lb src/cpu/p6/cpufixup.c CVS: src/include/device/pci_ids.h CVS: src/superio/winbond/w83627hf/superio.c CVS: Added Files: CVS: src/cpu/p6/apic_timer.c src/cpu/p6/chip.h CVS: src/cpu/p6/disable_mmx_sse.inc src/cpu/p6/enable_mmx_sse.inc CVS: src/mainboard/tyan/s2735/Config.lb CVS: src/mainboard/tyan/s2735/auto.c CVS: src/mainboard/tyan/s2735/chip.h CVS: src/mainboard/tyan/s2735/cmos.layout CVS: src/mainboard/tyan/s2735/failover.c CVS: src/mainboard/tyan/s2735/irq_tables.c CVS: src/mainboard/tyan/s2735/mainboard.c CVS: src/mainboard/tyan/s2735/mptable.c CVS: src/northbridge/intel/e7501/Config.lb CVS: src/northbridge/intel/e7501/chip.h CVS: src/northbridge/intel/e7501/debug.c CVS: src/northbridge/intel/e7501/e7501.h CVS: src/northbridge/intel/e7501/northbridge.c CVS: src/northbridge/intel/e7501/raminit.c CVS: src/northbridge/intel/e7501/raminit.h CVS: src/northbridge/intel/e7501/reset_test.c CVS: src/southbridge/intel/i82801er/Config.lb CVS: src/southbridge/intel/i82801er/cmos_failover.c CVS: src/southbridge/intel/i82801er/i82801er.c CVS: src/southbridge/intel/i82801er/i82801er.h CVS: src/southbridge/intel/i82801er/i82801er_ac97.c CVS: src/southbridge/intel/i82801er/i82801er_early_smbus.c CVS: src/southbridge/intel/i82801er/i82801er_ide.c CVS: src/southbridge/intel/i82801er/i82801er_lpc.c CVS: src/southbridge/intel/i82801er/i82801er_nic.c CVS: src/southbridge/intel/i82801er/i82801er_pci.c CVS: src/southbridge/intel/i82801er/i82801er_reset.c CVS: src/southbridge/intel/i82801er/i82801er_sata.c CVS: src/southbridge/intel/i82801er/i82801er_smbus.c CVS: src/southbridge/intel/i82801er/i82801er_usb.c CVS: src/southbridge/intel/i82801er/i82801er_usb2.c CVS: src/southbridge/intel/i82870/82870.h CVS: src/southbridge/intel/i82870/Config.lb CVS: src/southbridge/intel/i82870/p64h2_ioapic.c CVS: src/southbridge/intel/i82870/p64h2_pci_parity.c .... Others in targets/tyan/s2735

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long
by Miernik 29 Jun '04

29 Jun '04

I have posted this to linux-fbdev-users http://sourceforge.net/mailarchive/forum.php?thread_id=4854738&forum_id=2358 but nobody anwsered, so maybe here someone will know. I use the framebuffer with this line in my /boot/grub/menu.lst : kernel /boot/vmlinuz-2.4.24-1-386 root=/dev/hda1 ro video=sisfb:mode:1152x864x16,rate:70 My video card is (output of lspci -vv): 0000:01:00.0 VGA compatible controller: Silicon Integrated Systems [SiS] 630/730 PCI/AGP VGA Display Adapter (rev 31) (prog-if 00 [VGA]) Subsystem: Silicon Integrated Systems [SiS] 630/730 PCI/AGP VGA Display Adapter Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- BIST result: 00 Region 0: Memory at c0000000 (32-bit, prefetchable) [size=128M] Region 1: Memory at cfee0000 (32-bit, non-prefetchable) [size=128K] Region 2: I/O ports at bc00 [size=128] Capabilities: [40] Power Management version 1 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] AGP version 2.0 Status: RQ=16 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW- GP3- Rate=x1,x2,x4 Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate=<none> It's a video card build in a PCChips M810L REV7.0 motherboard. The CPU is AMD Duron 600 MHz. Of course I use the fbdev X driver. The problem I have it takes 6.7 seconds to switch from console to X with <Alt><F7>. The 6.7 s time is very consistent, every time I measure it. It"s very long and annoying. The other direction (X->console with <Alt><F1>) its about immediate. During that 6.7 seconds the a rough outline of what is supposed to be on the screen is displayed. For example if the Galeon web browser is on the screen, then it displays the area where Galeon menus and other controls are in a block of grey, the area of the webpage in a block of black, and the URL box as a block of white. What might be the reason, and is there anything to be done about this? In kern.log doring boot I get: May 28 18:25:49 jaworz kernel: sisfb: Video ROM found and mapped to c00c0000 May 28 18:25:49 jaworz kernel: sisfb: Framebuffer at 0xc0000000, mapped to 0xe00ab000, size 8192k May 28 18:25:49 jaworz kernel: sisfb: MMIO at 0xcfee0000, mapped to 0xe08ac000, size 128k May 28 18:25:49 jaworz kernel: sisfb: Memory heap starting at 4096K May 28 18:25:49 jaworz kernel: sisfb: CRT1 DDC supported May 28 18:25:49 jaworz kernel: sisfb: CRT1 DDC level: 2 May 28 18:25:49 jaworz kernel: sisfb: Monitor range H 31-61KHz, V 60-75Hz, Max. dotclock 78MHz May 28 18:25:49 jaworz kernel: sisfb: WARNING: Refresh rate exceeds monitor specs! May 28 18:25:49 jaworz kernel: sisfb: Mode is 1152x864x16 (60Hz) May 28 18:25:49 jaworz kernel: sisfb: Initial vbflags 0x0 May 28 18:25:49 jaworz kernel: Console: switching to colour frame buffer device 144x54 May 28 18:25:49 jaworz kernel: sisfb: Installed SISFB_GET_INFO ioctl (80046ef8) May 28 18:25:49 jaworz kernel: sisfb: Installed SISFB_GET_VBRSTATUS ioctl (80046ef9) May 28 18:25:49 jaworz kernel: sisfb: 2D acceleration is enabled, scrolling mode ypan May 28 18:25:49 jaworz kernel: fb0: SIS 730 frame buffer device, Version 1.6.16 May 28 18:25:49 jaworz kernel: sisfb: (C) 2001-2003 Thomas Winischhofer. All rights reserved. And then a line like that appears every several minutes all the time the computer is on: May 28 18:26:04 jaworz kernel: sisfb: Unsupported rate 60 for 1152x864 May 28 18:26:04 jaworz kernel: sisfb: WARNING: Refresh rate exceeds monitor specs! May 28 18:26:07 jaworz kernel: sisfb: Unsupported rate 60 for 1152x864 May 28 18:26:07 jaworz kernel: sisfb: WARNING: Refresh rate exceeds monitor specs! May 28 18:26:27 jaworz kernel: sisfb: Unsupported rate 60 for 1152x864 May 28 18:26:27 jaworz kernel: sisfb: WARNING: Refresh rate exceeds monitor specs! I do not yet run LinuxBIOS on this mainboard. I plan to (that's what I bought this motherboard for) but I first want to fix this issue. Or maybe flashing it with LinuxBIOS will magically fix the problem? -- Miernik _________________________ xmpp:miernik@amessage.info ___________________/__ tel: +48888299997 __/ mailto:miernik@ctnet.pl http://www.miernik.ctnet.pl/

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LinuxBIOS and Win2K
by Mike Shields 29 Jun '04

29 Jun '04

Greetings, Mike Shields here. I am new to the list and to LinuxBIOS in general. I have searched the list archives and have read Adam Agnew's (et al) paper on booting Win2K on top of the stackable Open Source BIOS, as well as several other papers by William Arbaugh and coauthors on secure booting and secure BIOS. I am a consultant for SPAWAR (part of the US Navy) working on a project to make USN computers running windows more secure. I have been asked to give a short presentation to some SPAWAR and FNMOC people on June 29th as part of a project conference. The points I need to cover are the differences between current BIOS and LinuxBIOS and the advantages of the latter. We are trying to convince Dell (SPAWAR has a huge contract with Dell to supply computers to the navy) to give us the information to port LinuxBIOS to their systems. One misconception I must deal with is that many people think Windows won't load over LinuxBIOS (I have Adam's paper showing otherwise). I know very little about LinuxBIOS other than what I have read on www.linuxbios.org, my scans of the archive, and a short paper form Nicholus Andrews at Linux Labs. I was hoping to get some success stories on booting windows on top of LinuxBIOS, or other information I could use in my short presentation. Thanks, Mike Michael K. Shields, Ph.D. YarCom Inc. 350 S. Center St., Suite 500, Reno, NV 89501-2114 US v:336-783-0054 f:336-217-8227 c:336-407-2190 e:mshields@yarcom.com http://www.yarcom.com

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s: binary-file for Geode GX1 + Cx5530 & TFT
by Thomas Leidenfrost 29 Jun '04

29 Jun '04

Hi there, I'm using the AW-B651-Board with the NS Geode CPU and the Cx5530. Reading the archive I found out, that some people were using a similar combination, so I wanted to ask, if somebody can send me a binary file I can simply flash? (the original Bios is backupped in a seperate ROM). Next thing is, that my board has two monitor-outputs, the ordinary 15-pole-DIN and a flatpanel-connector on the board? Is there support for the flatpanel-connector? Thanks in advance, Tom.

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答复: Etherboot USB Updates?
by YhLu 28 Jun '04

28 Jun '04

http://sourceforge.net/tracker/index.php?func=detail&aid=943300&group_id=423 3&atid=304233 Regards YH -----邮件原件----- 发件人: Jay Miller [mailto:jmiller@actuality-systems.com] 发送时间: 2004年6月28日 15:15 收件人: YhLu 抄送: linuxbios(a)clustermatic.org 主题: Etherboot USB Updates? Hi Yinghai, Have you made any updates to the USB support published as a patch to etherboot 5.2.4? If not, would it be possible to get the configuration files you use to generate a working tg3--filo.zelf? I still am having problems getting elfboot to load the payload without dying. Thanks, Jay Miller 781-229-7812x117 Actuality Systems, Inc. jmiller(a)acutality-systems.com

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Etherboot USB Updates?
by Jay Miller 28 Jun '04

28 Jun '04

Hi Yinghai, Have you made any updates to the USB support published as a patch to etherboot 5.2.4? If not, would it be possible to get the configuration files you use to generate a working tg3--filo.zelf? I still am having problems getting elfboot to load the payload without dying. Thanks, Jay Miller 781-229-7812x117 Actuality Systems, Inc. jmiller(a)acutality-systems.com

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Using Cache As Ram for K8
by Li-Ta Lo 28 Jun '04

28 Jun '04

Hello, I have successfully used the cache in the K8 processor as RAM on the AMD Serenade mainboard. The cache as ram is used as a tiny stack space for the code generated by GCC which replace the need for a register only C complier like ROMCC. Now the whole LinuxBIOS C code can be compiled by GCC. There are few problems remaining. The first thing is I can only use 7 cache lines of cache (448 bytes) reliably in the K8. The access to the 8th cache line is unstable and the access to the 9th cache line hangs the processor. The other problem is the optimize_connection() function for multi-processor configuration runs unstably under CAR. It does not overflow the stack, it's just plain unstable for some reason. So I can only configure the mainboard as Uniprocessor. Is there anyone has any idea about these problems ? If we can solve these two problems, Cache As Ram can be used routinly for K8 and probably we can try to extend it to some other processors. YHLu, Do you have any dual K8 EVB with HDT pin out and works "perfectly" under normal (ROMCC) LinuxBIOS ? The ROMCC LinuxBIOS deos not work for the AMD Serenade board 100% (I still have the phantom device s problem) and the s2885 board we have does not have the pin out. Eric, What is the "effective" or "equalvalent" stack size of ROMCC ? Is 448 bytes of stack adquant for ROMCC "linted" code in general ? Ollie

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re: [COMMIT] romcc 0.63 and some fixes...
by YhLu 25 Jun '04

25 Jun '04

Next week, I will work on i82875 support. Regards YH -----邮件原件----- 发件人: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] 发送时间: 2004年6月25日 18:24 收件人: YhLu 抄送: LinuxBIOS 主题: Re: 答复: [COMMIT] romcc 0.63 and some fixes... YhLu <YhLu(a)tyan.com> writes: > So next week, we can get the updated romcc? That is the plan. I don't know how much it will fix beyond the segfault issue... Eric

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coreboot June 2004