coreboot October 2004

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197 discussions

IBM Netvista 8363 (again)
by David Smith 02 Oct '04

02 Oct '04

I was searching the archive and saw that zac luzader has managed to get the Netvista to boot to 'something sane' of his own making. I came into posession of a couple of these Netvistas and I want to figure out what I can do with them. Zac, or anyone else who has these working in a standalone mode, please drop me a line. Thanks David

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RE: [BULK] Re: changes today.
by YhLu 01 Oct '04

01 Oct '04

Eric, if (cpu_init_detected()) { asm volatile ("jmp __cpu_reset"); } The cpu_init seems reset the memcontroller with opteron. (all HT links configuration are still there). So you can not just jmp to __cpu_reset. There are two solution for it 1. init ram and then jump to __cpu_reset But the smbus_io_base may already changed by last normal boot. So should use assigned smbus_io_base, that need to change amd8111_early_smbus.c structure. 2. just issue another soft reset, --- amd8111 is in bus 1 now. if (cpu_init_detected()) { #if 0 asm volatile ("jmp __cpu_reset"); #else /* cpu reset also reset the memtroller ???? need soft_reset to reset all except keep HT link freq and width */ distinguish_cpu_resets(); soft2_reset(); #endif } Which one do you prefer to? Regards YH

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RE: changes today.
by YhLu 01 Oct '04

01 Oct '04

I see. I don't want to mess the CVS tree. -----Original Message----- From: Ronald G. Minnich [mailto:rminnich@lanl.gov] Sent: Friday, October 01, 2004 4:24 PM To: Stefan Reinauer Cc: YhLu; ebiederman(a)lnxi.com; Li-Ta Lo; linuxbios(a)clustermatic.org Subject: Re: changes today. On Sat, 2 Oct 2004, Stefan Reinauer wrote: > Hi Yinghai, Yinghai, there seem to be a few questions on this patch, can you let Ollie and me go over it next week? He is back then. Please don't commit yet. thanks ron

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RE: [BULK] Re: changes today.
by YhLu 01 Oct '04

01 Oct '04

> 4. better ht_setup_chainx() in incoherent_ht.c ---> change share bus 0 to different bus for different incoherent HT link. For s2885 there are two incoherent links in CPU0, one for 8151 and one for 8131/8111. For AMD/quartet are incoherent link in CPU0, and another link in CPU1 For S2895 there are two incoherent links in CPU0 and another link in CPU1. For S2885, in old ht_setup_chains, I let the two links share bus 0, So PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06010207, PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000007, But if there is too much link, will used the device num. So update the ht_setup_chains static int ht_setup_chains(const struct ht_chain *ht_c, int ht_c_num) { /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. * On most boards this just happens. If a cpu has multiple * non Coherent links the appropriate bus registers for the * links needs to be programed to point at bus 0. */ int reset_needed; unsigned upos; device_t udev; int i; reset_needed = 0; for (i = 0; i < ht_c_num; i++) { uint32_t reg; unsigned devpos; unsigned regpos; uint32_t dword; unsigned busn; reg = pci_read_config32(PCI_DEV(0,0x18,1), ht_c[i].devreg); //We need setup 0x94, 0xb4, and 0xd4 according to the reg devpos = ((reg & 0xf0)>>4)+0x18; // nodeid; it will decide 0x18 or 0x19 regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; // link n; it will decide 0x94 or 0xb4, 0x0xd4; busn = (reg & 0xff0000)>>16; dword = pci_read_config32( PCI_DEV(0, devpos, 0), regpos) ; dword &= ~(0xffff<<8); dword |= (reg & 0xffff0000)>>8; pci_write_config32( PCI_DEV(0, devpos,0), regpos , dword); /* Make certain the HT bus is not enumerated */ ht_collapse_previous_enumeration(busn); upos = ht_c[i].upos; udev = ht_c[i].udev; reset_needed |= ht_setup_chainx(udev,upos,busn ); } return reset_needed; } > 5. fix one bug about io and mem allocation for multi ht links. --- in > northbridge.c Should mark some reg to prevent the overlap. Because amdk8_find_mempair and amdk8_find_iopair are called several times (for the incoherent links), before the registers are set. So same reg will be assigned to different link. That is bug, So add some thing in the PCI reg. /* Mark reg has been used now */ base = f1_read_config32(reg); if( (base & 3) != 3 ) { base |= 0x01fff000; f1_write_config32(reg, base); } /* Mark reg has been used now */ base = f1_read_config32(reg); if( (base & 3) != 3 ) { base |= 0xffffff00; f1_write_config32(reg, base); } Regards YH

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RE: changes today.
by YhLu 01 Oct '04

01 Oct '04

Please respond. Otherwise I will commit it today. -----Original Message----- From: YhLu Sent: Thursday, September 30, 2004 12:01 PM To: Ronald G. Minnich; ebiederman(a)lnxi.com; Stefan Reinauer; Li-Ta Lo Cc: linuxbios(a)clustermatic.org Subject: RE: changes today. Ron/Eric/Stephan/Ollie, Please check the patch. 1. some tyan volatile messing because of ROMCC changes. 2. S2882 interrupt line assignment in mptable.c 3. exclude range for flash_rom. 4. better ht_setup_chainx() in incoherent_ht.c ---> change share bus 0 to different bus for different incoherent HT link. 5. fix one bug about io and mem allocation for multi ht links. --- in northbridge.c Mark it if used before assign final value. 6. enable amd/quartet to init multi incoherent HT link in auto.c --- not test, no MB on hand. 7. enable S2885 to init multi incoherent HT link in auto.c Regards YH

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PCI guru consultant needed
by Richard Smith 01 Oct '04

01 Oct '04

Bitworks needs help. We currently Intel Celeron 440bx design that has ATI M1 video chips on board. Off and on for the past 6 months or so I've been working to make them work under Linuxbios, ADLO, or testbios, etc. I've have finally managed to show that the problem is hardware related to our design. As I can make a PCI eval card from ATI work on a Asus P2B motherboard and linuxbios using X to softboot the card. The same setup on our board fails to work. Somehow the SDRAM inside the M1 chip is failing to initialize properly. The video output has all the right VSYNC and HSYNC for the 800x600 mode I setup but a black screen and a large square block for the cursor. If I exit X and try to write/read a value into video ram I get garbage back. This works on the Ausu P2B. Things with our customer have gone critical. I've got to have something working by the end of October. So I'm in search of people who really understand PCI and video stuff and are available for consulting either on site here or I can come to thier site. Also any one have on know of place I can go to get a PCI complience test done? Or hardware I can rent? We reciently borrowed a HP 16500B logic analyzer with a Future+Systems passive PCI hookup but it dosn't do complience testing. We need an additional card for that. -- Richard A. Smith

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RE: PCI guru consultant needed
by YhLu 01 Oct '04

01 Oct '04

On board and add-on card, there is some difference. I just noticed Ati ragexl init in LinuxBIOS only support Onboard device. And does not support addon card. But the ragexl init in Kernel can support both. Regards YH -----Original Message----- From: Stefan Reinauer [mailto:stepan@openbios.org] Sent: Friday, October 01, 2004 10:59 AM To: Richard Smith Cc: linuxbios(a)clustermatic.org Subject: Re: PCI guru consultant needed * Richard Smith <rsmith(a)bitworks.com> [041001 18:47]: > Somehow the SDRAM inside the M1 chip is failing to initialize properly. > The video output has all the right VSYNC and HSYNC for the 800x600 > mode I setup but a black screen and a large square block for the cursor. > If I exit X and try to write/read a value into video ram I get garbage > back. This works on the Ausu P2B. Wild guess: - Timing issues? - missing bridge initialization? Stefan _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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coreboot October 2004