coreboot July 2003

coreboot@coreboot.org

67 participants
150 discussions

Re: K8 + 2.4.21 + Tyan S2880
by YhLu 21 Jul '03

21 Jul '03

Eric, Thanks info about ROMCC option about -mcpu=k8. I will try and make the RAM can be configurable. My CPU is C0, In Opteron We may need to manipulate the MSR to enable the apic. Regards Yinghai Lu YhLu <YhLu(a)tyan.com> writes: > Eric, > > My boss has said that I can release the source code to you. > > Please find out the patch I made. Make the diff to today's tree. > > I didn't test RON new script and still use the old scripts tools. > > I strip out the LSI scsi support, because I don't know if there is any > license problem, and I have referred to their documents and may need put > their FW in the ROM. Ah, an interesting problem. > It's greater you add ops->enable function that make it easy to handle > special device. To some device if it is not gotten magic code, it will not > get the resource allocate to it. Before that I have to do it in init > function and re-allocate the resource to it again. Welcome. > Please refer to my old amd8131_ioapic.c in southbridge/amd8111. > Also you init the io_base, upper16 reg, otherwise the device in PCIX > will not got io port allocated to them, and will not work. Sorry I don't quite parse that sentence. > I have tested Stefan's the code about coherent_ht.c, and add some hardcode > to it. > coherent_ht.o.c is the original one. Coherent_ht.1.c is total hardcode one. > coherent_ht.c and coherent_ht.2.c are modified with some hardcode ones. Interesting looking at this code are you working with C0 stepping Opterons? I have the stock B3 and am having fun getting the memory resets in all of the proper places. > raminit.c and raminit.1.c are till the hardcode one, and I have tried to use > the configurable one, but auto.c can not be compiled, it is too big and used > up REG? Looking. It is your romcc options. By default romcc will not use mmx or sse registers unless you tell it that you have them. I have been doing this with -mcpu=k8. The register pressure is much less when you have 24 registers to work with instead of just 8. > The old one has been renamed to raminit.o.c. > > To start other cpus, in auto.c We must enable apic and make sure all > apic_id is right. Please refer to mainboard/tyan/s2880/auto.c boot_cpu > function. Yep, an interesting way of doing it. > Again, thank you all to answer my questions to help Tyan s2880 work with > LinuxBIOS. Ron, Stefan. Could one of you help with merging Yinghai's code? I might have time, but I don't think I will manage it before I leave for OLS on Tuesday. Eric

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EPIA-M, linuxbios + power button
by Dave Ashley 21 Jul '03

21 Jul '03

Under award bios the power button did an instant off. Under linuxbios I have to hold the power button down for 4 seconds to get the power to go off. I vaguely remember reading about controlling the power button, but I can't find it in the docs. Does anyone know how to fix this?

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about linux bios on newer boards...
by Tamer Higazi 21 Jul '03

21 Jul '03

Hi! I'd like to buy a new Computer and i am using Linux continuesly. I have asked myself if a Linuxbios could run on a newer board. Either i am asking myself, if a linuxbios could halt (run down) my linux machine if i push the power switch on my computer as it is allready possible on WinXP. For any help and answer thank you Tamer

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EPIA-M SPD progress
by Dave Ashley 20 Jul '03

20 Jul '03

I used the freebios/util/scanspd code as a starting point and found out the DDR ram is at slot 0x50 and can be accessed through standard SMBus reads at io ports 0x500+. A dump of my working eeprom is this: 128 8 7 12 10 1 64 0 4 117 117 0 128 8 0 1 14 4 12 1 2 32 0 160 117 0 0 80 60 80 45 32 144 144 80 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 156 Then 0's. These are read using int i; unsigned char val; smbus_wait_until_ready(); for(i=0;i<64;++i) { smbus_read_byte(0x50,i,&val); printf("%d%c",val, (i&15)==15 ? '\n' : ' '); } The southbridge vt8235 code sets 1106:3177 RxD1 + RxD2 in its misc_setup.inc. So standard smbus reads should be available at dram init time. Probe vs SPD discussion: I think the question is which produces a better result, regardless of complexity. Probing seems to have disadvantages in that it can't know how to set timing amounts, signal levels, or clock delays. It would only allow you to figure out the right column bit size I expect. What disadvantages does SPD have other than it is more complex? Wouldn't it let you then be able to correctly use any DDR module you want? -Dave

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IDE chipsets and hdd hotswap
by Jeremy Jackson 19 Jul '03

19 Jul '03

Hi, I have an application for IDE hdd hotswap, and I'm trying to determine the best chipset. I think one thing to consider is the ability or Linux/LinuxBIOS to completely initialize the chipset from power on reset to use UltraDMA (133 if possible). If it can do that, logically it can re-do it when a different drive is swapped in. So I'm asking on the LinuxBIOS list since IDE chip initialization has surely been dealt with. Can anyone give me the name of chipsets which they have gotten going with UltraDMA and LinuxBIOS? The second issue is the ability to tri-state off the bus, but I can find that info elsewhere (ie kernel source) The hdparm utility/kernel driver has the beginnings of this support. I know that the Promise PCI card controllers have a bios which probably contains hidden magic, perhaps another off-board card can be found. Regards, Jeremy

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Re: EPIA-M SPD progress [PMX:#]
by Dave Ashley 19 Jul '03

19 Jul '03

src/sdram/smbus_pcibus.inc has some smbus code, I was able to compile it into the epia-m tree and do some test SMBUS_READ_BYTE calls that actually read out values from the ddr eeprom. I had to #if out the section that actually does the dram configuration to get it to compile. I'm in a bad way for experimenting with this, I have to physically remove the BIOS and plug in a new one if something goes bad, and do the reverse to recover. I've fried 2 motherboards with my pliers rubbing out traces under the flashrom socket (good luck fixing that!). If the dram settings are wrong it might make the product flaky. We're trying to field some units for in situ testing real soon, and the system has to be solid. We can probably hardcode the dram configuration for our known good ddr module that we're using mostly. However I'd like the system to function the right way. I'll keep messing with it for now. -Dave >some SPD roms have incorrect information. You have to take care with SPD. > >Overall, SPD is better. However, if you are on a short fuse and need to >deliver soon, I would go with probing for now and restrict the type of ram >you use. > >Longer term, we want to do SPD. > >ron >

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EPIA-M DDR SPD detection
by Dave Ashley 19 Jul '03

19 Jul '03

It appears we've got 3 people interested in having this functional, Ron, Andrew and myself. Myself = I need it working asap just to round out our epia-m solution Andrew = Seems to be working on it right now, priority unknown Ron = Seems to want it eventually but if it's in freebios2 that would be ok As I understand it Ron doesn't have an epia-m to experiment with anyway. I can't do anything with freebios2 at this stage since everything is working so well with the freebios mechanics as it is. I don't mind doing bit banging in X86 code to get stuff done. Someone else can clean that up at a later date and convert it to C/romcc for maintainability. Now realistically I knew nothing concrete about DRAM configuration or the details on the SPD system itself until some time 2 days ago and the time since. With the lm_sensors project I've managed to read out the serial eeprom contents and view it with a perl script and it looks like the right stuff. But I wouldn't know how to interpret that data and configure the dram controller and the ddr ram itself appropriately without more studying. What I can contribute quickly could be figuring out how to read the SPD data from the VT8235 I2C or SMB bus or whatever early in the boot process. I was going to look into this right now anyway. Then maybe one of you other guys can run with this info to get the SPD dram configuration working. -Dave

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Re: Loading OS from Flash
by John Praveen 19 Jul '03

19 Jul '03

Hi Thanks. My Geode one is SC1200. ron minnich <rminnich(a)lanl.gov> wrote: On Fri, 18 Jul 2003, John Praveen wrote: > I am new to linux bios. My project is based on > geode chip. I want my linux OS to be in Flash ROM(capacity 4 MB). I have sad news. You can't get a 4 MB chip on that board, I bet. I can't get to this. This means that 4 MB Flash ROM cannot be used with SC1200? Or is it not supported in LinuxBIOS. Plz help me to understand these. It is probably 4 Mbits, 512 KB. You'll have to put that overweight linux kernel on a diet to get it to fit in there. One option is 2.4.0 or so, that might fit. Can DoC fit on your geode anywhere? No I don't use DiskOnChip. ron --------------------------------- Do you Yahoo!? SBC Yahoo! DSL - Now only $29.95 per month!

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power connectors for mainboards
by ron minnich 18 Jul '03

18 Jul '03

I have four K7SEMs which I would like to run from one PC power supply. Does anyone know if there are off-the-shelf cables available to do this type of thing? Essentially a "Y" connector for the mainboard power connector. ron

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Assembly code errors
by Dave Ashley 18 Jul '03

18 Jul '03

When I write some assembly code and I've got the syntax wrong, the build fails but the line numbers reported in error messages don't relate to the source I'm working on. I'm wondering could the build process for the assembly code be changed so the python script creates a global toplevel.asm file that has within it #includes for all the source files? So rather than cat'ing all the files, you let the compiler include them, so its error messages will be informative. There's nothing especially bad about ASM code development, but things like accurate error reporting can make it easier (or harder when absent). -Dave

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coreboot July 2003