coreboot March 2003

coreboot@coreboot.org

61 participants
96 discussions

[epia]Unknown bootloader class
by NEWBELL7＠magicn.com 18 Mar '03

18 Mar '03

I have epia board. I had followed the HOWTO/EPIA Documentation. But The debug messages are like this below. What's wrong? I use a ROM Emulator. And I use mkelfImage from freebios/util/mkelfImage/. Please, Help me!! ===================================================== LinuxBIOS-1.0.0 Tue Mar 18 21:45:13 KST 2003 starting... Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.0.0 Tue Mar 18 21:45:13 KST 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Scanning PCI bus...PCI: pci_scan_bus for bus 0 PCI: 00:00.0 [1106/0601] PCI: 00:01.0 [1106/8601] PCI: 00:11.0 [1106/8231] PCI: 00:11.1 [1106/0571] PCI: 00:11.2 [1106/3038] PCI: 00:11.3 [1106/3038] PCI: 00:11.4 [1106/8235] PCI: 00:11.5 [1106/3058] PCI: 00:11.6 [1106/3068] PCI: 00:12.0 [1106/3065] PCI: pci_scan_bus for bus 1 PCI: pci_scan_bus returning with max=01 PCI: pci_scan_bus returning with max=01 done Allocating PCI resources... PCI: 00:00.0 register 10(00000008), read-only ignoring it PCI: 00:00.0 register 10(00000008), read-only ignoring it PCI: 00:00.0 register 10(00000008), read-only ignoring it PCI: 00:00.0 register 10(00000008), read-only ignoring it ASSIGN RESOURCES, bus 0 PCI: 00:01.0 1c <- [0x00001000 - 0x00000fff] bus 1 io PCI: 00:01.0 24 <- [0xfeb00000 - 0xfeafffff] bus 1 prefmem PCI: 00:01.0 20 <- [0xfeb00000 - 0xfeafffff] bus 1 mem PCI: 00:11.1 20 <- [0x00001c40 - 0x00001c4f] io PCI: 00:11.2 20 <- [0x00001c00 - 0x00001c1f] io PCI: 00:11.3 20 <- [0x00001c20 - 0x00001c3f] io PCI: 00:11.5 10 <- [0x00001000 - 0x000010ff] io PCI: 00:11.5 14 <- [0x00001c50 - 0x00001c53] io PCI: 00:11.5 18 <- [0x00001c60 - 0x00001c63] io PCI: 00:11.6 10 <- [0x00001400 - 0x000014ff] io PCI: 00:12.0 10 <- [0x00001800 - 0x000018ff] io PCI: 00:12.0 14 <- [0xfeb00000 - 0xfeb000ff] mem ASSIGNED RESOURCES, bus 0 done. Enabling PCI resourcess...PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 cmd <- 07 PCI: 00:11.0 cmd <- 87 PCI: 00:11.1 cmd <- 81 PCI: 00:11.2 cmd <- 01 PCI: 00:11.3 cmd <- 01 PCI: 00:11.4 cmd <- 00 PCI: 00:11.5 cmd <- 01 PCI: 00:11.6 cmd <- 01 PCI: 00:12.0 cmd <- 83 done. Initializing PCI devices... PCI devices initialized sizeram: returning 0x1fc00 KB sizeram: NOT returning 0x1fc00 KB sizeram: there are still some SPD problems ... sizeram: SO we return only 0x10000 KB totalram: 64M Initializing CPU #0 Enabling cache... Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 64MB, type WB DONE variable MTRRs Clear out the extra MTRR's call intel_enable_fixed_mtrr() call intel_enable_var_mtrr() Leave setup_mtrrs done. Max cpuid index : 1 Vendor ID : CentaurHauls Processor Type : 0x00 Processor Family : 0x06 Processor Model : 0x07 Processor Mask : 0x00 Processor Stepping : 0x08 Feature flags : 0x00803035 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Disabling local apic...done. CPU #0 Initialized Mainboard fixup IDE enable in reg. 50 is 0x7 set IDE reg. 50 to 0x7 IRQs in reg. 4c are 0x4 setting reg. 4c to 0x4 enables in reg 0x40 0x8 enables in reg 0x40 read back as 0xb enables in reg 0x9 0x8f enables in reg 0x9 read back as 0x8a command in reg 0x4 0x81 command in reg 0x4 reads back as 0x7 Ethernet fixup Configuring VIA LAN RTC Init Invalid CMOS LB checksum Final mainboard fixup Southbridge fixup setting southbridge Assigning IRQ 12 to 0:11.2 Readback = 12 Assigning IRQ 12 to 0:11.3 Readback = 12 Assigning IRQ 10 to 0:11.5 Readback = 10 Assigning IRQ 10 to 0:11.6 Readback = 10 setting ethernet Assigning IRQ 11 to 0:12.0 Readback = 11 setting pci slot Checking IRQ routing tables... /home/newbell/LinuxBios/freebios/src/arch/i386/lib/pirq_routing.c: 24:check_p irq_routing_table() - irq_routing_table located at: 0x0000a440 done. Copying IRQ routing tables to 0xf0000...done. Verifing priq routing tables copy at 0xf0000...failed Wrote linuxbios table at: 00000500 - 00000664 checksum 48cc Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.2 203:init_bytes() - zkernel_start:0xfff00000 zkernel_mask:0x0000ffff Searching for 16 byte tags 64:rom_read_bytes() - overflowed source buffer. max_block = 15 init_bytes found 0 tags Found ELF candiate at offset 0 New segment addr 0x94000 size 0x74e8 offset 0x60 filesize 0x396c (cleaned up) New segment addr 0x94000 size 0x74e8 offset 0x60 filesize 0x396c Loading Segment: addr: 0x0000000000094000 memsz: 0x00000000000074e8 filesz: 0x00 0000000000396c Clearing Segment: addr: 0x000000000009796c memsz: 0x0000000000003b7c Jumping to boot code at 0x94000 ROM segment 0x4041 length 0x0006 reloc 0x9400 Etherboot 5.0.8 (GPL) Tagged ELF for [VIA 86C100] Boot from (N)etwork or from (L)ocal? clocks_per_tick = 420319 N Probing...[VIA 86C100]Found VIA 6102 ROM address 0x0000 rhine.c v1.0.0 2000-01-07 IO address 1800 Ethernet Address: 00:00:F0:91:58:39 Analyzing Media type,this will take several seconds........OK Linespeed=10Mbs Fullduplex The PCI BIOS has not enabled this device! Updating PCI command 0003->0007. pci_bus 00 pci_device_fn 90 Searching for server (DHCP)... .Me: 165.213.172.236, Server: 165.213.172.155, Gateway 165.213.172.1 Loading 165.213.172.155:/tftpboot/vmlinuz.xterm ...(ELF)... ................... ....................................................................... ....... ....................................................................... ....... ....................................................................... ....... ....................................................................... ....... ....................................................................... ....... ....................................................................... ....... ....................................................................... ....... ....................................................................don e rhine disable Unknown bootloader class! type=0x000101C0 data=0x000989CE Firmware type: LinuxBIOS

1 0

SiS630 Software Watchdog Timer
by Spirit 18 Mar '03

18 Mar '03

Hello! I've been reading the SIS630 datasheet and found out that the chipset has a watchdog timer (for some reason they call it 'software') similar to that of the i810. Does anybody here know if there is a ready driver for that thing? P.S. I'm inspecting the datasheet in search for ways of disabling AC97 Audio and Modem functions, as that would be a great addition to the linuxbios. -- Best regards, Spirit mailto:spirit@reactor.ru

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RE: ADLO for EPIA
by hcyun＠etri.re.kr 17 Mar '03

17 Mar '03

Thanks. It works and I can see something (just splash of colors) on my CRT. The screen, though it is not usable, is brought up by original VGABIOS using ADLO. Heechul. > -----Original Message----- > From: Andrew Ip [mailto:aip@cwlinux.com] > Sent: Monday, March 17, 2003 3:28 PM > To: hcyun(a)etri.re.kr > Cc: linuxbios(a)clustermatic.org > Subject: Re: ADLO for EPIA > > > Heechul, > > > With current linuxbios for EPIA, I found that internel > graphic device (bus > > 1, dev 0 ) is not visible in the pci configuration space. I > have tried to > > enable this by setting PP_Rx3E and RxA9 registers, but with failed. > > Do you know how to make it visible? > Including this setup will enable the vga device. Hope this help. > > -Andrew > > -- > Andrew Ip > Email: aip(a)cwlinux.com > Tel: (852) 2542 2046 > Fax: (852) 2542 2036 > Mobile: (852) 9201 9866 > > Cwlinux Limited > Unit 202B 2/F Lai Cheong Factory Building, > 479-479A Castle Peak Road, > Lai Chi Kok, Kowloon, > Hong Kong. > > Tel: (852)2542 2046 > Fax: (852)2542 2036 > > For public pgp key, please obtain it from http://www.keyserver.net/en. >

1 0

RE: ADLO for EPIA
by hcyun＠etri.re.kr 17 Mar '03

17 Mar '03

With current linuxbios for EPIA, I found that internel graphic device (bus 1, dev 0 ) is not visible in the pci configuration space. I have tried to enable this by setting PP_Rx3E and RxA9 registers, but with failed. Do you know how to make it visible? Heechul > In the current cvs tree, vga is not enabled. Have you > enabled it yet? > > -Andrew > > -- > Andrew Ip > Email: aip(a)cwlinux.com > Tel: (852) 2542 2046 > Fax: (852) 2542 2036 > Mobile: (852) 9201 9866 > > Cwlinux Limited > Unit 202B 2/F Lai Cheong Factory Building, > 479-479A Castle Peak Road, > Lai Chi Kok, Kowloon, > Hong Kong. > > Tel: (852)2542 2046 > Fax: (852)2542 2036 > > For public pgp key, please obtain it from http://www.keyserver.net/en. >

2 1

serial console problems
by Alexander Amelkin 16 Mar '03

16 Mar '03

Hello! I already asked, but nobody answered my question. I'm having problems with the serial console when booting LinuxBIOS on a pcchips m787cl+ motherboard. The serial works for output (I can see what the box says) but doesn't for input (I can't login from the serial console). If I boot the same kernel with the same parameters (console=ttyS0,9600n8) using the original motherboard's BIOS (AMI), I don't have any problems at all. Any suggestions? With best regards, Alexander mailto:spirit@reactor.ru

3 2

compiling etherboot
by Alessio Sangalli 16 Mar '03

16 Mar '03

Hi. I'm trying to compile etherboot for linuxbios to boot an image on a ide device. I downloaded both version 5.0.9 and 5.1.7. Would you tell me which targets should I make? What about file system support? bye bye thank you as -- How to build a lirc receiver http://www.manoweb.com/alesan/lirc

1 0

Patch to flash_rom
by SONE Takeshi 16 Mar '03

16 Mar '03

Hi, I modified the flash_rom program a little and it might be useful for others. - Add "enable" for VIA VT8231 (southbridge of EPIA board) This does same thing as what is in src/mainboard/via/epia/README. (Btw, I downloaded the datasheet for VT8231 from here: http://www.google.com/search?q=vt8231+application%2Fpdf It's publically online ;-) - Fixed segfault when no "enable" is defined for a board. - Fixed delay calibration so it really finishes in a second (original code takes up to 100 seconds theoretically, >10 seconds on my box) - Support for -r (read), -w (write), and -v (verify). Writing is not really tested since I don't have my BIOS Savior yet. Looking forward to trying out LinuxBIOS on my box. Thanks for the great work. -- Takeshi Index: flash_rom.c =================================================================== RCS file: /cvsroot/freebios/freebios/util/flash_and_burn/flash_rom.c,v retrieving revision 1.16 diff -u -r1.16 flash_rom.c --- flash_rom.c 28 Feb 2003 17:21:37 -0000 1.16 +++ flash_rom.c 12 Mar 2003 14:03:11 -0000 @@ -136,6 +136,9 @@ new = old | 1; + if (new == old) + return 0; + ok = pci_write_byte(dev, 0x4e, new); if (ok != new) { @@ -146,6 +149,28 @@ return 0; } +int +enable_flash_vt8231(struct pci_dev *dev, char *name) { + unsigned char old, new; + int ok; + + old = pci_read_byte(dev, 0x40); + + new = old | 0x10; + + if (new == old) + return 0; + + ok = pci_write_byte(dev, 0x40, new); + + if (ok != 0) { + printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", + old, new, name); + return -1; + } + return 0; +} + struct flashchip * probe_flash(struct flashchip * flash) { int fd_mem; @@ -227,8 +252,8 @@ timeusec = 1000000 * (end.tv_sec - start.tv_sec ) + (end.tv_usec - start.tv_usec); fprintf(stderr, "timeusec is %d\n", timeusec); - count *= 100; - if (timeusec < 1000000) + count *= 2; + if (timeusec < 1000000/3) continue; ok = 1; } @@ -260,6 +285,7 @@ {0x1, 0x1, "sis630 -- what's the ID?", enable_flash_sis630}, {0x8086, 0x2480, "E7500", enable_flash_e7500}, + {0x1106, 0x8231, "VT8231", enable_flash_vt8231}, }; int @@ -291,10 +317,25 @@ } /* now do the deed. */ - enable->doit(dev, enable->name); + if (enable) { + printf("Enabling flash write on %s...", enable->name); + if (enable->doit(dev, enable->name) == 0) + printf("OK\n"); + } return 0; } +void usage(const char *name) +{ + printf("usage: %s [-rwv] [file]\n", name); + printf("-r: read flash and save into file\n" + "-w: write file into flash (default when file is specified)\n" + "-v: verify flash against file\n" + " If no file is specified, then all that happens\n" + " is that flash info is dumped\n"); + exit(1); +} + int main (int argc, char * argv[]) { @@ -302,12 +343,36 @@ unsigned long size; FILE * image; struct flashchip * flash; - - if (argc > 2){ - printf("usage: %s [romimage]\n", argv[0]); - printf(" If no romimage is specified, then all that happens\n"); - printf(" is that flash info is dumped\n"); + int opt; + int read_it = 0, write_it = 0, verify_it = 0; + char *filename = NULL; + while ((opt = getopt(argc, argv, "rwv")) != EOF) { + switch (opt) { + case 'r': + read_it = 1; + break; + case 'w': + write_it = 1; + break; + case 'v': + verify_it = 1; + break; + default: + usage(argv[0]); + break; + } } + if (read_it && write_it) { + printf("-r and -w are mutually exclusive\n"); + usage(argv[0]); + } + + if (optind < argc) + filename = argv[optind++]; + + printf("Calibrating timer since microsleep sucks ... takes a second\n"); + myusec_calibrate_delay(); + printf("OK, calibrated, now do the deed\n"); /* try to enable it. Failure IS an option, since not all motherboards * really need this to be done, etc., etc. It sucks. @@ -320,25 +385,35 @@ } printf("Part is %s\n", flash->name); - if (argc < 2){ + if (!filename){ printf("OK, only ENABLING flash write, but NOT FLASHING\n"); return 0; } size = flash->total_size * 1024; - - if ((image = fopen (argv[1], "r")) == NULL) { - perror("Error opening image file"); - exit(1); - } - buf = (char *) calloc (size, sizeof(char)); - fread (buf, sizeof(char), size, image); - printf("Calibrating timer since microsleep sucks ... takes a second\n"); - myusec_calibrate_delay(); - printf("OK, calibrated, now do the deed\n"); + if (read_it) { + if ((image = fopen (filename, "w")) == NULL) { + perror("Error opening image file"); + exit(1); + } + printf("Reading Flash..."); + memcpy(buf, (const char *) flash->virt_addr, size); + fwrite(buf, sizeof(char), size, image); + fclose(image); + printf("done\n"); + } else { + if ((image = fopen (filename, "r")) == NULL) { + perror("Error opening image file"); + exit(1); + } + fread (buf, sizeof(char), size, image); + fclose(image); + } - flash->write (flash, buf); - verify_flash (flash, buf, /* verbose = */ 0); + if (write_it) + flash->write (flash, buf); + if (verify_it) + verify_flash (flash, buf, /* verbose = */ 0); return 0; }

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New version of DOC Millennium MD2802-D08
by Andrew Ip 16 Mar '03

16 Mar '03

MD2802-D08 is the new version of MD2800-D08. Basically it is the same with newer packing, and it is working with LinuxBIOS!!! -Andrew -- Andrew Ip Email: aip(a)cwlinux.com Tel: (852) 2542 2046 Fax: (852) 2542 2036 Mobile: (852) 9201 9866 Cwlinux Limited Unit 202B 2/F Lai Cheong Factory Building, 479-479A Castle Peak Road, Lai Chi Kok, Kowloon, Hong Kong. Tel: (852)2542 2046 Fax: (852)2542 2036 For public pgp key, please obtain it from http://www.keyserver.net/en.

1 0

Looking for datasheet of Sis chipset
by Charlie Song 14 Mar '03

14 Mar '03

Hello all, Could anyone provide the datasheet of SiS chipset that supports Intel Pentim 4/3 ? Thanks, Charlie

1 0

problem with udelay solved - romimage too big
by Alessio Sangalli 14 Mar '03

14 Mar '03

Hi, mucking with the source cde and with configuration samples I've solved the compile problem I wrote about yesterday night (udelay) Now I can get a romimage file. I plan to burn this file inside the normal flash of my pcchips 810 board to boot from IDE (hard disk). However, the file romimage is too big! I would have expected a 256KB file, but I obtain a 1.4MB one: $ ll -h payload.block linuxbios.rom romimage -rw-rw-r-- 1 alesan alesan 64k Mar 14 13:31 linuxbios.rom -rw-rw-r-- 1 alesan alesan 1.3M Mar 14 13:31 payload.block -rw-rw-r-- 1 alesan alesan 1.4M Mar 14 13:31 romimage What am I doing wrong? This is the config file: target rom mainboard pcchips/m810lmr cpu k7 option CONFIG_UDELAY_TSC=1 option VIDEO_CONSOLE=1 option SERIAL_CONSOLE=1 option DEFAULT_CONSOLE_LOGLEVEL=6 option SERIAL_POST=1 option ENABLE_MII=1 option MUST_ENABLE_FLOPPY=1 option HAVE_FRAMEBUFFER=1 option SMA_SIZE=0x80 option BOOT_IDE=1 option IDE_BOOT_DRIVE=0 option ONE_TRACK=32 biosbase 0xffff0000 linux /usr/src/linux commandline root=/dev/hda1 console=ttyS0,115200 console=tty0 bye bye thank you as -- How to build a lirc receiver http://www.manoweb.com/alesan/lirc

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coreboot March 2003