coreboot October 2003

coreboot@coreboot.org

52 participants
115 discussions

RE: AMD64: Something's missing?
by Alan Mimms 22 Oct '03

22 Oct '03

One thing that encryption in the bootstrap CAN do is prevent Trojan attacks against the kernel image. If attackers can't find out what the encryption key is they can't create a substitute Trojan kernel. It plugs a hole. Alan Mimms, Senior Architect F5 Networks, Inc. Spokane Development Center Liberty Lake, Washington v: 509-343-3524 f: 509-343-3501 -----Original Message----- From: SONE Takeshi [mailto:ts1@tsn.or.jp] Sent: Wednesday, October 22, 2003 2:18 AM To: Evan Langlois Cc: linuxbios(a)clustermatic.org Subject: Re: AMD64: Something's missing? On Tue, Oct 21, 2003 at 10:26:01PM +0200, Evan Langlois wrote: > > > EtherBoot can boot lots of things from the network or an IDE hard disk. > > FILO can boot from IDE hard disk, IDE CDROM, floppy, and maybe more? 9load > > I don't know much about except that it is used to load the plan9 kernel. > > I don't know much about FILO. Can anyone comment on its compatibility with > the LILO graphical features (displaying graphical menus/splash screens), and > is there any support available for encrypted filesystems? FILO is not aimed at being compatible with LILO. > Assuming FILO works like LILO, and doesn't know about filesystems, I'm > assuming encryption would be difficult, and it might therefore be best to > chain-load another boot-loader, but I'd want the encryption keys to be in the > ROM to make it as difficult as possible to get to them. FILO has filesystem routines borrowed from GRUB, so it works like GRUB rather than LILO. > Encryption in the BIOS itself may be a positive feature, not just for > corporate users that want to protect their IP, but laptop users and such (in > which case the key would be asked for on boot) that don't want sensitive > information leaking out just because a laptop was stolen. Encryption in boot process doesn't make sense to me. What you want to protect is the data in the storage, not the boot image (kernel). Encryption of the storage is OS's bussiness, and the OS will ask you the password before decrypting any data. -- Takeshi _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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[COMMIT] romcc-0.37
by ebiederman＠lnxi.com 22 Oct '03

22 Oct '03

Ok. Non inline function calls are trickier than I expected. My intuition said I just needed to tweak the generated intermediate code and I could reuse all of my optimizing back end. In almost all cases my back end looks at the code generated declares it spaghetti and refuses to compile it. However I did manage a lot of good general cleanups. I believe I have fix the problem with reading ints instead of bytes from structures. I have optimized the code somewhat so sub word size loads can now be into any of the 8 general purpose registers. I have converted practically all the compile time options into run time switches so the code is a little cleaner and more configurable. Before I return to working on non inlining I need to step back and think some more to see which technique will work best. Either improving my code analysis algorithms, or compiling the functions separately and then inserting calls. There are pluses and minuses to both techniques. Hopefully I will be a little more active now that I have come to a stopping place. Eric

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FW: Forth
by Gregg C Levine 21 Oct '03

21 Oct '03

Hello (again) from Gregg C Levine Folks, take a look at the forwarded message below my signature. It seems to me, that it was spawned from my messages discussing the OpenBIOS kernel. I am inviting advice, and comment. I have responded twice to the person, but so far no replies. ------------------- Gregg C Levine hansolofalcon(a)worldnet.att.net ------------------------------------------------------------ "The Force will be with you...Always." Obi-Wan Kenobi "Use the Force, Luke." Obi-Wan Kenobi (This company dedicates this E-Mail to General Obi-Wan Kenobi ) (This company dedicates this E-Mail to Master Yoda ) -----Original Message----- From: werty(a)swissinfo.org [mailto:werty@swissinfo.org] Sent: Monday, October 20, 2003 5:13 AM To: hansolofalcon(a)worldnet.att.net Subject: Forth Read your post on Forth . Where can i get on mailing list. I want to write a DTC Forth for i386 . It will be fast as it has 3 subroutine levels and lowest level is not Called , but the primatives Do have Returns at end ? ha ha They jmp directly to next primative . Stack must be preserved and restored to exit the prim' . ______________________________________________________________________ _ Dreaming of a Swiss Account? Get it here: http://freemail.swissinfo.org

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V2 EPIA - IDE compat mode, RAM init, and early MTRR
by SONE Takeshi 21 Oct '03

21 Oct '03

Attached patch fixes IDE compatibility mode (so FILO works), and RAM initialization, so the DIMM on the second slot works. SPD is not used by this patch, we have to figure out how to type MA mapping by SPD (see the comment in the code). Maybe I will work on SPD-based RAM timing. earlymtrr.c should go to src/cpu/p6 so the XIP works. The change in src/cpu/p6/mtrr.c just reverse the change made by Eric for K8.. -- Takeshi

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AMD8151
by Stefan Reinauer 21 Oct '03

21 Oct '03

Hi, I still don't get the 8151 to work properly on the solo board. i believe that the link setup looks like: Athlon64 | 8151 | 8111 since athlon64 has only one ht link. my config.lb defines: northbridge amd/amdk8 "mc0" southbridge amd/amd8151 "amd8151" link 0 end southbridge amd/amd8111 "amd8111" link [1|2] end end What is the right way of describing how the 8111 is connected in the config? And I only get hangs at: NB: Function 3 Misc Control.. IF I set amd8111 link to 0 I get a reboot plus hang at PCI: 03:00.2 [ffff/ffff] disabled amd8111_enable dev: PCI: 03:01.0 lpc_dev: PCI: 01:05.0 index: 9 reg: fe9f -> fce PCI: 03:01.0 [ffff/ffff] disabled PCI: 03:05.0 [14e4/1645] enabled Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.5.0-Fallback Mo Okt 20 11:35:43 CEST 2003 rebooting... I also noticed that not all elements in the capability linked list of the 8151 are HT capabilities. The first one on 8151 is an AGP capability element. Maybe this explains why a different ordered probing is needed, does LinuxBIOS correctly skip AGP capability blocks? Stefan -- ARCHITECTURE TEAM SUSE LINUX AG

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cpu/p6/mtrr.c
by SONE Takeshi 21 Oct '03

21 Oct '03

Eric, Is the below change intended? EPIA has problem with current CVS (resets when setting var mtrr), and it worked again when I reversed this change. According to the Intel System Programming Manual for PIII, bits 36-63 are reserved, and apparently C3 doesn't like it to be set. black:~/src/freebios2/src/cpu/p6$ cvs diff -u -r1.4 -r1.5 mtrr.c Index: mtrr.c =================================================================== RCS file: /cvsroot/freebios/freebios2/src/cpu/p6/mtrr.c,v retrieving revision 1.4 retrieving revision 1.5 diff -u -r1.4 -r1.5 --- mtrr.c 19 Jul 2003 04:28:21 -0000 1.4 +++ mtrr.c 11 Oct 2003 06:20:17 -0000 1.5 @@ -92,7 +92,7 @@ base.lo = basek << 10; if (sizek < 4*1024*1024) { - mask.hi = 0x0F; + mask.hi = 0x0FF; mask.lo = ~((sizek << 10) -1); } else { -- Takeshi

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Fwd: via datasheets
by Greg Watson 20 Oct '03

20 Oct '03

Can anyone help this guy out? Greg >Status: U >To: jarrah(a)users.sourceforge.net >Subject: via datasheets >From: Yugesh <yugesh(a)users.sourceforge.net> >Cc: <yugesh(a)users.sourceforge.net> >Date: Mon, 20 Oct 2003 13:07:38 -0700 >X-Spam-Score: 0.0 (/) >X-Spam-Report: 0.0/5.0 > Spam Filtering performed by sourceforge.net. > See http://spamassassin.org/tag/ for more details. > Report problems to >https://sf.net/tracker/?func=add&group_id=1&atid=200001 > > >Hi, > > > >I don't know if you are able to help or not... I'm trying to get > >a hold of via datasheets to write some drivers. Specifically I > >need info on the VT8235 southbridge and vt82623 > >northbridge (CLE266 on an epia m10000). > > > >I noticed there was some via / epia code in your freebios > >code. > > > >Do you know where I can obtain information on the via > >chipsets ? > > > >I've tried requesting it from via with no response. > > > >Thanks.!

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Re: EPIA version 2
by Russell Gower 20 Oct '03

20 Oct '03

----- Original Message ----- From: "ron minnich" <rminnich(a)lanl.gov> To: "Russell Gower" <russell(a)abc9986.demon.co.uk> Cc: "LinuxBIOS" <linuxbios(a)clustermatic.org> Sent: Sunday, October 12, 2003 4:42 PM Subject: Re: EPIA version 2 > On Sat, 11 Oct 2003, Russell Gower wrote: > > > I'm currently using the v1 tree for my EPIA based project, it looks like > > it's time for me to move over to the v2 tree. Is there any instructions on > > how to build linuxbios from the v2 tree? > > > > cd freebios2/targets > ./buildtarget via/epia > > that's a start to see how it is done. > > ron > > When I do that I get the following output. Traceback (innermost last): File "/home/russell/linuxbios/freebios2/targets/epia/config.py", line 2289, in ? if (not parse('board', fp.read())): File "/home/russell/linuxbios/freebios2/targets/epia/config.py", line 1923, in parse return wrap_error_reporter(P, rule) File "/home/russell/linuxbios/freebios2/util/newconfig/yappsrt.py", line 162, in wrap_error_reporter try: return getattr(parser, rule)() File "/home/russell/linuxbios/freebios2/targets/epia/config.py", line 1850, in board loadoptions() File "/home/russell/linuxbios/freebios2/targets/epia/config.py", line 1004, in loadoptions if (not parse('options', fp.read())): File "/home/russell/linuxbios/freebios2/targets/epia/config.py", line 1923, in parse return wrap_error_reporter(P, rule) File "/home/russell/linuxbios/freebios2/util/newconfig/yappsrt.py", line 162, in wrap_error_reporter try: return getattr(parser, rule)() File "/home/russell/linuxbios/freebios2/targets/epia/config.py", line 1916, in options define = self.define() File "/home/russell/linuxbios/freebios2/targets/epia/config.py", line 1910, in define defstmts = self.defstmts(ID) File "/home/russell/linuxbios/freebios2/targets/epia/config.py", line 1876, in defstmts value = self.value() File "/home/russell/linuxbios/freebios2/targets/epia/config.py", line 1748, in value expr = self.expr() File "/home/russell/linuxbios/freebios2/targets/epia/config.py", line 1350, in expr logical = self.logical() File "/home/russell/linuxbios/freebios2/targets/epia/config.py", line 1365, in logical factor = self.factor() File "/home/russell/linuxbios/freebios2/targets/epia/config.py", line 1380, in factor term = self.term() File "/home/russell/linuxbios/freebios2/targets/epia/config.py", line 1406, in term return long(NUM, 10) TypeError: long requires exactly 1 argument; 2 given Russell.

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New to LinuxBIOS - PIII?
by Evan Langlois 17 Oct '03

17 Oct '03

Hi, I'm new to the list, and haven't really had a chance to read through all the archives. But, perhaps someone can give me a recommendation. We're considering using LinuxBIOS for various reasons (well, I am), however looking at the web site and vendor list is a bit disappointing. I'm a bit concerned about long-term availability since most motherboards marked as "stable" are already at the end of their lifecycle. I'm hoping that list is outdated. We (err ... I) would be willing to do minor coding to help the project, and maybe help out in other ways, but unfortuneately, I simply don't have the time or experience in the sort of low-level coding required to be of any practical use. Doing a port to another board is probably beyond my capability at the moment, and I certainly have plenty of other projects. Basically, I'm hoping to get LinuxBIOS into a reliable, server-grade Pentium III (or better) motherboard that can handle a 1+ Ghz CPU. Preferably with dual Intel NICs on-board. I know, I'm asking way too much. From there, I'd like to customize the kernel in the ROM to provide encrypted hard disk support (likely an IDE Flash drive), and loading our software from an encrypted drive so people can't yank out the drive and read it. If anyone has suggestions or recommendations, I'd certainly appreciate it. Thank you, Evan Langlois

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(fwd) Re: Epox Boards [sachse@gmx.net]
by Stefan Reinauer 17 Oct '03

17 Oct '03

Does anyone know whether these work? ----- Forwarded message from Mark-Andres Hohm <sachse(a)gmx.net> ----- Date: Wed, 15 Oct 2003 19:48:34 +0200 From: Mark-Andres Hohm <sachse(a)gmx.net> To: Stefan Reinauer <stepan(a)suse.de> Subject: Re: Epox Boards -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Stefan Reinauer wrote: | * Mark-Andres Hohm <sachse(a)gmx.net> [031013 20:59]: | |>-----BEGIN PGP SIGNED MESSAGE----- |>Hash: SHA1 |> |>Have anyone expirience with Epox board and linuxbios? | | | _Which_ Epox board? Can you send lspci -vvv? | | Stefan here are the lspci from the epox kta3pro this have to work with linux and win 00:00.0 Host bridge: VIA Technologies, Inc. VT8363/8365 [KT133/KM133] (rev 03) ~ Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- ~ Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- ~ Latency: 8 ~ Region 0: Memory at d0000000 (32-bit, prefetchable) [size=32M] ~ Capabilities: [a0] AGP version 2.0 ~ Status: RQ=31 SBA+ 64bit- FW+ Rate=x1,x2,x4 ~ Command: RQ=0 SBA- AGP- 64bit- FW- Rate=<none> ~ Capabilities: [c0] Power Management version 2 ~ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) ~ Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:01.0 PCI bridge: VIA Technologies, Inc. VT8363/8365 [KT133/KM133 AGP] (prog-if 00 [Normal decode]) ~ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- ~ Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- ~ Latency: 0 ~ Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 ~ I/O behind bridge: 0000f000-00000fff ~ Memory behind bridge: d4000000-d5ffffff ~ Prefetchable memory behind bridge: d2000000-d3ffffff ~ BridgeCtl: Parity- SERR- NoISA+ VGA+ MAbort- >Reset- FastB2B- ~ Capabilities: [80] Power Management version 2 ~ Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) ~ Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:07.0 ISA bridge: VIA Technologies, Inc. VT82C686 [Apollo Super South] (rev 40) ~ Subsystem: VIA Technologies, Inc. VT82C686/A PCI to ISA Bridge ~ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- ~ Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- ~ Latency: 0 ~ Capabilities: [c0] Power Management version 2 ~ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) ~ Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:07.1 IDE interface: VIA Technologies, Inc. VT82C586/B/VT82C686/A/B/VT8233/A/C/VT8235 PIPC Bus Master IDE (rev 06) (prog-if 8a [Master SecP PriP]) ~ Subsystem: VIA Technologies, Inc. VT82C586/B/VT82C686/A/B/VT8233/A/C/VT8235 PIPC Bus Master IDE ~ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- ~ Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- ~ Latency: 32 ~ Region 4: I/O ports at 9000 [size=16] ~ Capabilities: [c0] Power Management version 2 ~ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) ~ Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:07.2 USB Controller: VIA Technologies, Inc. USB (rev 16) (prog-if 00 [UHCI]) ~ Subsystem: VIA Technologies, Inc. (Wrong ID) USB Controller ~ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- ~ Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- ~ Latency: 32, cache line size 08 ~ Interrupt: pin D routed to IRQ 11 ~ Region 4: I/O ports at 9400 [size=32] ~ Capabilities: [80] Power Management version 2 ~ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) ~ Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:07.4 Bridge: VIA Technologies, Inc. VT82C686 [Apollo Super ACPI] (rev 40) ~ Subsystem: VIA Technologies, Inc. VT82C686 [Apollo Super ACPI] ~ Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- ~ Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- ~ Interrupt: pin ? routed to IRQ 9 ~ Capabilities: [68] Power Management version 2 ~ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) ~ Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:07.5 Multimedia audio controller: VIA Technologies, Inc. VT82C686 AC97 Audio Controller (rev 50) ~ Subsystem: VIA Technologies, Inc. Onboard Audio on EP7KXA ~ Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- ~ Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- ~ Interrupt: pin C routed to IRQ 5 ~ Region 0: I/O ports at 9c00 [size=256] ~ Region 1: I/O ports at a000 [size=4] ~ Region 2: I/O ports at a400 [size=4] ~ Capabilities: [c0] Power Management version 2 ~ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) ~ Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:09.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10) ~ Subsystem: Allied Telesyn International AT-2500TX/ACPI ~ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- ~ Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- ~ Latency: 32 (8000ns min, 16000ns max) ~ Interrupt: pin A routed to IRQ 10 ~ Region 0: I/O ports at a800 [size=256] ~ Region 1: Memory at d7001000 (32-bit, non-prefetchable) [size=256] ~ Capabilities: [50] Power Management version 1 ~ Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) ~ Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:0b.0 SCSI storage controller: Adaptec AHA-2940U/UW/D / AIC-7881U ~ Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- ~ Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- ~ Latency: 32 (2000ns min, 2000ns max), cache line size 08 ~ Interrupt: pin A routed to IRQ 11 ~ Region 0: I/O ports at ac00 [disabled] [size=256] ~ Region 1: Memory at d7000000 (32-bit, non-prefetchable) [size=4K] ~ Expansion ROM at <unassigned> [disabled] [size=64K] 00:0e.0 Unknown mass storage controller: Triones Technologies, Inc. HPT366/368/370/370A/372 (rev 04) ~ Subsystem: Triones Technologies, Inc. HPT370A ~ Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- ~ Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- ~ Latency: 120 (2000ns min, 2000ns max) ~ Interrupt: pin A routed to IRQ 10 ~ Region 0: I/O ports at b000 [size=8] ~ Region 1: I/O ports at b400 [size=4] ~ Region 2: I/O ports at b800 [size=8] ~ Region 3: I/O ports at bc00 [size=4] ~ Region 4: I/O ports at c000 [size=256] ~ Expansion ROM at <unassigned> [disabled] [size=128K] ~ Capabilities: [60] Power Management version 2 ~ Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) ~ Status: D0 PME-Enable- DSel=0 DScale=0 PME- 01:00.0 VGA compatible controller: nVidia Corporation NV5M64 [RIVA TNT2 Model 64/Model 64 Pro] (rev 15) (prog-if 00 [VGA]) ~ Subsystem: CardExpert Technology: Unknown device 0000 ~ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- ~ Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- ~ Latency: 32 (1250ns min, 250ns max) ~ Interrupt: pin A routed to IRQ 12 ~ Region 0: Memory at d4000000 (32-bit, non-prefetchable) [size=16M] ~ Region 1: Memory at d2000000 (32-bit, prefetchable) [size=32M] ~ Expansion ROM at <unassigned> [disabled] [size=64K] ~ Capabilities: [60] Power Management version 1 ~ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) ~ Status: D0 PME-Enable- DSel=0 DScale=0 PME- ~ Capabilities: [44] AGP version 2.0 ~ Status: RQ=31 SBA- 64bit- FW- Rate=x1,x2,x4 ~ Command: RQ=0 SBA- AGP- 64bit- FW- Rate=<none> - --------------------------------------------------------------------------------- here are the log from my 2nd board which is only wors with linux because ist the router. its a epox 8k9a. 00:00.0 Host bridge: VIA Technologies, Inc. VT8377 [KT400 AGP] Host Bridge ~ Subsystem: VIA Technologies, Inc. VT8377 [KT400 AGP] Host Bridge ~ Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- ~ Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- ~ Latency: 8 ~ Region 0: Memory at d0000000 (32-bit, prefetchable) [size=128M] ~ Capabilities: [a0] AGP version 2.0 ~ Status: RQ=31 SBA+ 64bit- FW- Rate=x1,x2,x4 ~ Command: RQ=31 SBA- AGP- 64bit- FW- Rate=<none> ~ Capabilities: [c0] Power Management version 2 ~ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) ~ Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:01.0 PCI bridge: VIA Technologies, Inc. VT8235 PCI Bridge (prog-if 00 [Normal decode]) ~ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- ~ Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- ~ Latency: 0 ~ Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 ~ I/O behind bridge: 00009000-00009fff ~ Memory behind bridge: dc000000-ddffffff ~ Prefetchable memory behind bridge: d8000000-dbffffff ~ BridgeCtl: Parity- SERR- NoISA+ VGA+ MAbort- >Reset- FastB2B- ~ Capabilities: [80] Power Management version 2 ~ Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) ~ Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:0b.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10) ~ Subsystem: Realtek Semiconductor Co., Ltd. RT8139 ~ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- ~ Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- ~ Latency: 32 (8000ns min, 16000ns max) ~ Interrupt: pin A routed to IRQ 19 ~ Region 0: I/O ports at a000 [size=256] ~ Region 1: Memory at df001000 (32-bit, non-prefetchable) [size=256] 00:0d.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10) ~ Subsystem: Realtek Semiconductor Co., Ltd. RT8139 ~ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- ~ Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- ~ Latency: 32 (8000ns min, 16000ns max) ~ Interrupt: pin A routed to IRQ 19 ~ Region 0: I/O ports at a400 [size=256] ~ Region 1: Memory at df000000 (32-bit, non-prefetchable) [size=256] 00:0e.0 RAID bus controller: Triones Technologies, Inc. HPT374 (rev 07) ~ Subsystem: Triones Technologies, Inc.: Unknown device 0001 ~ Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- ~ Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- ~ Latency: 120 (2000ns min, 2000ns max) ~ Interrupt: pin A routed to IRQ 17 ~ Region 0: I/O ports at a800 [size=8] ~ Region 1: I/O ports at ac00 [size=4] ~ Region 2: I/O ports at b000 [size=8] ~ Region 3: I/O ports at b400 [size=4] ~ Region 4: I/O ports at b800 [size=256] ~ Expansion ROM at <unassigned> [disabled] [size=128K] ~ Capabilities: [60] Power Management version 2 ~ Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) ~ Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:0e.1 RAID bus controller: Triones Technologies, Inc. HPT374 (rev 07) ~ Subsystem: Triones Technologies, Inc.: Unknown device 0001 ~ Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- ~ Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- ~ Latency: 120 (2000ns min, 2000ns max) ~ Interrupt: pin A routed to IRQ 17 ~ Region 0: I/O ports at bc00 [size=8] ~ Region 1: I/O ports at c000 [size=4] ~ Region 2: I/O ports at c400 [size=8] ~ Region 3: I/O ports at c800 [size=4] ~ Region 4: I/O ports at cc00 [size=256] ~ Capabilities: [60] Power Management version 2 ~ Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) ~ Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:11.0 ISA bridge: VIA Technologies, Inc. VT8235 ISA Bridge ~ Subsystem: VIA Technologies, Inc. VT8235 ISA Bridge ~ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- ~ Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- ~ Latency: 0 ~ Capabilities: [c0] Power Management version 2 ~ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) ~ Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:11.1 IDE interface: VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT8233/A/C/VT8235 PIPC Bus Master IDE (rev 06) (prog-if 8a [Master SecP PriP]) ~ Subsystem: Unknown device 1695:3005 ~ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- ~ Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- ~ Latency: 32 ~ Interrupt: pin A routed to IRQ 255 ~ Region 4: I/O ports at dc00 [size=16] ~ Capabilities: [c0] Power Management version 2 ~ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) ~ Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:11.5 Multimedia audio controller: VIA Technologies, Inc. VT8233/A/8235 AC97 Audio Controller (rev 50) ~ Subsystem: Unknown device 1695:3005 ~ Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- ~ Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- ~ Interrupt: pin C routed to IRQ 12 ~ Region 0: I/O ports at e000 [size=256] ~ Capabilities: [c0] Power Management version 2 ~ Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) ~ Status: D0 PME-Enable- DSel=0 DScale=0 PME- 01:00.0 VGA compatible controller: ATI Technologies Inc Rage 128 PF/PRO AGP 4x TMDS (prog-if 00 [VGA]) ~ Subsystem: Giga-byte Technology: Unknown device 4005 ~ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- ~ Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- ~ Latency: 32 (2000ns min), cache line size 08 ~ Interrupt: pin A routed to IRQ 16 ~ Region 0: Memory at d8000000 (32-bit, prefetchable) [size=64M] ~ Region 1: I/O ports at 9000 [size=256] ~ Region 2: Memory at dd000000 (32-bit, non-prefetchable) [size=16K] ~ Expansion ROM at <unassigned> [disabled] [size=128K] ~ Capabilities: [50] AGP version 2.0 ~ Status: RQ=31 SBA+ 64bit- FW- Rate=x1,x2,x4 ~ Command: RQ=0 SBA+ AGP- 64bit- FW- Rate=<none> ~ Capabilities: [5c] Power Management version 2 ~ Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) ~ Status: D0 PME-Enable- DSel=0 DScale=0 PME- -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.2.1 (GNU/Linux) iD8DBQE/jYhuPC4Ugo8dWvcRAkaHAJ41qrX/dERy2uuSfPhkyD3mmMQ94wCfasJd k6skYq275YuYv92I5Ct/bUc= =aty1 -----END PGP SIGNATURE----- ----- End forwarded message ----- Best regards, Stefan Reinauer -- Architecture Team SuSE Linux AG

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coreboot October 2003