Hi Marc,
(CC to list)
On Thu, Sep 13, 2007 at 06:33:17PM -0600, Marc Jones wrote:
Uwe Hermann wrote:
Hi,
here's my first try with the K9N. It took me a while to figure out how to make serial work (the Super I/O is at 0x4e on this board, and you need a small hack to switch to 24MHz, see patch), but that part works fine now.
0x4e is not unusual for the SIO decode.
Yep, but it seems that's what the BIOS does. I verified with superiotool (I added W83627EHG support, patch pending).
You should check and see if the pcbios sets 24Mhz or 48Mhz. I would set it up the same as they do. There should be a bit for half clock divisor on the serial port instead of changing the clock.
Ah, yes, CR 0xF0 (page 102 in the datasheet) looks like the register I need. I'll try that.
However, the BIOS indeed sets the clock speed to 24MHz (CR 0x24, bit 6 was set to zero when I checked).
I suspect that this is the SPD address is different.
How do I find out the correct one? i2cdetect/i2cdump?
Uwe.
Uwe Hermann wrote:
Hi Marc,
...
I suspect that this is the SPD address is different.
How do I find out the correct one? i2cdetect/i2cdump?
Uwe.
I think that a scan with i2cdump would be your best bet. Marc
On Fri, Sep 14, 2007 at 01:31:48PM -0600, Marc Jones wrote:
I suspect that this is the SPD address is different.
How do I find out the correct one? i2cdetect/i2cdump?
I think that a scan with i2cdump would be your best bet.
It turns out the code was working already, it's just that some combination of RAM slots and number of DIMMs don't work. I think there was a posting about that in the past, but I can't seem to find it.
When I use only one DIMM, it works just fine. I'll investigate the exact circumstances when it works or doesn't work. Or is it a K8 or MCP55 requirement to have only _one_ DIMM populated (in LinuxBIOS at least)? If so, how can we fix it?
Uwe.
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Marc Jones -
Uwe Hermann