r3205 - in trunk/coreboot-v2/src/southbridge/intel: esb6300 i3100 i82801ca i82801db i82801dbm i82801er
Author: eswierk Date: 2008-04-01 04:36:59 +0200 (Tue, 01 Apr 2008) New Revision: 3205
Modified: trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_early_smbus.c trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_smbus.c trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_early_smbus.c trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_early_smbus.c Log: The early init code of several Intel southbridge chipsets calls pci_locate_device() to locate the SMBus controller and LPC bridge devices on the PCI bus. Since these devices are always located at a fixed PCI bus:device:function, the code can be simplified by hardcoding the devices.
Signed-off-by: Ed Swierk eswierk@arastra.com Acked-by: Corey Osgood corey.osgood@gmail.com
Modified: trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_early_smbus.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_early_smbus.c 2008-03-31 21:02:29 UTC (rev 3204) +++ trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_early_smbus.c 2008-04-01 02:36:59 UTC (rev 3205) @@ -4,12 +4,8 @@
static void enable_smbus(void) { - device_t dev; - dev = pci_locate_device(PCI_ID(0x8086, 0x25a4), 0); - if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); - } - uint8_t enable; + device_t dev = PCI_DEV(0x0, 0x1f, 0x3); + print_spew("SMBus controller enabled\r\n"); pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); pci_write_config8(dev, 0x40, 1); @@ -19,11 +15,6 @@ /* Disable interrupt generation */ outb(0, SMBUS_IO_BASE + SMBHSTCTL); - - dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); - if (dev == PCI_DEV_INVALID) { - die("ISA bridge not found\r\n"); - } }
static int smbus_read_byte(unsigned device, unsigned address)
Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c 2008-03-31 21:02:29 UTC (rev 3204) +++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c 2008-04-01 02:36:59 UTC (rev 3205) @@ -20,12 +20,7 @@
static void i3100_enable_superio(void) { - device_t dev; - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, - PCI_DEVICE_ID_INTEL_3100_LPC), 0); - if (dev == PCI_DEV_INVALID) { - die("LPC bridge not found\r\n"); - } + device_t dev = PCI_DEV(0x0, 0x1f, 0x0);
/* Enable decoding of I/O locations for SuperIO devices */ pci_write_config16(dev, 0x82, 0x340f); @@ -33,12 +28,7 @@
static void i3100_halt_tco_timer(void) { - device_t dev; - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, - PCI_DEVICE_ID_INTEL_3100_LPC), 0); - if (dev == PCI_DEV_INVALID) { - die("LPC bridge not found\r\n"); - } + device_t dev = PCI_DEV(0, 0x1f, 0);
/* Temporarily enable the ACPI I/O range at 0x4000 */ pci_write_config32(dev, 0x40, 0x4000 | (1 << 0));
Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_smbus.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_smbus.c 2008-03-31 21:02:29 UTC (rev 3204) +++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_smbus.c 2008-04-01 02:36:59 UTC (rev 3205) @@ -24,12 +24,8 @@
static void enable_smbus(void) { - device_t dev; - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, - PCI_DEVICE_ID_INTEL_3100_SMB), 0); - if (dev == PCI_DEV_INVALID) { - die("SMBus controller not found\r\n"); - } + device_t dev = PCI_DEV(0x0, 0x1f, 0x3); + print_spew("SMBus controller enabled\r\n"); pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); pci_write_config8(dev, 0x40, 1);
Modified: trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c 2008-03-31 21:02:29 UTC (rev 3204) +++ trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c 2008-04-01 02:36:59 UTC (rev 3205) @@ -3,12 +3,8 @@
static void enable_smbus(void) { - device_t dev; - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_SMB), 0); - if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); - } - + device_t dev = PCI_DEV(0x0, 0x1f, 0x3); + print_debug("SMBus controller enabled\r\n"); /* set smbus iobase */ pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
Modified: trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_early_smbus.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_early_smbus.c 2008-03-31 21:02:29 UTC (rev 3204) +++ trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_early_smbus.c 2008-04-01 02:36:59 UTC (rev 3205) @@ -22,13 +22,10 @@
static void enable_smbus(void) { - device_t dev; - dev = pci_locate_device(PCI_ID(0x8086, 0x24d3), 0); - if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); - } + device_t dev = PCI_DEV(0x0, 0x1f, 0x3); + print_spew("SMBus controller enabled\r\n"); - + pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); /* Set smbus enable */ pci_write_config8(dev, 0x40, 1); @@ -36,19 +33,12 @@ pci_write_config8(dev, 0x4, 1); /* SMBALERT_DIS */ pci_write_config8(dev, 0x11, 4); - + /* Disable interrupt generation */ outb(0, SMBUS_IO_BASE + SMBHSTCTL);
/* clear any lingering errors, so the transaction will run */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - -#if 0 // It's unlikely that half the southbridge suddenly vanishes? - dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); - if (dev == PCI_DEV_INVALID) { - die("ISA bridge not found\r\n"); - } -#endif }
static int smbus_read_byte(unsigned device, unsigned address)
Modified: trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c 2008-03-31 21:02:29 UTC (rev 3204) +++ trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c 2008-04-01 02:36:59 UTC (rev 3205) @@ -21,12 +21,8 @@
static void enable_smbus(void) { - device_t dev; - dev = pci_locate_device(PCI_ID(0x8086, 0x24c3), 0); - if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); - } - + device_t dev = PCI_DEV(0x0, 0x1f, 0x3); + print_debug("SMBus controller enabled\r\n"); /* set smbus iobase */ pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
Modified: trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_early_smbus.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_early_smbus.c 2008-03-31 21:02:29 UTC (rev 3204) +++ trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_early_smbus.c 2008-04-01 02:36:59 UTC (rev 3205) @@ -4,13 +4,10 @@
static void enable_smbus(void) { - device_t dev; - dev = pci_locate_device(PCI_ID(0x8086, 0x24d3), 0); - if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); - } + device_t dev = PCI_DEV(0x0, 0x1f, 0x3); + print_spew("SMBus controller enabled\r\n"); - + pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); /* Set smbus enable */ pci_write_config8(dev, 0x40, 1); @@ -18,19 +15,12 @@ pci_write_config8(dev, 0x4, 1); /* SMBALERT_DIS */ pci_write_config8(dev, 0x11, 4); - + /* Disable interrupt generation */ outb(0, SMBUS_IO_BASE + SMBHSTCTL);
/* clear any lingering errors, so the transaction will run */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - -#if 0 // It's unlikely that half the southbridge suddenly vanishes? - dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); - if (dev == PCI_DEV_INVALID) { - die("ISA bridge not found\r\n"); - } -#endif }
static int smbus_read_byte(unsigned device, unsigned address)
-
svn＠coreboot.org