It mostly looks like fspm parameters are incorrect for memory init. Can you please attach coreboot logs?
Regards, Naresh G Solanki
On Fri 30 Nov, 2018, 2:50 AM roman perepelitsin < email@example.com wrote:
Hi! I'm try to run Coreboot on Intel Xeon1505L with C236 and DDR4 memory down using kabylake FSP GOLD. I setup UART0 for coreboot console out and try to set UART0 for FSP-M debug out, but have only POST codes to port80/81 from FSP-M. In FSP integration guide I didn't find full POST-codes describe. So - can some body help with this? My lasts post codes: DD46h DD30h DD32h DD35h DD45h DD36h DD37h DD41h DD4Dh DD3fh. I think it MRC codes, but that they mean - don't know. I see in oscilloscope, that DDR try to start in this stage, but after all I have error from FSP-M 80000007h.
-- regards, Perepelitsin Roman -- coreboot mailing list: firstname.lastname@example.org https://mail.coreboot.org/mailman/listinfo/coreboot