Hi List,
This patch series contains two patches. The first fixes building coreboot with multiple jobs (The -jX option in make). When building coreboot without a build/ directory, the coreboot.pre target fails to build, as build/config.h doesn't exist at that stage.
The second patch is rather intrusive, as it changes the way how devicetree.cb files are parsed. Right now, they are passed directly to sconfig for processing. This patch changes that behaviour in a way that cpp is run before passing it to sconfig.
This has the advantage that we can use config.h definitions for building a devicetree based on kconfig choices - which is usefull for example in the Thinkpad T60 port i'm preparing right now. The motherboard of the T60 can have three different Graphic chips: Intel GMA, Radeon X1300, and FireGL V5200. With this patch, we can have the user to select the right Adapter, and include only the relevant parts from devicetree.cb by using #ifdef/#endif directives.
The bad thing about this patch is, that '#' can't be used for comments, so the patch also changes all comments to use '//' which is valid for passing it through cpp.
I have to review all the comment changes, but i want to post that patch early for discussion.
Sven.
Signed-off-by: Sven Schnelle svens@stackframe.org --- Makefile.inc | 2 +- src/arch/x86/Makefile.inc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Makefile.inc b/Makefile.inc index 54d472a..3f553c6 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -61,7 +61,7 @@ romstage-c-deps:=$$(OPTION_TABLE_H) ####################################################################### # Add handler to compile ACPI's ASL define ramstage-objs_asl_template -$(obj)/$(1).ramstage.o: src/$(1).asl +$(obj)/$(1).ramstage.o: src/$(1).asl $(obj)/config.h @printf " IASL $$(subst $(top)/,,$$(@))\n" $(CPP) -MMD -MT $$(@) -D__ACPI__ -P -include $(abspath $(obj)/config.h) -I$(src) -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$@).asl iasl -p $$(obj)/$(1) -tc $$(basename $$@).asl diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index afdcb9e..98498e0 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -227,7 +227,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR) @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD $(CFLAGS) -I$(src) -I. -I$(obj) -c $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@
-$(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h +$(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h @printf " CC romstage.inc\n" $(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@
pass devicetree.cb trough cpp before parse it with sconfig. This has the advantage that we can use Kconfig variables in devicetree.cb.
Signed-off-by: Sven Schnelle svens@stackframe.org --- Makefile.inc | 8 +- src/mainboard/a-trend/atc-6220/devicetree.cb | 50 ++-- src/mainboard/a-trend/atc-6240/devicetree.cb | 56 ++-- src/mainboard/abit/be6-ii_v2_0/devicetree.cb | 50 ++-- src/mainboard/advantech/pcm-5820/devicetree.cb | 52 ++-- src/mainboard/amd/bimini_fam10/devicetree.cb | 142 ++++++------ src/mainboard/amd/db800/devicetree.cb | 56 ++-- src/mainboard/amd/dbm690t/devicetree.cb | 118 +++++----- src/mainboard/amd/inagua/devicetree.cb | 126 +++++----- src/mainboard/amd/mahogany/devicetree.cb | 124 +++++----- src/mainboard/amd/mahogany_fam10/devicetree.cb | 160 ++++++------ src/mainboard/amd/norwich/devicetree.cb | 38 ++-- src/mainboard/amd/persimmon/devicetree.cb | 140 ++++++------ src/mainboard/amd/pistachio/devicetree.cb | 100 ++++---- src/mainboard/amd/rumba/devicetree.cb | 16 +- src/mainboard/amd/serengeti_cheetah/devicetree.cb | 94 ++++---- .../amd/serengeti_cheetah_fam10/devicetree.cb | 120 +++++----- src/mainboard/amd/tilapia_fam10/devicetree.cb | 160 ++++++------ src/mainboard/arima/hdama/devicetree.cb | 222 +++++++++--------- src/mainboard/artecgroup/dbe61/devicetree.cb | 38 ++-- src/mainboard/asi/mb_5blgp/devicetree.cb | 46 ++-- src/mainboard/asi/mb_5blmp/devicetree.cb | 38 ++-- src/mainboard/asrock/939a785gmh/devicetree.cb | 136 +++++----- src/mainboard/asrock/e350m1/devicetree.cb | 144 ++++++------ src/mainboard/asus/a8n_e/devicetree.cb | 112 +++++----- src/mainboard/asus/a8v-e_deluxe/devicetree.cb | 84 +++--- src/mainboard/asus/a8v-e_se/devicetree.cb | 84 +++--- src/mainboard/asus/m2n-e/devicetree.cb | 140 ++++++------ src/mainboard/asus/m2v-mx_se/devicetree.cb | 76 +++--- src/mainboard/asus/m2v/devicetree.cb | 76 +++--- src/mainboard/asus/m4a78-em/devicetree.cb | 106 ++++---- src/mainboard/asus/m4a785-m/devicetree.cb | 106 ++++---- src/mainboard/asus/mew-am/devicetree.cb | 52 ++-- src/mainboard/asus/mew-vm/devicetree.cb | 40 ++-- src/mainboard/asus/p2b-d/devicetree.cb | 54 ++-- src/mainboard/asus/p2b-ds/devicetree.cb | 56 ++-- src/mainboard/asus/p2b-f/devicetree.cb | 50 ++-- src/mainboard/asus/p2b-ls/devicetree.cb | 52 ++-- src/mainboard/asus/p2b/devicetree.cb | 50 ++-- src/mainboard/asus/p3b-f/devicetree.cb | 50 ++-- src/mainboard/axus/tc320/devicetree.cb | 46 ++-- src/mainboard/azza/pt-6ibd/devicetree.cb | 50 ++-- src/mainboard/bcom/winnet100/devicetree.cb | 46 ++-- src/mainboard/bcom/winnetp680/devicetree.cb | 70 +++--- src/mainboard/biostar/m6tba/devicetree.cb | 44 ++-- src/mainboard/broadcom/blast/devicetree.cb | 130 +++++----- .../compaq/deskpro_en_sff_p600/devicetree.cb | 50 ++-- src/mainboard/dell/s1850/devicetree.cb | 24 +- src/mainboard/digitallogic/adl855pc/devicetree.cb | 44 ++-- src/mainboard/digitallogic/msm586seg/devicetree.cb | 8 +- src/mainboard/digitallogic/msm800sev/devicetree.cb | 60 +++--- src/mainboard/eaglelion/5bcm/devicetree.cb | 26 +- src/mainboard/ecs/p6iwp-fe/devicetree.cb | 88 ++++---- src/mainboard/emulation/qemu-x86/devicetree.cb | 6 +- src/mainboard/getac/p470/devicetree.cb | 160 ++++++------ src/mainboard/gigabyte/ga-6bxc/devicetree.cb | 44 ++-- src/mainboard/gigabyte/ga-6bxe/devicetree.cb | 44 ++-- src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb | 86 ++++---- src/mainboard/gigabyte/m57sli/devicetree.cb | 190 +++++++------- src/mainboard/gigabyte/ma785gmt/devicetree.cb | 106 ++++---- src/mainboard/gigabyte/ma78gm/devicetree.cb | 108 ++++---- src/mainboard/hp/dl145_g1/devicetree.cb | 100 ++++---- src/mainboard/hp/dl145_g3/devicetree.cb | 76 +++--- src/mainboard/hp/dl165_g6_fam10/devicetree.cb | 76 +++--- src/mainboard/hp/e_vectra_p2706t/devicetree.cb | 58 +++--- src/mainboard/ibase/mb899/devicetree.cb | 100 ++++---- src/mainboard/ibm/e325/devicetree.cb | 30 ++-- src/mainboard/ibm/e326/devicetree.cb | 32 ++-- src/mainboard/iei/juki-511p/devicetree.cb | 34 ++-- src/mainboard/iei/kino-780am2-fam10/devicetree.cb | 82 +++--- src/mainboard/iei/nova4899r/devicetree.cb | 44 ++-- src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb | 66 +++--- src/mainboard/intel/d810e2cb/devicetree.cb | 92 ++++---- src/mainboard/intel/d945gclf/devicetree.cb | 110 ++++---- src/mainboard/intel/eagleheights/devicetree.cb | 56 ++-- src/mainboard/intel/jarrell/devicetree.cb | 16 +- src/mainboard/intel/mtarvon/devicetree.cb | 42 ++-- src/mainboard/intel/truxton/devicetree.cb | 42 ++-- src/mainboard/intel/xe7501devkit/devicetree.cb | 70 +++--- src/mainboard/iwave/iWRainbowG6/devicetree.cb | 30 ++-- src/mainboard/iwill/dk8_htx/devicetree.cb | 72 +++--- src/mainboard/iwill/dk8s2/devicetree.cb | 38 ++-- src/mainboard/iwill/dk8x/devicetree.cb | 18 +- src/mainboard/jetway/j7f24/devicetree.cb | 66 +++--- src/mainboard/jetway/pa78vm5/devicetree.cb | 104 ++++---- src/mainboard/kontron/986lcd-m/devicetree.cb | 104 ++++---- src/mainboard/kontron/kt690/devicetree.cb | 130 +++++----- src/mainboard/lanner/em8510/devicetree.cb | 42 ++-- src/mainboard/lenovo/x60/devicetree.cb | 109 +++++---- src/mainboard/lenovo/x60/romstage.c | 11 +- src/mainboard/lippert/frontrunner/devicetree.cb | 10 +- src/mainboard/lippert/hurricane-lx/devicetree.cb | 82 +++--- src/mainboard/lippert/literunner-lx/devicetree.cb | 76 +++--- src/mainboard/lippert/roadrunner-lx/devicetree.cb | 82 +++--- src/mainboard/lippert/spacerunner-lx/devicetree.cb | 82 +++--- src/mainboard/mitac/6513wu/devicetree.cb | 94 ++++---- src/mainboard/msi/ms6119/devicetree.cb | 50 ++-- src/mainboard/msi/ms6147/devicetree.cb | 50 ++-- src/mainboard/msi/ms6156/devicetree.cb | 90 ++++---- src/mainboard/msi/ms6178/devicetree.cb | 94 ++++---- src/mainboard/msi/ms7135/devicetree.cb | 70 +++--- src/mainboard/msi/ms7260/devicetree.cb | 192 +++++++------- src/mainboard/msi/ms9185/devicetree.cb | 104 ++++---- src/mainboard/msi/ms9282/devicetree.cb | 168 +++++++------- src/mainboard/msi/ms9652_fam10/devicetree.cb | 216 ++++++++-------- src/mainboard/nec/powermate2000/devicetree.cb | 46 ++-- src/mainboard/newisys/khepri/devicetree.cb | 30 ++-- src/mainboard/nokia/ip530/devicetree.cb | 152 ++++++------ src/mainboard/nvidia/l1_2pvv/devicetree.cb | 224 +++++++++--------- src/mainboard/pcengines/alix1c/devicetree.cb | 60 +++--- src/mainboard/pcengines/alix2d/devicetree.cb | 42 ++-- src/mainboard/rca/rm4100/devicetree.cb | 58 +++--- src/mainboard/roda/rk886ex/devicetree.cb | 118 +++++----- src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb | 78 +++--- src/mainboard/sunw/ultra40/devicetree.cb | 168 +++++++------- src/mainboard/supermicro/h8dme/devicetree.cb | 158 ++++++------ src/mainboard/supermicro/h8dmr/devicetree.cb | 174 +++++++------- src/mainboard/supermicro/h8dmr_fam10/devicetree.cb | 174 +++++++------- src/mainboard/supermicro/h8qme_fam10/devicetree.cb | 106 ++++---- src/mainboard/supermicro/x6dai_g/devicetree.cb | 8 +- src/mainboard/supermicro/x6dhe_g/devicetree.cb | 42 ++-- src/mainboard/supermicro/x6dhe_g2/devicetree.cb | 42 ++-- src/mainboard/supermicro/x6dhr_ig/devicetree.cb | 28 +- src/mainboard/supermicro/x6dhr_ig2/devicetree.cb | 24 +- src/mainboard/technexion/tim5690/devicetree.cb | 112 +++++----- src/mainboard/technexion/tim8690/devicetree.cb | 114 +++++----- src/mainboard/technologic/ts5300/devicetree.cb | 4 +- src/mainboard/televideo/tc7020/devicetree.cb | 48 ++-- src/mainboard/thomson/ip1000/devicetree.cb | 58 +++--- src/mainboard/traverse/geos/devicetree.cb | 38 ++-- src/mainboard/tyan/s1846/devicetree.cb | 42 ++-- src/mainboard/tyan/s2735/devicetree.cb | 32 ++-- src/mainboard/tyan/s2850/devicetree.cb | 42 ++-- src/mainboard/tyan/s2875/devicetree.cb | 34 ++-- src/mainboard/tyan/s2880/devicetree.cb | 50 ++-- src/mainboard/tyan/s2881/devicetree.cb | 68 +++--- src/mainboard/tyan/s2882/devicetree.cb | 98 ++++---- src/mainboard/tyan/s2885/devicetree.cb | 80 +++--- src/mainboard/tyan/s2891/devicetree.cb | 184 +++++++------- src/mainboard/tyan/s2892/devicetree.cb | 128 +++++----- src/mainboard/tyan/s2895/devicetree.cb | 158 ++++++------ src/mainboard/tyan/s2912/devicetree.cb | 164 ++++++------ src/mainboard/tyan/s2912_fam10/devicetree.cb | 166 ++++++------ src/mainboard/tyan/s4880/devicetree.cb | 50 ++-- src/mainboard/tyan/s4882/devicetree.cb | 262 ++++++++++---------- src/mainboard/via/epia-cn/devicetree.cb | 64 +++--- src/mainboard/via/epia-m/devicetree.cb | 32 ++-- src/mainboard/via/epia-m700/devicetree.cb | 38 ++-- src/mainboard/via/epia-n/devicetree.cb | 128 +++++----- src/mainboard/via/epia/devicetree.cb | 46 ++-- src/mainboard/via/pc2500e/devicetree.cb | 78 +++--- src/mainboard/via/vt8454c/devicetree.cb | 58 +++--- src/mainboard/winent/pl6064/devicetree.cb | 62 +++--- src/mainboard/wyse/s50/devicetree.cb | 58 +++--- util/sconfig/main.c | 7 +- util/sconfig/sconfig.l | 2 +- 156 files changed, 6204 insertions(+), 6195 deletions(-)
diff --git a/Makefile.inc b/Makefile.inc index 3f553c6..618e2ee 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -167,10 +167,14 @@ $(ROMCC): $(top)/util/romcc/romcc.c ####################################################################### # needed objects that every mainboard uses # Creation of these is architecture and mainboard independent -$(obj)/mainboard/$(MAINBOARDDIR)/static.c: $(src)/mainboard/$(MAINBOARDDIR)/devicetree.cb $(objutil)/sconfig/sconfig + +$(obj)/devicetree.cb.pre: $(src)/mainboard/$(MAINBOARDDIR)/devicetree.cb $(obj)/config.h @printf " SCONFIG $(subst $(src)/,,$(<))\n" + cpp $(CFLAGS) -P -MMD -MT $@ $< -o $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/static.c: $(obj)/devicetree.cb.pre $(objutil)/sconfig/sconfig mkdir -p $(obj)/mainboard/$(MAINBOARDDIR) - $(objutil)/sconfig/sconfig $(MAINBOARDDIR) $(obj)/mainboard/$(MAINBOARDDIR) + $(objutil)/sconfig/sconfig $(MAINBOARDDIR) $(obj)/mainboard/$(MAINBOARDDIR) $(obj)/devicetree.cb.pre
ramstage-y+=$(obj)/mainboard/$(MAINBOARDDIR)/static.c
diff --git a/src/mainboard/a-trend/atc-6220/devicetree.cb b/src/mainboard/a-trend/atc-6220/devicetree.cb index 4ab61c4..0815fc1 100644 --- a/src/mainboard/a-trend/atc-6220/devicetree.cb +++ b/src/mainboard/a-trend/atc-6220/devicetree.cb @@ -1,55 +1,55 @@ -chip northbridge/intel/i440bx # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/slot_1 # CPU - device lapic 0 on end # APIC +chip northbridge/intel/i440bx // Northbridge + device lapic_cluster 0 on // APIC cluster + chip cpu/intel/slot_1 // CPU + device lapic 0 on end // APIC end end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 7.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) - device pnp 3f0.0 on # Floppy + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + device pci 1.0 on end // PCI/AGP bridge + chip southbridge/intel/i82371eb // Southbridge + device pci 7.0 on // ISA bridge + chip superio/winbond/w83977tf // Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 3f0.1 on # Parallel port + device pnp 3f0.1 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 3f0.2 on # COM1 + device pnp 3f0.2 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 3f0.3 on # COM2 / IR + device pnp 3f0.3 on // COM2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 3f0.5 on # PS/2 keyboard + device pnp 3f0.5 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt + irq 0x70 = 1 // PS/2 keyboard interrupt + irq 0x72 = 12 // PS/2 mouse interrupt end - device pnp 3f0.6 on # Consumer IR + device pnp 3f0.6 on // Consumer IR end - device pnp 3f0.7 on # GPIO 1 + device pnp 3f0.7 on // GPIO 1 end - device pnp 3f0.8 on # GPIO 2 + device pnp 3f0.8 on // GPIO 2 end - device pnp 3f0.a on # ACPI + device pnp 3f0.a on // ACPI end end end - device pci 7.1 on end # IDE - device pci 7.2 on end # USB - device pci 7.3 on end # ACPI + device pci 7.1 on end // IDE + device pci 7.2 on end // USB + device pci 7.3 on end // ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. + // Enable UDMA/33 for higher speed if your IDE device(s) support it. register "ide0_drive0_udma33_enable" = "0" register "ide0_drive1_udma33_enable" = "0" register "ide1_drive0_udma33_enable" = "0" diff --git a/src/mainboard/a-trend/atc-6240/devicetree.cb b/src/mainboard/a-trend/atc-6240/devicetree.cb index 7a2b9a9..4853d05 100644 --- a/src/mainboard/a-trend/atc-6240/devicetree.cb +++ b/src/mainboard/a-trend/atc-6240/devicetree.cb @@ -1,65 +1,65 @@ -chip northbridge/intel/i440bx # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/slot_1 # CPU - device lapic 0 on end # APIC +chip northbridge/intel/i440bx // Northbridge + device lapic_cluster 0 on // APIC cluster + chip cpu/intel/slot_1 // CPU + device lapic 0 on end // APIC end end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 7.0 on # ISA bridge - chip superio/winbond/w83627hf # Super I/O - device pnp 3f0.0 on # Floppy + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + device pci 1.0 on end // PCI/AGP bridge + chip southbridge/intel/i82371eb // Southbridge + device pci 7.0 on // ISA bridge + chip superio/winbond/w83627hf // Super I/O + device pnp 3f0.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 3f0.1 on # Parallel port + device pnp 3f0.1 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 end - device pnp 3f0.2 on # COM1 + device pnp 3f0.2 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 3f0.3 on # COM2 / IR + device pnp 3f0.3 on // COM2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 3f0.5 on # PS/2 keyboard + device pnp 3f0.5 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt + irq 0x70 = 1 // PS/2 keyboard interrupt + irq 0x72 = 12 // PS/2 mouse interrupt end - device pnp 3f0.6 on # Consumer IR + device pnp 3f0.6 on // Consumer IR io 0x60 = 0x00 end - device pnp 3f0.7 on # Game port / MIDI / GPIO 1 + device pnp 3f0.7 on // Game port / MIDI / GPIO 1 io 0x60 = 0x201 io 0x62 = 0x330 irq 0x70 = 9 end - device pnp 3f0.8 off # GPIO 2 / WDT + device pnp 3f0.8 off // GPIO 2 / WDT end - device pnp 3f0.9 off # GPIO 3 + device pnp 3f0.9 off // GPIO 3 end - device pnp 3f0.a off # ACPI + device pnp 3f0.a off // ACPI end - device pnp 3f0.b off # HWM (TODO) + device pnp 3f0.b off // HWM (TODO) end end end - device pci 7.1 on end # IDE - device pci 7.2 on end # USB - device pci 7.3 on end # ACPI - device pci c.0 on end # Onboard audio (ES1371) + device pci 7.1 on end // IDE + device pci 7.2 on end // USB + device pci 7.3 on end // ACPI + device pci c.0 on end // Onboard audio (ES1371) register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. + // Enable UDMA/33 for higher speed if your IDE device(s) support it. register "ide0_drive0_udma33_enable" = "0" register "ide0_drive1_udma33_enable" = "0" register "ide1_drive0_udma33_enable" = "0" diff --git a/src/mainboard/abit/be6-ii_v2_0/devicetree.cb b/src/mainboard/abit/be6-ii_v2_0/devicetree.cb index 9c7cf56..6454142 100644 --- a/src/mainboard/abit/be6-ii_v2_0/devicetree.cb +++ b/src/mainboard/abit/be6-ii_v2_0/devicetree.cb @@ -1,52 +1,52 @@ -chip northbridge/intel/i440bx # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/slot_1 # CPU - device lapic 0 on end # APIC +chip northbridge/intel/i440bx // Northbridge + device lapic_cluster 0 on // APIC cluster + chip cpu/intel/slot_1 // CPU + device lapic 0 on end // APIC end end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 7.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) - device pnp 3f0.0 on # Floppy + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + device pci 1.0 on end // PCI/AGP bridge + chip southbridge/intel/i82371eb // Southbridge + device pci 7.0 on // ISA bridge + chip superio/winbond/w83977tf // Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 3f0.1 on # Parallel port + device pnp 3f0.1 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 3f0.2 on # COM1 + device pnp 3f0.2 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 3f0.3 on # COM2 / IR + device pnp 3f0.3 on // COM2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 3f0.5 on # PS/2 keyboard + device pnp 3f0.5 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt + irq 0x70 = 1 // PS/2 keyboard interrupt + irq 0x72 = 12 // PS/2 mouse interrupt end - device pnp 3f0.6 on # Consumer IR + device pnp 3f0.6 on // Consumer IR end - device pnp 3f0.7 on # GPIO 1 + device pnp 3f0.7 on // GPIO 1 end - device pnp 3f0.8 on # GPIO 2 + device pnp 3f0.8 on // GPIO 2 end - device pnp 3f0.a on # ACPI + device pnp 3f0.a on // ACPI end end end - device pci 7.1 on end # IDE, UDMA/33 (part of 82371EB) - device pci 7.2 on end # USB - device pci 7.3 on end # ACPI - device pci 13.0 on end # IDE, UDMA/66 (HPT366 controller) + device pci 7.1 on end // IDE, UDMA/33 (part of 82371EB) + device pci 7.2 on end // USB + device pci 7.3 on end // ACPI + device pci 13.0 on end // IDE, UDMA/66 (HPT366 controller) register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" diff --git a/src/mainboard/advantech/pcm-5820/devicetree.cb b/src/mainboard/advantech/pcm-5820/devicetree.cb index b416e9a..34377c7 100644 --- a/src/mainboard/advantech/pcm-5820/devicetree.cb +++ b/src/mainboard/advantech/pcm-5820/devicetree.cb @@ -1,56 +1,56 @@ -chip northbridge/amd/gx1 # Northbridge - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - chip southbridge/amd/cs5530 # Southbridge - device pci 12.0 on # ISA bridge - chip superio/winbond/w83977f # SUper I/O - device pnp 3f0.0 on # Floppy +chip northbridge/amd/gx1 // Northbridge + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + chip southbridge/amd/cs5530 // Southbridge + device pci 12.0 on // ISA bridge + chip superio/winbond/w83977f // SUper I/O + device pnp 3f0.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 3f0.1 on # Parallel port + device pnp 3f0.1 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 3f0.2 on # COM1 + device pnp 3f0.2 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 3f0.3 on # COM2 + device pnp 3f0.3 on // COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 3f0.4 on # RTC / On-Now control + device pnp 3f0.4 on // RTC / On-Now control io 0x60 = 0x70 irq 0x70 = 8 end - device pnp 3f0.5 on # PS/2 keyboard / mouse + device pnp 3f0.5 on // PS/2 keyboard / mouse io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt + irq 0x70 = 1 // PS/2 keyboard interrupt + irq 0x72 = 12 // PS/2 mouse interrupt end - device pnp 3f0.6 on # IR - # TODO? + device pnp 3f0.6 on // IR + // TODO? end - device pnp 3f0.7 on # GPIO 1 - # TODO? + device pnp 3f0.7 on // GPIO 1 + // TODO? end - device pnp 3f0.8 on # GPIO 2 - # TODO? + device pnp 3f0.8 on // GPIO 2 + // TODO? end end end - device pci 12.1 on end # SMI - device pci 12.2 on end # IDE - device pci 12.3 on end # Audio (onboard) - device pci 12.4 on end # VGA - device pci 13.0 on end # USB + device pci 12.1 on end // SMI + device pci 12.2 on end // IDE + device pci 12.3 on end // Audio (onboard) + device pci 12.4 on end // VGA + device pci 13.0 on end // USB register "ide0_enable" = "1" register "ide1_enable" = "1" end end - chip cpu/amd/model_gx1 # CPU + chip cpu/amd/model_gx1 // CPU end end diff --git a/src/mainboard/amd/bimini_fam10/devicetree.cb b/src/mainboard/amd/bimini_fam10/devicetree.cb index a5bec74..03988f8 100644 --- a/src/mainboard/amd/bimini_fam10/devicetree.cb +++ b/src/mainboard/amd/bimini_fam10/devicetree.cb @@ -1,28 +1,28 @@ - # sample config for amd/bimini_fam10 + // sample config for amd/bimini_fam10 chip northbridge/amd/amdfam10/root_complex device lapic_cluster 0 on - chip cpu/amd/socket_ASB2 #L1 and DDR3 + chip cpu/amd/socket_ASB2 //L1 and DDR3 device lapic 0 on end end end device pci_domain 0 on subsystemid 0x1022 0x3060 inherit chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge + device pci 18.0 on // northbridge chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 off end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 on end # PCIE P2P bridge 0x9605 - device pci 6.0 on end # PCIE P2P bridge 0x9606 - device pci 7.0 on end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 off end # - register "gppsb_configuration" = "4" # Configuration E - register "gpp_configuration" = "2" # Configuration C + device pci 0.0 on end // HT 0x9600 + device pci 1.0 on end // Internal Graphics P2P bridge 0x9602 + device pci 2.0 off end // PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 off end // PCIE P2P bridge 0x960b + device pci 4.0 on end // PCIE P2P bridge 0x9604 + device pci 5.0 on end // PCIE P2P bridge 0x9605 + device pci 6.0 on end // PCIE P2P bridge 0x9606 + device pci 7.0 on end // PCIE P2P bridge 0x9607 + device pci 8.0 off end // NB/SB Link P2P bridge + device pci 9.0 on end // + device pci a.0 off end // + register "gppsb_configuration" = "4" // Configuration E + register "gpp_configuration" = "2" // Configuration C register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "0" @@ -32,42 +32,42 @@ chip northbridge/amd/amdfam10/root_complex register "gfx_reconfiguration" = "1" register "gfx_link_width" = "0" end - chip southbridge/amd/sb800 # it is under NB/SB Link, but on the same pci bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 + chip southbridge/amd/sb800 // it is under NB/SB Link, but on the same pci bus + device pci 11.0 on end // SATA + device pci 12.0 on end // USB + device pci 12.2 on end // USB + device pci 13.0 on end // USB + device pci 13.2 on end // USB + device pci 14.0 on // SM + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 + chip drivers/generic/generic //dimm 0-0-1 device i2c 51 on end end - chip drivers/generic/generic #dimm 0-1-0 + chip drivers/generic/generic //dimm 0-1-0 device i2c 52 on end end - chip drivers/generic/generic #dimm 0-1-1 + chip drivers/generic/generic //dimm 0-1-1 device i2c 53 on end end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.4 off end # PCI 0x4384 # PCI-b conflict with GPIO. - device pci 14.5 on end # USB 2 - device pci 14.6 on end # Gec - device pci 15.0 on end # PCIe 0 - device pci 15.1 on end # PCIe 1 - device pci 15.2 on end # PCIe 2 - device pci 15.3 on end # PCIe 3 - device pci 16.0 on end # USB - device pci 16.2 on end # USB - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end // SM + device pci 14.1 on end // IDE 0x439c + device pci 14.2 on end // HDA 0x4383 + device pci 14.3 on end // LPC 0x439d + device pci 14.4 off end // PCI 0x4384 # PCI-b conflict with GPIO. + device pci 14.5 on end // USB 2 + device pci 14.6 on end // Gec + device pci 15.0 on end // PCIe 0 + device pci 15.1 on end // PCIe 1 + device pci 15.2 on end // PCIe 2 + device pci 15.3 on end // PCIe 3 + device pci 16.0 on end // USB + device pci 16.2 on end // USB + register "boot_switch_sata_ide" = "0" // 0: boot from SATA. 1: IDE register "gpp_configuration" = "4" - end #southbridge/amd/sb800 - end # device pci 18.0 + end //southbridge/amd/sb800 + end // device pci 18.0
device pci 18.0 on end device pci 18.0 on end @@ -76,34 +76,34 @@ chip northbridge/amd/amdfam10/root_complex device pci 18.3 on end device pci 18.4 on end end - end #pci_domain - #for node 32 to node 63 -# device pci_domain 0 on -# chip northbridge/amd/amdfam10 -# device pci 00.0 on end# northbridge -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.1 on end -# device pci 00.2 on end -# device pci 00.3 on end -# device pci 00.4 on end -# device pci 00.5 on end -# end -# end #pci_domain + end //pci_domain + //for node 32 to node 63 +// device pci_domain 0 on +// chip northbridge/amd/amdfam10 +// device pci 00.0 on end# northbridge +// device pci 00.0 on end +// device pci 00.0 on end +// device pci 00.0 on end +// device pci 00.1 on end +// device pci 00.2 on end +// device pci 00.3 on end +// device pci 00.4 on end +// device pci 00.5 on end +// end +// end #pci_domain
-# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # hard reset -# device pnp 0.9 off end # mcp55 -# device pnp 0.a on end # GH ext table -# end +// chip drivers/generic/debug +// device pnp 0.0 off end # chip name +// device pnp 0.1 on end # pci_regs_all +// device pnp 0.2 off end # mem +// device pnp 0.3 off end # cpuid +// device pnp 0.4 off end # smbus_regs_all +// device pnp 0.5 off end # dual core msr +// device pnp 0.6 off end # cache size +// device pnp 0.7 off end # tsc +// device pnp 0.8 off end # hard reset +// device pnp 0.9 off end # mcp55 +// device pnp 0.a on end # GH ext table +// end
end diff --git a/src/mainboard/amd/db800/devicetree.cb b/src/mainboard/amd/db800/devicetree.cb index e872571..85727f6 100644 --- a/src/mainboard/amd/db800/devicetree.cb +++ b/src/mainboard/amd/db800/devicetree.cb @@ -1,64 +1,64 @@ chip northbridge/amd/lx device pci_domain 0 on - device pci 1.0 on end # Northbridge - device pci 1.1 on end # Graphics + device pci 1.0 on end // Northbridge + device pci 1.1 on end // Graphics chip southbridge/amd/cs5536 - # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK - # SIRQ Mode = Active(Quiet) mode. Save power.... - # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK + // IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + // SIRQ Mode = Active(Quiet) mode. Save power.... + // Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK register "lpc_serirq_enable" = "0x0000105a" register "lpc_serirq_polarity" = "0x0000EFA5" register "lpc_serirq_mode" = "1" register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "1" # 0: host, 1:device - register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "enable_ide_nand_flash" = "0" // 0:ide mode, 1:flash + register "enable_USBP4_device" = "1" // 0: host, 1:device + register "enable_USBP4_overcurrent" = "0" //0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) register "com1_enable" = "0" register "com1_address" = "0x3F8" register "com1_irq" = "4" register "com2_enable" = "0" register "com2_address" = "0x2F8" register "com2_irq" = "3" - register "unwanted_vpci[0]" = "0" # End of list has a zero - device pci d.0 on end # Ethernet - device pci e.0 on end # Slot1 - device pci f.0 on # ISA Bridge + register "unwanted_vpci[0]" = "0" // End of list has a zero + device pci d.0 on end // Ethernet + device pci e.0 on end // Slot1 + device pci f.0 on // ISA Bridge chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel port + device pnp 2e.1 off // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off end # Com2 - device pnp 2e.5 on # Keyboard + device pnp 2e.3 off end // Com2 + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GAME_MIDI_GIPO1 - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b off end # HW Monitor + device pnp 2e.6 off end // CIR + device pnp 2e.7 off end // GAME_MIDI_GIPO1 + device pnp 2e.8 off end // GPIO2 + device pnp 2e.9 off end // GPIO3 + device pnp 2e.a off end // ACPI + device pnp 2e.b off end // HW Monitor end end - device pci f.2 on end # IDE Controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI + device pci f.2 on end // IDE Controller + device pci f.3 on end // Audio + device pci f.4 on end // OHCI + device pci f.5 on end // EHCI end end - # APIC cluster is late CPU init. + // APIC cluster is late CPU init. device lapic_cluster 0 on chip cpu/amd/model_lx device lapic 0 on end diff --git a/src/mainboard/amd/dbm690t/devicetree.cb b/src/mainboard/amd/dbm690t/devicetree.cb index e1b01b2..4328287 100644 --- a/src/mainboard/amd/dbm690t/devicetree.cb +++ b/src/mainboard/amd/dbm690t/devicetree.cb @@ -1,13 +1,13 @@ -#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) -#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, -# 1: the system allows a PCIE link to be established on Dev2 or Dev3. -#Define gfx_dual_slot, 0: single slot, 1: dual slot -#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable -#Define gfx_tmds, 0: didn't support TMDS, 1: support -#Define gfx_compliance, 0: didn't support compliance, 1: support -#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration -#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 +//Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +//Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) +//Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, +// 1: the system allows a PCIE link to be established on Dev2 or Dev3. +//Define gfx_dual_slot, 0: single slot, 1: dual slot +//Define gfx_lane_reversal, 0: disable lane reversal, 1: enable +//Define gfx_tmds, 0: didn't support TMDS, 1: support +//Define gfx_compliance, 0: didn't support compliance, 1: support +//Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration +//Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex device lapic_cluster 0 on chip cpu/amd/socket_S1G1 @@ -17,19 +17,19 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on subsystemid 0x1022 0x3050 inherit chip northbridge/amd/amdk8 - device pci 18.0 on # southbridge + device pci 18.0 on // southbridge chip southbridge/amd/rs690 - device pci 0.0 on end # HT 0x7910 - device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - device pci 5.0 on end # Internal Graphics 0x791F + device pci 0.0 on end // HT 0x7910 + device pci 1.0 on // Internal Graphics P2P bridge 0x7912 + device pci 5.0 on end // Internal Graphics 0x791F end - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 - device pci 3.0 off end # PCIE P2P bridge 0x791b - device pci 4.0 on end # PCIE P2P bridge 0x7914 - device pci 5.0 on end # PCIE P2P bridge 0x7915 - device pci 6.0 on end # PCIE P2P bridge 0x7916 - device pci 7.0 on end # PCIE P2P bridge 0x7917 - device pci 8.0 off end # NB/SB Link P2P bridge + device pci 2.0 on end // PCIE P2P bridge (external graphics) 0x7913 + device pci 3.0 off end // PCIE P2P bridge 0x791b + device pci 4.0 on end // PCIE P2P bridge 0x7914 + device pci 5.0 on end // PCIE P2P bridge 0x7915 + device pci 6.0 on end // PCIE P2P bridge 0x7916 + device pci 7.0 on end // PCIE P2P bridge 0x7917 + device pci 8.0 off end // NB/SB Link P2P bridge register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" @@ -40,83 +40,83 @@ chip northbridge/amd/amdk8/root_complex register "gfx_reconfiguration" = "1" register "gfx_link_width" = "0" end - chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus - device pci 12.0 on end # SATA 0x4380 - device pci 13.0 on end # USB 0x4387 - device pci 13.1 on end # USB 0x4388 - device pci 13.2 on end # USB 0x4389 - device pci 13.3 on end # USB 0x438a - device pci 13.4 on end # USB 0x438b - device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 - chip drivers/generic/generic #dimm 0-0-0 + chip southbridge/amd/sb600 // it is under NB/SB Link, but on the same pri bus + device pci 12.0 on end // SATA 0x4380 + device pci 13.0 on end // USB 0x4387 + device pci 13.1 on end // USB 0x4388 + device pci 13.2 on end // USB 0x4389 + device pci 13.3 on end // USB 0x438a + device pci 13.4 on end // USB 0x438b + device pci 13.5 on end // USB 2 0x4386 + device pci 14.0 on // SM 0x4385 + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 + chip drivers/generic/generic //dimm 0-0-1 device i2c 51 on end end - chip drivers/generic/generic #dimm 0-1-0 + chip drivers/generic/generic //dimm 0-1-0 device i2c 52 on end end - chip drivers/generic/generic #dimm 0-1-1 + chip drivers/generic/generic //dimm 0-1-1 device i2c 53 on end end - end # SM - device pci 14.1 on end # IDE 0x438c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x438d + end // SM + device pci 14.1 on end // IDE 0x438c + device pci 14.2 on end // HDA 0x4383 + device pci 14.3 on // LPC 0x438d chip superio/ite/it8712f - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Com1 + device pnp 2e.1 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 off # Com2 + device pnp 2e.2 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 off # Parallel Port + device pnp 2e.3 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard + device pnp 2e.4 off end // EC + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.6 on # Mouse + device pnp 2e.6 on // Mouse irq 0x70 = 12 end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + device pnp 2e.7 off // GPIO, must be closed for unresolved reason. end - device pnp 2e.8 off # MIDI + device pnp 2e.8 off // MIDI io 0x60 = 0x300 irq 0x70 = 9 end - device pnp 2e.9 off # GAME + device pnp 2e.9 off // GAME io 0x60 = 0x220 end - device pnp 2e.a off end # CIR - end #superio/ite/it8712f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # ACI 0x4382 - device pci 14.6 on end # MCI 0x438e + device pnp 2e.a off end // CIR + end //superio/ite/it8712f + end //LPC + device pci 14.4 on end // PCI 0x4384 + device pci 14.5 on end // ACI 0x4382 + device pci 14.6 on end // MCI 0x438e register "hda_viddid" = "0x10ec0882" - end #southbridge/amd/sb600 - end # device pci 18.0 + end //southbridge/amd/sb600 + end // device pci 18.0
device pci 18.0 on end device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end - end #northbridge/amd/amdk8 - end #pci_domain -end #northbridge/amd/amdk8/root_complex + end //northbridge/amd/amdk8 + end //pci_domain +end //northbridge/amd/amdk8/root_complex
diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb index acae2ca..16395ed 100644 --- a/src/mainboard/amd/inagua/devicetree.cb +++ b/src/mainboard/amd/inagua/devicetree.cb @@ -1,21 +1,21 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -# +// +// This file is part of the coreboot project. +// +// Copyright (C) 2011 Advanced Micro Devices, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +// chip northbridge/amd/agesa_wrapper/family14/root_complex device lapic_cluster 0 on chip cpu/amd/agesa_wrapper/family14 @@ -24,60 +24,60 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex end device pci_domain 0 on subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa_wrapper/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge - device pci 1.1 on end # Internal Multimedia - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 on end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - end # agesa_wrapper northbridge + chip northbridge/amd/agesa_wrapper/family14 // CPU side of HT root complex +// device pci 18.0 on # northbridge + chip northbridge/amd/agesa_wrapper/family14 // PCI side of HT root complex + device pci 0.0 on end // Root Complex + device pci 1.0 on end // Internal Graphics P2P bridge + device pci 1.1 on end // Internal Multimedia + device pci 4.0 on end // PCIE P2P bridge 0x9604 + device pci 5.0 off end // PCIE P2P bridge 0x9605 + device pci 6.0 on end // PCIE P2P bridge 0x9606 + device pci 7.0 off end // PCIE P2P bridge 0x9607 + device pci 8.0 off end // NB/SB Link P2P bridge + end // agesa_wrapper northbridge
- chip southbridge/amd/cimx_wrapper/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 + chip southbridge/amd/cimx_wrapper/sb800 // it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end // SATA + device pci 12.0 on end // USB + device pci 12.1 on end // USB + device pci 12.2 on end // USB + device pci 13.0 on end // USB + device pci 13.1 on end // USB + device pci 13.2 on end // USB + device pci 14.0 on // SM + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 + chip drivers/generic/generic //dimm 0-0-1 device i2c 51 on end end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d + end // SM + device pci 14.1 on end // IDE 0x439c + device pci 14.2 on end // HDA 0x4383 + device pci 14.3 on // LPC 0x439d chip superio/smsc/kbc1100 - device pnp 2e.7 on # Keyboard + device pnp 2e.7 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - end # kbc1100 - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - device pci 15.0 on end # PCIe PortA - device pci 15.1 on end # PCIe PortB - device pci 15.2 on end # PCIe PortC - device pci 15.3 on end # PCIe PortD - register "gpp_configuration" = "4" #1:1:1:1 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx_wrapper/sb800 -# end # device pci 18.0 -# These seem unnecessary + end // kbc1100 + end //LPC + device pci 14.4 on end // PCI 0x4384 + device pci 14.5 on end // USB 2 + device pci 15.0 on end // PCIe PortA + device pci 15.1 on end // PCIe PortB + device pci 15.2 on end // PCIe PortC + device pci 15.3 on end // PCIe PortD + register "gpp_configuration" = "4" //1:1:1:1 + register "boot_switch_sata_ide" = "0" // 0: boot from SATA. 1: IDE + end //southbridge/amd/cimx_wrapper/sb800 +// end # device pci 18.0 +// These seem unnecessary device pci 18.0 on end - #device pci 18.0 on end + //device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end @@ -85,7 +85,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex device pci 18.5 on end device pci 18.6 on end device pci 18.7 on end - end #chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex - end #pci_domain -end #northbridge/amd/agesa_wrapper/family14/root_complex + end //chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex + end //pci_domain +end //northbridge/amd/agesa_wrapper/family14/root_complex
diff --git a/src/mainboard/amd/mahogany/devicetree.cb b/src/mainboard/amd/mahogany/devicetree.cb index d60d5a1..f164dd1 100644 --- a/src/mainboard/amd/mahogany/devicetree.cb +++ b/src/mainboard/amd/mahogany/devicetree.cb @@ -1,13 +1,13 @@ -#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) -#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, -# 1: the system allows a PCIE link to be established on Dev2 or Dev3. -#Define gfx_dual_slot, 0: single slot, 1: dual slot -#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable -#Define gfx_tmds, 0: didn't support TMDS, 1: support -#Define gfx_compliance, 0: didn't support compliance, 1: support -#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration -#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 +//Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +//Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) +//Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, +// 1: the system allows a PCIE link to be established on Dev2 or Dev3. +//Define gfx_dual_slot, 0: single slot, 1: dual slot +//Define gfx_lane_reversal, 0: disable lane reversal, 1: enable +//Define gfx_tmds, 0: didn't support TMDS, 1: support +//Define gfx_compliance, 0: didn't support compliance, 1: support +//Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration +//Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex device lapic_cluster 0 on chip cpu/amd/socket_AM2 @@ -17,21 +17,21 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on subsystemid 0x1022 0x3060 inherit chip northbridge/amd/amdk8 - device pci 18.0 on # southbridge + device pci 18.0 on // southbridge chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default + device pci 0.0 on end // HT 0x9600 + device pci 1.0 on end // Internal Graphics P2P bridge 0x9602 + device pci 2.0 on end // PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 on end // PCIE P2P bridge 0x960b + device pci 4.0 on end // PCIE P2P bridge 0x9604 + device pci 5.0 off end // PCIE P2P bridge 0x9605 + device pci 6.0 off end // PCIE P2P bridge 0x9606 + device pci 7.0 off end // PCIE P2P bridge 0x9607 + device pci 8.0 off end // NB/SB Link P2P bridge + device pci 9.0 on end // + device pci a.0 on end // + register "gppsb_configuration" = "1" // Configuration B + register "gpp_configuration" = "3" // Configuration D default register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "1" @@ -41,81 +41,81 @@ chip northbridge/amd/amdk8/root_complex register "gfx_reconfiguration" = "1" register "gfx_link_width" = "0" end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 + chip southbridge/amd/sb700 // it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end // SATA + device pci 12.0 on end // USB + device pci 12.1 on end // USB + device pci 12.2 on end // USB + device pci 13.0 on end // USB + device pci 13.1 on end // USB + device pci 13.2 on end // USB + device pci 14.0 on // SM + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 + chip drivers/generic/generic //dimm 0-0-1 device i2c 51 on end end - chip drivers/generic/generic #dimm 0-1-0 + chip drivers/generic/generic //dimm 0-1-0 device i2c 52 on end end - chip drivers/generic/generic #dimm 0-1-1 + chip drivers/generic/generic //dimm 0-1-1 device i2c 53 on end end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d + end // SM + device pci 14.1 on end // IDE 0x439c + device pci 14.2 on end // HDA 0x4383 + device pci 14.3 on // LPC 0x439d chip superio/ite/it8718f - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Com1 + device pnp 2e.1 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 off # Com2 + device pnp 2e.2 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 off # Parallel Port + device pnp 2e.3 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard + device pnp 2e.4 off end // EC + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.6 on # Mouse + device pnp 2e.6 on // Mouse irq 0x70 = 12 end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + device pnp 2e.7 off // GPIO, must be closed for unresolved reason. end - device pnp 2e.8 off # MIDI + device pnp 2e.8 off // MIDI io 0x60 = 0x300 irq 0x70 = 9 end - device pnp 2e.9 off # GAME + device pnp 2e.9 off // GAME io 0x60 = 0x220 end - device pnp 2e.a off end # CIR - end #superio/ite/it8718f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 + device pnp 2e.a off end // CIR + end //superio/ite/it8718f + end //LPC + device pci 14.4 on end // PCI 0x4384 + device pci 14.5 on end // USB 2 + register "boot_switch_sata_ide" = "0" // 0: boot from SATA. 1: IDE + end //southbridge/amd/sb700 + end // device pci 18.0
device pci 18.0 on end device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end - end #northbridge/amd/amdk8 - end #pci_domain -end #northbridge/amd/amdk8/root_complex + end //northbridge/amd/amdk8 + end //pci_domain +end //northbridge/amd/amdk8/root_complex diff --git a/src/mainboard/amd/mahogany_fam10/devicetree.cb b/src/mainboard/amd/mahogany_fam10/devicetree.cb index c51e53e..6c0e2c0 100644 --- a/src/mainboard/amd/mahogany_fam10/devicetree.cb +++ b/src/mainboard/amd/mahogany_fam10/devicetree.cb @@ -1,28 +1,28 @@ -# sample config for amd/mahogany_fam10 +// sample config for amd/mahogany_fam10 chip northbridge/amd/amdfam10/root_complex device lapic_cluster 0 on - chip cpu/amd/socket_AM2r2 #L1 and DDR2 + chip cpu/amd/socket_AM2r2 //L1 and DDR2 device lapic 0 on end end end device pci_domain 0 on subsystemid 0x1022 0x3060 inherit chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge + device pci 18.0 on // northbridge chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default + device pci 0.0 on end // HT 0x9600 + device pci 1.0 on end // Internal Graphics P2P bridge 0x9602 + device pci 2.0 on end // PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 on end // PCIE P2P bridge 0x960b + device pci 4.0 on end // PCIE P2P bridge 0x9604 + device pci 5.0 off end // PCIE P2P bridge 0x9605 + device pci 6.0 off end // PCIE P2P bridge 0x9606 + device pci 7.0 off end // PCIE P2P bridge 0x9607 + device pci 8.0 off end // NB/SB Link P2P bridge + device pci 9.0 on end // + device pci a.0 on end // + register "gppsb_configuration" = "1" // Configuration B + register "gpp_configuration" = "3" // Configuration D default register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "1" @@ -32,75 +32,75 @@ chip northbridge/amd/amdfam10/root_complex register "gfx_reconfiguration" = "1" register "gfx_link_width" = "0" end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 + chip southbridge/amd/sb700 // it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end // SATA + device pci 12.0 on end // USB + device pci 12.1 on end // USB + device pci 12.2 on end // USB + device pci 13.0 on end // USB + device pci 13.1 on end // USB + device pci 13.2 on end // USB + device pci 14.0 on // SM + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 + chip drivers/generic/generic //dimm 0-0-1 device i2c 51 on end end - chip drivers/generic/generic #dimm 0-1-0 + chip drivers/generic/generic //dimm 0-1-0 device i2c 52 on end end - chip drivers/generic/generic #dimm 0-1-1 + chip drivers/generic/generic //dimm 0-1-1 device i2c 53 on end end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d + end // SM + device pci 14.1 on end // IDE 0x439c + device pci 14.2 on end // HDA 0x4383 + device pci 14.3 on // LPC 0x439d chip superio/ite/it8718f - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Com1 + device pnp 2e.1 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 off # Com2 + device pnp 2e.2 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 off # Parallel Port + device pnp 2e.3 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard + device pnp 2e.4 off end // EC + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.6 on # Mouse + device pnp 2e.6 on // Mouse irq 0x70 = 12 end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + device pnp 2e.7 off // GPIO, must be closed for unresolved reason. end - device pnp 2e.8 off # MIDI + device pnp 2e.8 off // MIDI io 0x60 = 0x300 irq 0x70 = 9 end - device pnp 2e.9 off # GAME + device pnp 2e.9 off // GAME io 0x60 = 0x220 end - device pnp 2e.a off end # CIR - end #superio/ite/it8718f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 + device pnp 2e.a off end // CIR + end //superio/ite/it8718f + end //LPC + device pci 14.4 on end // PCI 0x4384 + device pci 14.5 on end // USB 2 + register "boot_switch_sata_ide" = "0" // 0: boot from SATA. 1: IDE + end //southbridge/amd/sb700 + end // device pci 18.0
device pci 18.0 on end device pci 18.0 on end @@ -108,36 +108,36 @@ chip northbridge/amd/amdfam10/root_complex device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end -# device pci 00.5 on end +// device pci 00.5 on end end - end #pci_domain - #for node 32 to node 63 -# device pci_domain 0 on -# chip northbridge/amd/amdfam10 -# device pci 00.0 on end# northbridge -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.1 on end -# device pci 00.2 on end -# device pci 00.3 on end -# device pci 00.4 on end -# device pci 00.5 on end -# end -# end #pci_domain + end //pci_domain + //for node 32 to node 63 +// device pci_domain 0 on +// chip northbridge/amd/amdfam10 +// device pci 00.0 on end# northbridge +// device pci 00.0 on end +// device pci 00.0 on end +// device pci 00.0 on end +// device pci 00.1 on end +// device pci 00.2 on end +// device pci 00.3 on end +// device pci 00.4 on end +// device pci 00.5 on end +// end +// end #pci_domain
-# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # hard reset -# device pnp 0.9 off end # mcp55 -# device pnp 0.a on end # GH ext table -# end +// chip drivers/generic/debug +// device pnp 0.0 off end # chip name +// device pnp 0.1 on end # pci_regs_all +// device pnp 0.2 off end # mem +// device pnp 0.3 off end # cpuid +// device pnp 0.4 off end # smbus_regs_all +// device pnp 0.5 off end # dual core msr +// device pnp 0.6 off end # cache size +// device pnp 0.7 off end # tsc +// device pnp 0.8 off end # hard reset +// device pnp 0.9 off end # mcp55 +// device pnp 0.a on end # GH ext table +// end
end diff --git a/src/mainboard/amd/norwich/devicetree.cb b/src/mainboard/amd/norwich/devicetree.cb index 533ea92..edb5183 100644 --- a/src/mainboard/amd/norwich/devicetree.cb +++ b/src/mainboard/amd/norwich/devicetree.cb @@ -1,37 +1,37 @@ chip northbridge/amd/lx device pci_domain 0 on - device pci 1.0 on end # Northbridge - device pci 1.1 on end # Graphics + device pci 1.0 on end // Northbridge + device pci 1.1 on end // Graphics chip southbridge/amd/cs5536 - # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK - # SIRQ Mode = Active(Quiet) mode. Save power.... - # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK + // IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + // SIRQ Mode = Active(Quiet) mode. Save power.... + // Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK register "lpc_serirq_enable" = "0x00001002" register "lpc_serirq_polarity" = "0x0000EFFD" register "lpc_serirq_mode" = "1" register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "0" #0: host, 1:device - register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "enable_ide_nand_flash" = "0" // 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" //0: host, 1:device + register "enable_USBP4_overcurrent" = "0" //0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) register "com1_enable" = "1" register "com1_address" = "0x3F8" register "com1_irq" = "4" register "com2_enable" = "0" register "com2_address" = "0x2F8" register "com2_irq" = "3" - register "unwanted_vpci[0]" = "0" # End of list has a zero - device pci b.0 on end # Slot 3 - device pci c.0 on end # Slot 4 - device pci d.0 on end # Slot 1 - device pci e.0 on end # Slot 2 - device pci f.0 on end # ISA Bridge - device pci f.2 on end # IDE Controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI + register "unwanted_vpci[0]" = "0" // End of list has a zero + device pci b.0 on end // Slot 3 + device pci c.0 on end // Slot 4 + device pci d.0 on end // Slot 1 + device pci e.0 on end // Slot 2 + device pci f.0 on end // ISA Bridge + device pci f.2 on end // IDE Controller + device pci f.3 on end // Audio + device pci f.4 on end // OHCI + device pci f.5 on end // EHCI end end - # APIC cluster is late CPU init. + // APIC cluster is late CPU init. device lapic_cluster 0 on chip cpu/amd/model_lx device lapic 0 on end diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb index 8ca165b..a2d9b3b 100644 --- a/src/mainboard/amd/persimmon/devicetree.cb +++ b/src/mainboard/amd/persimmon/devicetree.cb @@ -1,21 +1,21 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -# +// +// This file is part of the coreboot project. +// +// Copyright (C) 2011 Advanced Micro Devices, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +// chip northbridge/amd/agesa_wrapper/family14/root_complex device lapic_cluster 0 on chip cpu/amd/agesa_wrapper/family14 @@ -24,76 +24,76 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex end device pci_domain 0 on subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa_wrapper/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - end # agesa_wrapper northbridge + chip northbridge/amd/agesa_wrapper/family14 // CPU side of HT root complex +// device pci 18.0 on # northbridge + chip northbridge/amd/agesa_wrapper/family14 // PCI side of HT root complex + device pci 0.0 on end // Root Complex + device pci 1.0 on end // Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end // Internal Multimedia + device pci 4.0 on end // PCIE P2P bridge 0x9604 + device pci 5.0 off end // PCIE P2P bridge 0x9605 + device pci 6.0 off end // PCIE P2P bridge 0x9606 + device pci 7.0 off end // PCIE P2P bridge 0x9607 + device pci 8.0 off end // NB/SB Link P2P bridge + end // agesa_wrapper northbridge
- chip southbridge/amd/cimx_wrapper/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 + chip southbridge/amd/cimx_wrapper/sb800 // it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end // SATA + device pci 12.0 on end // USB + device pci 12.1 on end // USB + device pci 12.2 on end // USB + device pci 13.0 on end // USB + device pci 13.1 on end // USB + device pci 13.2 on end // USB + device pci 14.0 on // SM + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 + chip drivers/generic/generic //dimm 0-0-1 device i2c 51 on end end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d + end // SM + device pci 14.1 on end // IDE 0x439c + device pci 14.2 on end // HDA 0x4383 + device pci 14.3 on // LPC 0x439d chip superio/fintek/f81865f - device pnp 4e.0 off # Floppy + device pnp 4e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 4e.3 off end # Parallel Port - device pnp 4e.4 off end # Hardware Monitor - device pnp 4e.5 on # Keyboard + device pnp 4e.3 off end // Parallel Port + device pnp 4e.4 off end // Hardware Monitor + device pnp 4e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 4e.6 off end # GPIO - device pnp 4e.a off end # PME - device pnp 4e.10 on # COM1 + device pnp 4e.6 off end // GPIO + device pnp 4e.a off end // PME + device pnp 4e.10 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 4e.11 off # COM2 + device pnp 4e.11 off // COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end - end # f81865f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - device pci 15.0 on end # PCIe PortA - device pci 15.1 on end # PCIe PortB - device pci 15.2 on end # PCIe PortC - device pci 15.3 on end # PCIe PortD - register "gpp_configuration" = "4" #1:1:1:1 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx_wrapper/sb800 -# end # device pci 18.0 -# These seem unnecessary + end // f81865f + end //LPC + device pci 14.4 on end // PCI 0x4384 + device pci 14.5 on end // USB 2 + device pci 15.0 on end // PCIe PortA + device pci 15.1 on end // PCIe PortB + device pci 15.2 on end // PCIe PortC + device pci 15.3 on end // PCIe PortD + register "gpp_configuration" = "4" //1:1:1:1 + register "boot_switch_sata_ide" = "0" // 0: boot from SATA. 1: IDE + end //southbridge/amd/cimx_wrapper/sb800 +// end # device pci 18.0 +// These seem unnecessary device pci 18.0 on end - #device pci 18.0 on end + //device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end @@ -101,7 +101,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex device pci 18.5 on end device pci 18.6 on end device pci 18.7 on end - end #chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex - end #pci_domain -end #northbridge/amd/agesa_wrapper/family14/root_complex + end //chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex + end //pci_domain +end //northbridge/amd/agesa_wrapper/family14/root_complex
diff --git a/src/mainboard/amd/pistachio/devicetree.cb b/src/mainboard/amd/pistachio/devicetree.cb index 6608fdd..6bc3235 100644 --- a/src/mainboard/amd/pistachio/devicetree.cb +++ b/src/mainboard/amd/pistachio/devicetree.cb @@ -1,13 +1,13 @@ -#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) -#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, -# 1: the system allows a PCIE link to be established on Dev2 or Dev3. -#Define gfx_dual_slot, 0: single slot, 1: dual slot -#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable -#Define gfx_tmds, 0: didn't support TMDS, 1: support -#Define gfx_compliance, 0: didn't support compliance, 1: support -#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration -#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 +//Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +//Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) +//Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, +// 1: the system allows a PCIE link to be established on Dev2 or Dev3. +//Define gfx_dual_slot, 0: single slot, 1: dual slot +//Define gfx_lane_reversal, 0: disable lane reversal, 1: enable +//Define gfx_tmds, 0: didn't support TMDS, 1: support +//Define gfx_compliance, 0: didn't support compliance, 1: support +//Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration +//Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex device lapic_cluster 0 on chip cpu/amd/socket_AM2 @@ -17,20 +17,20 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on subsystemid 0x1022 0x3050 inherit chip northbridge/amd/amdk8 - device pci 18.0 on # southbridge, K8 HT Configuration + device pci 18.0 on // southbridge, K8 HT Configuration chip southbridge/amd/rs690 - device pci 0.0 on end # HT 0x7910 - # device pci 0.1 off end # CLK - device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - device pci 5.0 on end # Internal Graphics 0x791F + device pci 0.0 on end // HT 0x7910 + // device pci 0.1 off end # CLK + device pci 1.0 on // Internal Graphics P2P bridge 0x7912 + device pci 5.0 on end // Internal Graphics 0x791F end - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 - device pci 3.0 off end # PCIE P2P bridge 0x791b - device pci 4.0 on end # PCIE P2P bridge 0x7914 - device pci 5.0 on end # PCIE P2P bridge 0x7915 - device pci 6.0 on end # PCIE P2P bridge 0x7916 - device pci 7.0 on end # PCIE P2P bridge 0x7917 - device pci 8.0 off end # NB/SB Link P2P bridge + device pci 2.0 on end // PCIE P2P bridge (external graphics) 0x7913 + device pci 3.0 off end // PCIE P2P bridge 0x791b + device pci 4.0 on end // PCIE P2P bridge 0x7914 + device pci 5.0 on end // PCIE P2P bridge 0x7915 + device pci 6.0 on end // PCIE P2P bridge 0x7916 + device pci 7.0 on end // PCIE P2P bridge 0x7917 + device pci 8.0 off end // NB/SB Link P2P bridge register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" @@ -41,41 +41,41 @@ chip northbridge/amd/amdk8/root_complex register "gfx_reconfiguration" = "1" register "gfx_link_width" = "0" end - chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus - device pci 12.0 on end # SATA 0x4380 - device pci 13.0 on end # USB 0x4387 - device pci 13.1 on end # USB 0x4388 - device pci 13.2 on end # USB 0x4389 - device pci 13.3 on end # USB 0x438a - device pci 13.4 on end # USB 0x438b - device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 - chip drivers/generic/generic #dimm 0-0-0 + chip southbridge/amd/sb600 // it is under NB/SB Link, but on the same pri bus + device pci 12.0 on end // SATA 0x4380 + device pci 13.0 on end // USB 0x4387 + device pci 13.1 on end // USB 0x4388 + device pci 13.2 on end // USB 0x4389 + device pci 13.3 on end // USB 0x438a + device pci 13.4 on end // USB 0x438b + device pci 13.5 on end // USB 2 0x4386 + device pci 14.0 on // SM 0x4385 + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 + chip drivers/generic/generic //dimm 0-0-1 device i2c 51 off end end - chip drivers/generic/generic #dimm 0-1-0 + chip drivers/generic/generic //dimm 0-1-0 device i2c 52 off end end - chip drivers/generic/generic #dimm 0-1-1 + chip drivers/generic/generic //dimm 0-1-1 device i2c 53 off end end - end # SM - device pci 14.1 on end # IDE 0x438c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x438d - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # ACI 0x4382 - device pci 14.6 on end # MCI 0x438e - end #southbridge/amd/sb600 - end # device pci 18.0 + end // SM + device pci 14.1 on end // IDE 0x438c + device pci 14.2 on end // HDA 0x4383 + device pci 14.3 on end // LPC 0x438d + device pci 14.4 on end // PCI 0x4384 + device pci 14.5 on end // ACI 0x4382 + device pci 14.6 on end // MCI 0x438e + end //southbridge/amd/sb600 + end // device pci 18.0
- device pci 18.1 on end # K8 Address Map - device pci 18.2 on end # K8 DRAM Controller and HT Trace Mode - device pci 18.3 on end # K8 Miscellaneous Control - end #northbridge/amd/amdk8 - end #pci_domain -end #northbridge/amd/amdk8/root_complex + device pci 18.1 on end // K8 Address Map + device pci 18.2 on end // K8 DRAM Controller and HT Trace Mode + device pci 18.3 on end // K8 Miscellaneous Control + end //northbridge/amd/amdk8 + end //pci_domain +end //northbridge/amd/amdk8/root_complex
diff --git a/src/mainboard/amd/rumba/devicetree.cb b/src/mainboard/amd/rumba/devicetree.cb index fc49cbe..19fd978 100644 --- a/src/mainboard/amd/rumba/devicetree.cb +++ b/src/mainboard/amd/rumba/devicetree.cb @@ -1,5 +1,5 @@ chip northbridge/amd/gx2 - #register "irqmap" = "0xaa5b" + //register "irqmap" = "0xaa5b" device lapic_cluster 0 on chip cpu/amd/model_gx2 device lapic 0 on end @@ -9,13 +9,13 @@ chip northbridge/amd/gx2 device pci 1.0 on end device pci 1.1 on end chip southbridge/amd/cs5536 - register "lpc_serirq_enable" = "0x80" # enabled with default timing - device pci d.0 on end # Realtek 8139 LAN - device pci f.0 on end # ISA Bridge - device pci f.2 on end # IDE Controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI + register "lpc_serirq_enable" = "0x80" // enabled with default timing + device pci d.0 on end // Realtek 8139 LAN + device pci f.0 on end // ISA Bridge + device pci f.2 on end // IDE Controller + device pci f.3 on end // Audio + device pci f.4 on end // OHCI + device pci f.5 on end // EHCI end end end diff --git a/src/mainboard/amd/serengeti_cheetah/devicetree.cb b/src/mainboard/amd/serengeti_cheetah/devicetree.cb index b819292..fcde9a7 100644 --- a/src/mainboard/amd/serengeti_cheetah/devicetree.cb +++ b/src/mainboard/amd/serengeti_cheetah/devicetree.cb @@ -7,18 +7,18 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on subsystemid 0x1022 0x2b80 inherit chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 + device pci 18.0 on // northbridge + // devices on link 0, link 0 == LDT 0 chip southbridge/amd/amd8132 - # the on/off keyword is mandatory + // the on/off keyword is mandatory device pci 0.0 on end device pci 0.1 on end device pci 1.0 on end device pci 1.1 on end end chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge + // this "device pci 0.0" is the parent the next one + // PCI bridge device pci 0.0 on device pci 0.0 on end device pci 0.1 on end @@ -27,41 +27,41 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.0 on chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.3 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # CIR + device pnp 2e.6 off // CIR io 0x60 = 0x100 end - device pnp 2e.7 off # GAME_MIDI_GIPO1 + device pnp 2e.7 off // GAME_MIDI_GIPO1 io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.8 off end // GPIO2 + device pnp 2e.9 off end // GPIO3 + device pnp 2e.a off end // ACPI + device pnp 2e.b on // HW Monitor io 0x60 = 0x290 irq 0x70 = 5 end @@ -70,55 +70,55 @@ chip northbridge/amd/amdk8/root_complex device pci 1.1 on end device pci 1.2 on end device pci 1.3 on - chip drivers/i2c/i2cmux # pca9556 smbus mux - device i2c 18 on #0 pca9516 1 - chip drivers/generic/generic #dimm 0-0-0 + chip drivers/i2c/i2cmux // pca9556 smbus mux + device i2c 18 on //0 pca9516 1 + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 + chip drivers/generic/generic //dimm 0-0-1 device i2c 51 on end end - chip drivers/generic/generic #dimm 0-1-0 + chip drivers/generic/generic //dimm 0-1-0 device i2c 52 on end end - chip drivers/generic/generic #dimm 0-1-1 + chip drivers/generic/generic //dimm 0-1-1 device i2c 53 on end end end - device i2c 18 on #1 pca9516 2 - chip drivers/generic/generic #dimm 1-0-0 + device i2c 18 on //1 pca9516 2 + chip drivers/generic/generic //dimm 1-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 1-0-1 + chip drivers/generic/generic //dimm 1-0-1 device i2c 51 on end end - chip drivers/generic/generic #dimm 1-1-0 + chip drivers/generic/generic //dimm 1-1-0 device i2c 52 on end end - chip drivers/generic/generic #dimm 1-1-1 + chip drivers/generic/generic //dimm 1-1-1 device i2c 53 on end end - chip drivers/generic/generic #dimm 1-2-0 + chip drivers/generic/generic //dimm 1-2-0 device i2c 54 on end end - chip drivers/generic/generic #dimm 1-2-1 + chip drivers/generic/generic //dimm 1-2-1 device i2c 55 on end end - chip drivers/generic/generic #dimm 1-3-0 + chip drivers/generic/generic //dimm 1-3-0 device i2c 56 on end end - chip drivers/generic/generic #dimm 1-3-1 + chip drivers/generic/generic //dimm 1-3-1 device i2c 57 on end end end end - end # acpi + end // acpi device pci 1.5 off end device pci 1.6 off end register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 + end // device pci 18.0
device pci 18.0 on end device pci 18.0 on end @@ -127,13 +127,13 @@ chip northbridge/amd/amdk8/root_complex device pci 18.3 on end end chip northbridge/amd/amdk8 - device pci 19.0 on # northbridge + device pci 19.0 on // northbridge chip southbridge/amd/amd8151 - # the on/off keyword is mandatory + // the on/off keyword is mandatory device pci 0.0 on end device pci 1.0 on end end - end # device pci 19.0 + end // device pci 19.0
device pci 19.0 on end device pci 19.0 on end @@ -143,17 +143,17 @@ chip northbridge/amd/amdk8/root_complex end
- end #pci_domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# end + end //pci_domain +// chip drivers/generic/debug +// device pnp 0.0 off end # chip name +// device pnp 0.1 on end # pci_regs_all +// device pnp 0.2 off end # mem +// device pnp 0.3 off end # cpuid +// device pnp 0.4 off end # smbus_regs_all +// device pnp 0.5 off end # dual core msr +// device pnp 0.6 off end # cache size +// device pnp 0.7 off end # tsc +// end
end
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb b/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb index bfbb2b3..80fba8e 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb +++ b/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb @@ -1,24 +1,24 @@ chip northbridge/amd/amdfam10/root_complex device lapic_cluster 0 on - chip cpu/amd/socket_F_1207 #L1 and DDR2 + chip cpu/amd/socket_F_1207 //L1 and DDR2 device lapic 0 on end end end device pci_domain 0 on subsystemid 0x1022 0x2b80 inherit chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 + device pci 18.0 on // northbridge + // devices on link 0, link 0 == LDT 0 chip southbridge/amd/amd8132 - # the on/off keyword is mandatory + // the on/off keyword is mandatory device pci 0.0 on end device pci 0.1 on end device pci 1.0 on end device pci 1.1 on end end chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge + // this "device pci 0.0" is the parent the next one + // PCI bridge device pci 0.0 on device pci 0.0 on end device pci 0.1 on end @@ -27,41 +27,41 @@ chip northbridge/amd/amdfam10/root_complex end device pci 1.0 on chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.3 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # CIR + device pnp 2e.6 off // CIR io 0x60 = 0x100 end - device pnp 2e.7 off # GAME_MIDI_GIPO1 + device pnp 2e.7 off // GAME_MIDI_GIPO1 io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.8 off end // GPIO2 + device pnp 2e.9 off end // GPIO3 + device pnp 2e.a off end // ACPI + device pnp 2e.b on // HW Monitor io 0x60 = 0x290 irq 0x70 = 5 end @@ -70,45 +70,45 @@ chip northbridge/amd/amdfam10/root_complex device pci 1.1 on end device pci 1.2 on end device pci 1.3 on - chip drivers/i2c/i2cmux2 # pca9556 smbus mux - chip drivers/i2c/i2cmux2 # pca9556 smbus mux - device i2c 18 on #0 pca9516 1 - chip drivers/generic/generic #dimm 0-0-0 + chip drivers/i2c/i2cmux2 // pca9556 smbus mux + chip drivers/i2c/i2cmux2 // pca9556 smbus mux + device i2c 18 on //0 pca9516 1 + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 + chip drivers/generic/generic //dimm 0-0-1 device i2c 51 on end end - chip drivers/generic/generic #dimm 0-1-0 + chip drivers/generic/generic //dimm 0-1-0 device i2c 52 on end end - chip drivers/generic/generic #dimm 0-1-1 + chip drivers/generic/generic //dimm 0-1-1 device i2c 53 on end end end - device i2c 18 on #1 pca9516 2 - chip drivers/generic/generic #dimm 1-0-0 + device i2c 18 on //1 pca9516 2 + chip drivers/generic/generic //dimm 1-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 1-0-1 + chip drivers/generic/generic //dimm 1-0-1 device i2c 51 on end end - chip drivers/generic/generic #dimm 1-1-0 + chip drivers/generic/generic //dimm 1-1-0 device i2c 52 on end end - chip drivers/generic/generic #dimm 1-1-1 + chip drivers/generic/generic //dimm 1-1-1 device i2c 53 on end end end end end - end # acpi + end // acpi device pci 1.5 off end device pci 1.6 off end register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 + end // device pci 18.0
device pci 18.0 on end device pci 18.0 on end @@ -116,37 +116,37 @@ chip northbridge/amd/amdfam10/root_complex device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end -# device pci 00.5 on end +// device pci 00.5 on end end - end #pci_domain - #for node 32 to node 63 -# device pci_domain 0 on -# chip northbridge/amd/amdfam10 -# device pci 00.0 on end# northbridge -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.1 on end -# device pci 00.2 on end -# device pci 00.3 on end -# device pci 00.4 on end -# device pci 00.5 on end -# end -# end #pci_domain + end //pci_domain + //for node 32 to node 63 +// device pci_domain 0 on +// chip northbridge/amd/amdfam10 +// device pci 00.0 on end# northbridge +// device pci 00.0 on end +// device pci 00.0 on end +// device pci 00.0 on end +// device pci 00.1 on end +// device pci 00.2 on end +// device pci 00.3 on end +// device pci 00.4 on end +// device pci 00.5 on end +// end +// end #pci_domain
-# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # hard reset -# device pnp 0.9 off end # mcp55 -# device pnp 0.a on end # GH ext table -# end +// chip drivers/generic/debug +// device pnp 0.0 off end # chip name +// device pnp 0.1 on end # pci_regs_all +// device pnp 0.2 off end # mem +// device pnp 0.3 off end # cpuid +// device pnp 0.4 off end # smbus_regs_all +// device pnp 0.5 off end # dual core msr +// device pnp 0.6 off end # cache size +// device pnp 0.7 off end # tsc +// device pnp 0.8 off end # hard reset +// device pnp 0.9 off end # mcp55 +// device pnp 0.a on end # GH ext table +// end
end
diff --git a/src/mainboard/amd/tilapia_fam10/devicetree.cb b/src/mainboard/amd/tilapia_fam10/devicetree.cb index aeb582a..9f9ee53 100644 --- a/src/mainboard/amd/tilapia_fam10/devicetree.cb +++ b/src/mainboard/amd/tilapia_fam10/devicetree.cb @@ -1,28 +1,28 @@ -# sample config for amd/tilapia_fam10 +// sample config for amd/tilapia_fam10 chip northbridge/amd/amdfam10/root_complex device lapic_cluster 0 on - chip cpu/amd/socket_AM3 #L1 and DDR3 + chip cpu/amd/socket_AM3 //L1 and DDR3 device lapic 0 on end end end device pci_domain 0 on subsystemid 0x1022 0x3060 inherit chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge + device pci 18.0 on // northbridge chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default + device pci 0.0 on end // HT 0x9600 + device pci 1.0 on end // Internal Graphics P2P bridge 0x9602 + device pci 2.0 on end // PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 on end // PCIE P2P bridge 0x960b + device pci 4.0 on end // PCIE P2P bridge 0x9604 + device pci 5.0 off end // PCIE P2P bridge 0x9605 + device pci 6.0 off end // PCIE P2P bridge 0x9606 + device pci 7.0 off end // PCIE P2P bridge 0x9607 + device pci 8.0 off end // NB/SB Link P2P bridge + device pci 9.0 on end // + device pci a.0 on end // + register "gppsb_configuration" = "1" // Configuration B + register "gpp_configuration" = "3" // Configuration D default register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "2" @@ -33,75 +33,75 @@ chip northbridge/amd/amdfam10/root_complex register "gfx_reconfiguration" = "1" register "gfx_link_width" = "0" end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 + chip southbridge/amd/sb700 // it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end // SATA + device pci 12.0 on end // USB + device pci 12.1 on end // USB + device pci 12.2 on end // USB + device pci 13.0 on end // USB + device pci 13.1 on end // USB + device pci 13.2 on end // USB + device pci 14.0 on // SM + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 + chip drivers/generic/generic //dimm 0-0-1 device i2c 51 on end end - chip drivers/generic/generic #dimm 0-1-0 + chip drivers/generic/generic //dimm 0-1-0 device i2c 52 on end end - chip drivers/generic/generic #dimm 0-1-1 + chip drivers/generic/generic //dimm 0-1-1 device i2c 53 on end end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d + end // SM + device pci 14.1 on end // IDE 0x439c + device pci 14.2 on end // HDA 0x4383 + device pci 14.3 on // LPC 0x439d chip superio/ite/it8718f - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Com1 + device pnp 2e.1 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 off # Com2 + device pnp 2e.2 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 off # Parallel Port + device pnp 2e.3 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard + device pnp 2e.4 off end // EC + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.6 on # Mouse + device pnp 2e.6 on // Mouse irq 0x70 = 12 end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + device pnp 2e.7 off // GPIO, must be closed for unresolved reason. end - device pnp 2e.8 off # MIDI + device pnp 2e.8 off // MIDI io 0x60 = 0x300 irq 0x70 = 9 end - device pnp 2e.9 off # GAME + device pnp 2e.9 off // GAME io 0x60 = 0x220 end - device pnp 2e.a off end # CIR - end #superio/ite/it8718f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 + device pnp 2e.a off end // CIR + end //superio/ite/it8718f + end //LPC + device pci 14.4 on end // PCI 0x4384 + device pci 14.5 on end // USB 2 + register "boot_switch_sata_ide" = "0" // 0: boot from SATA. 1: IDE + end //southbridge/amd/sb700 + end // device pci 18.0
device pci 18.0 on end device pci 18.0 on end @@ -109,35 +109,35 @@ chip northbridge/amd/amdfam10/root_complex device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end -# device pci 00.5 on end +// device pci 00.5 on end end - end #pci_domain - #for node 32 to node 63 -# device pci_domain 0 on -# chip northbridge/amd/amdfam10 -# device pci 00.0 on end# northbridge -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.1 on end -# device pci 00.2 on end -# device pci 00.3 on end -# device pci 00.4 on end -# device pci 00.5 on end -# end -# end #pci_domain + end //pci_domain + //for node 32 to node 63 +// device pci_domain 0 on +// chip northbridge/amd/amdfam10 +// device pci 00.0 on end# northbridge +// device pci 00.0 on end +// device pci 00.0 on end +// device pci 00.0 on end +// device pci 00.1 on end +// device pci 00.2 on end +// device pci 00.3 on end +// device pci 00.4 on end +// device pci 00.5 on end +// end +// end #pci_domain
-# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # hard reset -# device pnp 0.9 off end # mcp55 -# device pnp 0.a on end # GH ext table -# end +// chip drivers/generic/debug +// device pnp 0.0 off end # chip name +// device pnp 0.1 on end # pci_regs_all +// device pnp 0.2 off end # mem +// device pnp 0.3 off end # cpuid +// device pnp 0.4 off end # smbus_regs_all +// device pnp 0.5 off end # dual core msr +// device pnp 0.6 off end # cache size +// device pnp 0.7 off end # tsc +// device pnp 0.8 off end # hard reset +// device pnp 0.9 off end # mcp55 +// device pnp 0.a on end # GH ext table +// end end diff --git a/src/mainboard/arima/hdama/devicetree.cb b/src/mainboard/arima/hdama/devicetree.cb index d7252e2..b071193 100644 --- a/src/mainboard/arima/hdama/devicetree.cb +++ b/src/mainboard/arima/hdama/devicetree.cb @@ -7,134 +7,134 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on subsystemid 0x161f 0x3016 inherit chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 + device pci 18.0 on // northbridge + // devices on link 0, link 0 == LDT 0 chip southbridge/amd/amd8131 - # the on/off keyword is mandatory - device pci 0.0 on # PCIX bridge - ## On board NIC A - #chip drivers/generic/generic - # device pci 3.0 on - # irq 0 = 0x13 - # end - #end - ## On board NIC B - #chip drivers/generic/generic - # device pci 4.0 on - # irq 0 = 0x13 - # end - #end - ## PCI Slot 3 - #chip drivers/generic/generic - # device pci 1.0 on - # irq 0 = 0x11 - # irq 1 = 0x12 - # irq 2 = 0x13 - # irq 3 = 0x10 - # end - #end - ## PCI Slot 4 - #chip drivers/generic/generic - # device pci 2.0 on - # irq 0 = 0x12 - # irq 1 = 0x13 - # irq 2 = 0x10 - # irq 3 = 0x11 - # end - #end + // the on/off keyword is mandatory + device pci 0.0 on // PCIX bridge + // On board NIC A + //chip drivers/generic/generic + // device pci 3.0 on + // irq 0 = 0x13 + // end + //end + // On board NIC B + //chip drivers/generic/generic + // device pci 4.0 on + // irq 0 = 0x13 + // end + //end + // PCI Slot 3 + //chip drivers/generic/generic + // device pci 1.0 on + // irq 0 = 0x11 + // irq 1 = 0x12 + // irq 2 = 0x13 + // irq 3 = 0x10 + // end + //end + // PCI Slot 4 + //chip drivers/generic/generic + // device pci 2.0 on + // irq 0 = 0x12 + // irq 1 = 0x13 + // irq 2 = 0x10 + // irq 3 = 0x11 + // end + //end end - device pci 0.1 on end # IOAPIC - device pci 1.0 on # PCIX bridge - ## PCI Slot 1 - #chip drivers/generic/generic - # device pci 1.0 on - # irq 0 = 0x11 - # irq 1 = 0x12 - # irq 2 = 0x13 - # irq 3 = 0x10 - # end - #end - ## PCI Slot 2 - #chip drivers/generic/generic - # device pci 2.0 on - # irq 0 = 0x12 - # irq 1 = 0x13 - # irq 2 = 0x10 - # irq 3 = 0x11 - # end - #end + device pci 0.1 on end // IOAPIC + device pci 1.0 on // PCIX bridge + // PCI Slot 1 + //chip drivers/generic/generic + // device pci 1.0 on + // irq 0 = 0x11 + // irq 1 = 0x12 + // irq 2 = 0x13 + // irq 3 = 0x10 + // end + //end + // PCI Slot 2 + //chip drivers/generic/generic + // device pci 2.0 on + // irq 0 = 0x12 + // irq 1 = 0x13 + // irq 2 = 0x10 + // irq 3 = 0x11 + // end + //end end - device pci 1.1 on end # IOAPIC + device pci 1.1 on end // IOAPIC end chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent of the next one - # PCI bridge + // this "device pci 0.0" is the parent of the next one + // PCI bridge device pci 0.0 on - device pci 0.0 on end # USB0 - device pci 0.1 on end # USB1 - device pci 0.2 off end # USB 2.0 - device pci 1.0 off end # LAN - device pci 6.0 on end # ATI Rage XL - ## PCI Slot 5 (correct?) - #chip drivers/generic/generic - # device pci 5.0 on - # irq 0 = 0x11 - # irq 1 = 0x12 - # irq 2 = 0x13 - # irq 3 = 0x10 - # end - #end - ## PCI Slot 6 (correct?) - #chip drivers/generic/generic - # device pci 4.0 on - # irq 0 = 0x10 - # irq 1 = 0x11 - # irq 2 = 0x12 - # irq 3 = 0x13 - # end - #end + device pci 0.0 on end // USB0 + device pci 0.1 on end // USB1 + device pci 0.2 off end // USB 2.0 + device pci 1.0 off end // LAN + device pci 6.0 on end // ATI Rage XL + // PCI Slot 5 (correct?) + //chip drivers/generic/generic + // device pci 5.0 on + // irq 0 = 0x11 + // irq 1 = 0x12 + // irq 2 = 0x13 + // irq 3 = 0x10 + // end + //end + // PCI Slot 6 (correct?) + //chip drivers/generic/generic + // device pci 4.0 on + // irq 0 = 0x10 + // irq 1 = 0x11 + // irq 2 = 0x12 + // irq 3 = 0x13 + // end + //end
end - # LPC bridge + // LPC bridge device pci 1.0 on chip superio/nsc/pc87360 - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 off # Com 2 + device pnp 2e.2 off // Com 2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 on # Com 1 + device pnp 2e.3 on // Com 1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.4 off end # SWC - device pnp 2e.5 off end # Mouse - device pnp 2e.6 on # Keyboard + device pnp 2e.4 off end // SWC + device pnp 2e.5 off end // Mouse + device pnp 2e.6 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end # ACB - device pnp 2e.9 off end # FSCM - device pnp 2e.a off end # WDT + device pnp 2e.7 off end // GPIO + device pnp 2e.8 off end // ACB + device pnp 2e.9 off end // FSCM + device pnp 2e.a off end // WDT end end - device pci 1.1 on end # IDE - device pci 1.2 on end # SMBus 2.0 - device pci 1.3 on # System Management + device pci 1.1 on end // IDE + device pci 1.2 on end // SMBus 2.0 + device pci 1.3 on // System Management chip drivers/generic/generic - #phillips pca9545 smbus mux + //phillips pca9545 smbus mux device i2c 70 on - # analog_devices adm1026 + // analog_devices adm1026 chip drivers/generic/generic device i2c 2c on end end @@ -143,44 +143,44 @@ chip northbridge/amd/amdk8/root_complex device i2c 70 on end device i2c 70 on end end - chip drivers/generic/generic #dimm 0-0-0 + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 + chip drivers/generic/generic //dimm 0-0-1 device i2c 51 on end end - chip drivers/generic/generic #dimm 0-1-0 + chip drivers/generic/generic //dimm 0-1-0 device i2c 52 on end end - chip drivers/generic/generic #dimm 0-1-1 + chip drivers/generic/generic //dimm 0-1-1 device i2c 53 on end end - chip drivers/generic/generic #dimm 1-0-0 + chip drivers/generic/generic //dimm 1-0-0 device i2c 54 on end end - chip drivers/generic/generic #dimm 1-0-1 + chip drivers/generic/generic //dimm 1-0-1 device i2c 55 on end end - chip drivers/generic/generic #dimm 1-1-0 + chip drivers/generic/generic //dimm 1-1-0 device i2c 56 on end end - chip drivers/generic/generic #dimm 1-1-1 + chip drivers/generic/generic //dimm 1-1-1 device i2c 57 on end end end - device pci 1.5 off end # AC97 Audio - device pci 1.6 on end # AC97 Modem + device pci 1.5 off end // AC97 Audio + device pci 1.6 on end // AC97 Modem register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 + end // device pci 18.0
- device pci 18.0 on end # LDT1 - device pci 18.0 on end # LDT2 + device pci 18.0 on end // LDT1 + device pci 18.0 on end // LDT2 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end - end # chip northbridge/amd/amdk8 + end // chip northbridge/amd/amdk8 end end
diff --git a/src/mainboard/artecgroup/dbe61/devicetree.cb b/src/mainboard/artecgroup/dbe61/devicetree.cb index 4c2aab4..7b6449f 100644 --- a/src/mainboard/artecgroup/dbe61/devicetree.cb +++ b/src/mainboard/artecgroup/dbe61/devicetree.cb @@ -1,37 +1,37 @@ chip northbridge/amd/lx device pci_domain 0 on - device pci 1.0 on end # Northbridge - device pci 1.1 on end # Graphics + device pci 1.0 on end // Northbridge + device pci 1.1 on end // Graphics chip southbridge/amd/cs5536 - # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK - # SIRQ Mode = Active(Quiet) mode. Save power.... - # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK + // IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + // SIRQ Mode = Active(Quiet) mode. Save power.... + // Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK register "lpc_serirq_enable" = "0x00001002" register "lpc_serirq_polarity" = "0x0000EFFD" register "lpc_serirq_mode" = "1" register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "0" #0: host, 1:device - register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "enable_ide_nand_flash" = "0" // 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" //0: host, 1:device + register "enable_USBP4_overcurrent" = "0" //0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) register "com1_enable" = "0" register "com1_address" = "0x2F8" register "com1_irq" = "3" register "com2_enable" = "1" register "com2_address" = "0x3F8" register "com2_irq" = "4" - register "unwanted_vpci[0]" = "0" # End of list has a zero - device pci b.0 on end # Slot 3 - device pci c.0 on end # Slot 4 - device pci d.0 on end # Slot 1 - device pci e.0 on end # Slot 2 - device pci f.0 on end # ISA Bridge - device pci f.2 on end # IDE Controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI + register "unwanted_vpci[0]" = "0" // End of list has a zero + device pci b.0 on end // Slot 3 + device pci c.0 on end // Slot 4 + device pci d.0 on end // Slot 1 + device pci e.0 on end // Slot 2 + device pci f.0 on end // ISA Bridge + device pci f.2 on end // IDE Controller + device pci f.3 on end // Audio + device pci f.4 on end // OHCI + device pci f.5 on end // EHCI end end - # APIC cluster is late CPU init. + // APIC cluster is late CPU init. device lapic_cluster 0 on chip cpu/amd/model_lx device lapic 0 on end diff --git a/src/mainboard/asi/mb_5blgp/devicetree.cb b/src/mainboard/asi/mb_5blgp/devicetree.cb index f50be6e..20d9386 100644 --- a/src/mainboard/asi/mb_5blgp/devicetree.cb +++ b/src/mainboard/asi/mb_5blgp/devicetree.cb @@ -1,55 +1,55 @@ -chip northbridge/amd/gx1 # Northbridge - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - chip southbridge/amd/cs5530 # Southbridge - device pci 0f.0 on end # Ethernet - device pci 12.0 on # ISA bridge - chip superio/nsc/pc87351 # Super I/O - device pnp 2e.0 off # Floppy +chip northbridge/amd/gx1 // Northbridge + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + chip southbridge/amd/cs5530 // Southbridge + device pci 0f.0 on end // Ethernet + device pci 12.0 on // ISA bridge + chip superio/nsc/pc87351 // Super I/O + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Parallel port + device pnp 2e.1 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # COM2 + device pnp 2e.2 on // COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.e on # COM1 + device pnp 2e.e on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.4 on # System wake-up control (SWC) + device pnp 2e.4 on // System wake-up control (SWC) irq 0x60 = 0x500 end - device pnp 2e.5 on # PS/2 mouse + device pnp 2e.5 on // PS/2 mouse irq 0x70 = 12 end - device pnp 2e.6 on # PS/2 keyboard + device pnp 2e.6 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.7 on # GPIO + device pnp 2e.7 on // GPIO irq 0x60 = 0x800 end - device pnp 2e.8 on # Fan speed control + device pnp 2e.8 on // Fan speed control irq 0x60 = 0x900 end end end - device pci 12.1 off end # SMI - device pci 12.2 on end # IDE - device pci 12.3 on end # Audio - device pci 12.4 on end # VGA - device pci 13.0 on end # USB + device pci 12.1 off end // SMI + device pci 12.2 on end // IDE + device pci 12.3 on end // Audio + device pci 12.4 on end // VGA + device pci 13.0 on end // USB register "ide0_enable" = "1" - register "ide1_enable" = "0" # No connector on this board + register "ide1_enable" = "0" // No connector on this board end end - chip cpu/amd/model_gx1 # CPU + chip cpu/amd/model_gx1 // CPU end end diff --git a/src/mainboard/asi/mb_5blmp/devicetree.cb b/src/mainboard/asi/mb_5blmp/devicetree.cb index ded603a..fa4513b 100644 --- a/src/mainboard/asi/mb_5blmp/devicetree.cb +++ b/src/mainboard/asi/mb_5blmp/devicetree.cb @@ -1,48 +1,48 @@ -chip northbridge/amd/gx1 # Northbridge +chip northbridge/amd/gx1 // Northbridge device pci_domain 0 on - device pci 0.0 on end # Host bridge - chip southbridge/amd/cs5530 # Southbridge - device pci 0f.0 off end # Ethernet (Realtek RTL8139B) - device pci 12.0 on # ISA bridge - chip superio/nsc/pc87351 # Super I/O - device pnp 2e.4 on # PS/2 keyboard (+ mouse?) + device pci 0.0 on end // Host bridge + chip southbridge/amd/cs5530 // Southbridge + device pci 0f.0 off end // Ethernet (Realtek RTL8139B) + device pci 12.0 on // ISA bridge + chip superio/nsc/pc87351 // Super I/O + device pnp 2e.4 on // PS/2 keyboard (+ mouse?) io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 - # irq 0x72 = 12 + // irq 0x72 = 12 end - device pnp 2e.a on # PS/2 mouse + device pnp 2e.a on // PS/2 mouse irq 0x70 = 12 end - device pnp 2e.e on # COM1 + device pnp 2e.e on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.f off # Floppy + device pnp 2e.f off // Floppy io 0x60 = 0x3f2 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.10 on # Parallel port + device pnp 2e.10 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.12 on # COM2 + device pnp 2e.12 on // COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end end end - device pci 12.1 off end # SMI - device pci 12.2 on end # IDE - device pci 12.3 on end # Audio - device pci 12.4 on end # VGA (onboard) - device pci 13.0 on end # USB + device pci 12.1 off end // SMI + device pci 12.2 on end // IDE + device pci 12.3 on end // Audio + device pci 12.4 on end // VGA (onboard) + device pci 13.0 on end // USB register "ide0_enable" = "1" register "ide1_enable" = "1" end end - chip cpu/amd/model_gx1 # CPU + chip cpu/amd/model_gx1 // CPU end end
diff --git a/src/mainboard/asrock/939a785gmh/devicetree.cb b/src/mainboard/asrock/939a785gmh/devicetree.cb index 1dc92a3..3a6d116 100644 --- a/src/mainboard/asrock/939a785gmh/devicetree.cb +++ b/src/mainboard/asrock/939a785gmh/devicetree.cb @@ -1,14 +1,14 @@ -#Define gppsb_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define gpp_configuration -> device 9 1x and device a 1x is 3 and device 9 2x is 2 -#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) -#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, -# 1: the system allows a PCIE link to be established on Dev2 or Dev3. -#Define gfx_dual_slot, 0: single slot, 1: dual slot (means if GFX slot are two 2 8x slots) -#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable -#Define gfx_tmds, 0: didn't support TMDS, 1: support -#Define gfx_compliance, 0: didn't support compliance, 1: support -#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration -#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 +//Define gppsb_configuration, A=0, B=1, C=2, D=3, E=4(default) +//Define gpp_configuration -> device 9 1x and device a 1x is 3 and device 9 2x is 2 +//Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) +//Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, +// 1: the system allows a PCIE link to be established on Dev2 or Dev3. +//Define gfx_dual_slot, 0: single slot, 1: dual slot (means if GFX slot are two 2 8x slots) +//Define gfx_lane_reversal, 0: disable lane reversal, 1: enable +//Define gfx_tmds, 0: didn't support TMDS, 1: support +//Define gfx_compliance, 0: didn't support compliance, 1: support +//Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration +//Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex device lapic_cluster 0 on chip cpu/amd/socket_939 @@ -18,21 +18,21 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on subsystemid 0x1022 0x3060 inherit chip northbridge/amd/amdk8 - device pci 18.0 on # southbridge + device pci 18.0 on // southbridge chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge 16x slot - device pci 3.0 off end # used in dual slot config - device pci 4.0 off end # GPPSB - device pci 5.0 off end # GPPSB - device pci 6.0 off end # GPPSB - device pci 7.0 off end # GPPSB - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # GPP for x1 slot - device pci a.0 on end # GPP for internal network adapter - register "gppsb_configuration" = "4" # Configuration ? - register "gpp_configuration" = "3" # Configuration D default + device pci 0.0 on end // HT 0x9600 + device pci 1.0 on end // Internal Graphics P2P bridge 0x9602 + device pci 2.0 on end // PCIE P2P bridge 16x slot + device pci 3.0 off end // used in dual slot config + device pci 4.0 off end // GPPSB + device pci 5.0 off end // GPPSB + device pci 6.0 off end // GPPSB + device pci 7.0 off end // GPPSB + device pci 8.0 off end // NB/SB Link P2P bridge + device pci 9.0 on end // GPP for x1 slot + device pci a.0 on end // GPP for internal network adapter + register "gppsb_configuration" = "4" // Configuration ? + register "gpp_configuration" = "3" // Configuration D default register "port_enable" = "0x60c" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "0" @@ -42,91 +42,91 @@ chip northbridge/amd/amdk8/root_complex register "gfx_reconfiguration" = "1" register "gfx_link_width" = "0" end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 + chip southbridge/amd/sb700 // it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end // SATA + device pci 12.0 on end // USB + device pci 12.1 on end // USB + device pci 12.2 on end // USB + device pci 13.0 on end // USB + device pci 13.1 on end // USB + device pci 13.2 on end // USB + device pci 14.0 on // SM + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 + chip drivers/generic/generic //dimm 0-0-1 device i2c 51 on end end - chip drivers/generic/generic #dimm 0-1-0 + chip drivers/generic/generic //dimm 0-1-0 device i2c 52 on end end - chip drivers/generic/generic #dimm 0-1-1 + chip drivers/generic/generic //dimm 0-1-1 device i2c 53 on end end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d + end // SM + device pci 14.1 on end // IDE 0x439c + device pci 14.2 on end // HDA 0x4383 + device pci 14.3 on // LPC 0x439d
chip superio/winbond/w83627dhg - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # Com2 + device pnp 2e.3 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # PS/2 keyboard & mouse + device pnp 2e.5 on // PS/2 keyboard & mouse io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - #device pnp 2e.6 off # SPI - #end - device pnp 2e.307 off # GPIO6 + //device pnp 2e.6 off # SPI + //end + device pnp 2e.307 off // GPIO6 end - device pnp 2e.8 on # WDTO#, PLED + device pnp 2e.8 on // WDTO#, PLED end - device pnp 2e.009 on # GPIO2 + device pnp 2e.009 on // GPIO2 end - device pnp 2e.109 on # GPIO3 + device pnp 2e.109 on // GPIO3 end - device pnp 2e.209 on # GPIO4 + device pnp 2e.209 on // GPIO4 end - device pnp 2e.309 off # GPIO5 + device pnp 2e.309 off // GPIO5 end - device pnp 2e.a off # ACPI + device pnp 2e.a off // ACPI end - device pnp 2e.b on # HWM + device pnp 2e.b on // HWM io 0x60 = 0x290 end - device pnp 2e.c off # PECI, SST + device pnp 2e.c off // PECI, SST end - end #superio/winbond/w8362 + end //superio/winbond/w8362
- end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 + end //LPC + device pci 14.4 on end // PCI 0x4384 + device pci 14.5 on end // USB 2 + register "boot_switch_sata_ide" = "0" // 0: boot from SATA. 1: IDE + end //southbridge/amd/sb700 + end // device pci 18.0
device pci 18.0 on end device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end - end #northbridge/amd/amdk8 - end #pci_domain -end #northbridge/amd/amdk8/root_complex + end //northbridge/amd/amdk8 + end //pci_domain +end //northbridge/amd/amdk8/root_complex
diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb index 9dceae6..fe40e2b 100644 --- a/src/mainboard/asrock/e350m1/devicetree.cb +++ b/src/mainboard/asrock/e350m1/devicetree.cb @@ -1,21 +1,21 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -# +// +// This file is part of the coreboot project. +// +// Copyright (C) 2011 Advanced Micro Devices, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +// chip northbridge/amd/agesa_wrapper/family14/root_complex device lapic_cluster 0 on chip cpu/amd/agesa_wrapper/family14 @@ -24,92 +24,92 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex end device pci_domain 0 on subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa_wrapper/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - end # agesa_wrapper northbridge + chip northbridge/amd/agesa_wrapper/family14 // CPU side of HT root complex +// device pci 18.0 on # northbridge + chip northbridge/amd/agesa_wrapper/family14 // PCI side of HT root complex + device pci 0.0 on end // Root Complex + device pci 1.0 on end // Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end // Internal Multimedia + device pci 4.0 on end // PCIE P2P bridge 0x9604 + device pci 5.0 off end // PCIE P2P bridge 0x9605 + device pci 6.0 off end // PCIE P2P bridge 0x9606 + device pci 7.0 off end // PCIE P2P bridge 0x9607 + device pci 8.0 off end // NB/SB Link P2P bridge + end // agesa_wrapper northbridge
- chip southbridge/amd/cimx_wrapper/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 + chip southbridge/amd/cimx_wrapper/sb800 // it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end // SATA + device pci 12.0 on end // USB + device pci 12.1 on end // USB + device pci 12.2 on end // USB + device pci 13.0 on end // USB + device pci 13.1 on end // USB + device pci 13.2 on end // USB + device pci 14.0 on // SM + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 + chip drivers/generic/generic //dimm 0-0-1 device i2c 51 on end end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d + end // SM + device pci 14.1 on end // IDE 0x439c + device pci 14.2 on end // HDA 0x4383 + device pci 14.3 on // LPC 0x439d chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.3 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # CIR + device pnp 2e.6 off // CIR io 0x60 = 0x100 end - device pnp 2e.7 off # GAME_MIDI_GIPO1 + device pnp 2e.7 off // GAME_MIDI_GIPO1 io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.8 off end // GPIO2 + device pnp 2e.9 off end // GPIO3 + device pnp 2e.a off end // ACPI + device pnp 2e.b on // HW Monitor io 0x60 = 0x290 irq 0x70 = 5 end end - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - device pci 15.0 on end # PCIe PortA - device pci 15.1 on end # PCIe PortB - device pci 15.2 on end # PCIe PortC - device pci 15.3 on end # PCIe PortD - register "gpp_configuration" = "4" #1:1:1:1 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx_wrapper/sb800 -# end # device pci 18.0 -# These seem unnecessary + end //LPC + device pci 14.4 on end // PCI 0x4384 + device pci 14.5 on end // USB 2 + device pci 15.0 on end // PCIe PortA + device pci 15.1 on end // PCIe PortB + device pci 15.2 on end // PCIe PortC + device pci 15.3 on end // PCIe PortD + register "gpp_configuration" = "4" //1:1:1:1 + register "boot_switch_sata_ide" = "0" // 0: boot from SATA. 1: IDE + end //southbridge/amd/cimx_wrapper/sb800 +// end # device pci 18.0 +// These seem unnecessary device pci 18.0 on end - #device pci 18.0 on end + //device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end @@ -117,7 +117,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex device pci 18.5 on end device pci 18.6 on end device pci 18.7 on end - end #chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex - end #pci_domain -end #northbridge/amd/agesa_wrapper/family14/root_complex + end //chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex + end //pci_domain +end //northbridge/amd/agesa_wrapper/family14/root_complex
diff --git a/src/mainboard/asus/a8n_e/devicetree.cb b/src/mainboard/asus/a8n_e/devicetree.cb index 86bf3aa..e341d23 100644 --- a/src/mainboard/asus/a8n_e/devicetree.cb +++ b/src/mainboard/asus/a8n_e/devicetree.cb @@ -1,114 +1,114 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device lapic_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_939 # CPU socket - device lapic 0 on end # Local APIC of the CPU +chip northbridge/amd/amdk8/root_complex // Root complex + device lapic_cluster 0 on // (L)APIC cluster + chip cpu/amd/socket_939 // CPU socket + device lapic 0 on end // Local APIC of the CPU end end
- device pci_domain 0 on # PCI domain + device pci_domain 0 on // PCI domain subsystemid 0x1043 0x815a inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/ite/it8712f # Super I/O - device pnp 2e.0 on # Floppy + chip northbridge/amd/amdk8 // Northbridge / RAM controller + device pci 18.0 on // Link 0 == LDT 0 + chip southbridge/nvidia/ck804 // Southbridge + device pci 0.0 on end // HT + device pci 1.0 on // LPC + chip superio/ite/it8712f // Super I/O + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Com1 + device pnp 2e.1 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 off # Com2 (N/A on this board) + device pnp 2e.2 off // Com2 (N/A on this board) io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 on # Parallel port + device pnp 2e.3 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 end - device pnp 2e.4 on # Environment controller + device pnp 2e.4 on // Environment controller io 0x60 = 0x290 io 0x62 = 0x0000 irq 0x70 = 0x00 end - device pnp 2e.5 on # PS/2 keyboard + device pnp 2e.5 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x71 = 2 end - device pnp 2e.6 on # PS/2 mouse + device pnp 2e.6 on // PS/2 mouse irq 0x70 = 12 irq 0x71 = 2 end - device pnp 2e.7 on # GPIO config + device pnp 2e.7 on // GPIO config io 0x60 = 0x0800 - # Set GPIO 1 & 2 + // Set GPIO 1 & 2 io 0x25 = 0x0000 - # Set GPIO 3 & 4 + // Set GPIO 3 & 4 io 0x27 = 0x2540 - # GPIO Polarity for Set 3 + // GPIO Polarity for Set 3 io 0xb2 = 0x2100 - # GPIO Pin Internal Pull up for Set 3 + // GPIO Pin Internal Pull up for Set 3 io 0xba = 0x0100 - # Simple I/O register config + // Simple I/O register config io 0xc0 = 0x0000 io 0xc2 = 0x2540 io 0xc8 = 0x0000 io 0xca = 0x0500 end - device pnp 2e.8 on # MIDI port + device pnp 2e.8 on // MIDI port io 0x60 = 0x300 irq 0x70 = 10 end - device pnp 2e.9 on # Game port + device pnp 2e.9 on // Game port io 0x60 = 0x201 end - device pnp 2e.a off # IR (N/A on this board) + device pnp 2e.a off // IR (N/A on this board) io 0x60 = 0x310 irq 0x70 = 11 end end end - device pci 1.1 on # SM 0 - # chip drivers/generic/generic # DIMM 0-0-0 - # device i2c 50 on end - # end - # chip drivers/generic/generic # DIMM 0-0-1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # DIMM 0-1-0 - # device i2c 52 on end - # end - # chip drivers/generic/generic # DIMM 0-1-1 - # device i2c 53 on end - # end + device pci 1.1 on // SM 0 + // chip drivers/generic/generic # DIMM 0-0-0 + // device i2c 50 on end + // end + // chip drivers/generic/generic # DIMM 0-0-1 + // device i2c 51 on end + // end + // chip drivers/generic/generic # DIMM 0-1-0 + // device i2c 52 on end + // end + // chip drivers/generic/generic # DIMM 0-1-1 + // device i2c 53 on end + // end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # Onboard audio (ACI) - device pci 4.1 off end # Onboard modem (MCI), N/A - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on end # PCI - device pci a.0 on end # NIC - device pci b.0 on end # PCI E 3 - device pci c.0 on end # PCI E 2 - device pci d.0 on end # PCI E 1 - device pci e.0 on end # PCI E 0 + device pci 2.0 on end // USB 1.1 + device pci 2.1 on end // USB 2 + device pci 4.0 on end // Onboard audio (ACI) + device pci 4.1 off end // Onboard modem (MCI), N/A + device pci 6.0 on end // IDE + device pci 7.0 on end // SATA 1 + device pci 8.0 on end // SATA 0 + device pci 9.0 on end // PCI + device pci a.0 on end // NIC + device pci b.0 on end // PCI E 3 + device pci c.0 on end // PCI E 2 + device pci d.0 on end // PCI E 1 + device pci e.0 on end // PCI E 0 register "ide0_enable" = "1" register "ide1_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # TODO - # register "mac_eeprom_smbus" = "3" - # register "mac_eeprom_addr" = "0x51" + // TODO + // register "mac_eeprom_smbus" = "3" + // register "mac_eeprom_addr" = "0x51" end end device pci 18.1 on end diff --git a/src/mainboard/asus/a8v-e_deluxe/devicetree.cb b/src/mainboard/asus/a8v-e_deluxe/devicetree.cb index 31df8fa..17e41d7 100644 --- a/src/mainboard/asus/a8v-e_deluxe/devicetree.cb +++ b/src/mainboard/asus/a8v-e_deluxe/devicetree.cb @@ -1,92 +1,92 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device lapic_cluster 0 on # APIC cluster - chip cpu/amd/socket_939 # CPU - device lapic 0 on end # APIC +chip northbridge/amd/amdk8/root_complex // Root complex + device lapic_cluster 0 on // APIC cluster + chip cpu/amd/socket_939 // CPU + device lapic 0 on end // APIC end end - device pci_domain 0 on # PCI domain + device pci_domain 0 on // PCI domain subsystemid 1043 0 inherit - chip northbridge/amd/amdk8 # mc0 - device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 - chip southbridge/via/vt8237r # Southbridge - register "ide0_enable" = "1" # Enable IDE channel 0 - register "ide1_enable" = "1" # Enable IDE channel 1 - register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 - register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 - register "fn_ctrl_lo" = "0" # Enable SB functions - register "fn_ctrl_hi" = "0xad" # Enable SB functions - device pci 0.0 on end # HT - device pci f.1 on end # IDE - device pci 11.0 on # LPC - chip drivers/generic/generic # DIMM 0-0-0 + chip northbridge/amd/amdk8 // mc0 + device pci 18.0 on // Northbridge + // Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r // Southbridge + register "ide0_enable" = "1" // Enable IDE channel 0 + register "ide1_enable" = "1" // Enable IDE channel 1 + register "ide0_80pin_cable" = "1" // 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" // 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0" // Enable SB functions + register "fn_ctrl_hi" = "0xad" // Enable SB functions + device pci 0.0 on end // HT + device pci f.1 on end // IDE + device pci 11.0 on // LPC + chip drivers/generic/generic // DIMM 0-0-0 device i2c 50 on end end - chip drivers/generic/generic # DIMM 0-0-1 + chip drivers/generic/generic // DIMM 0-0-1 device i2c 51 on end end - chip drivers/generic/generic # DIMM 0-1-0 + chip drivers/generic/generic // DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 + chip drivers/generic/generic // DIMM 0-1-1 device i2c 53 on end end - chip superio/winbond/w83627ehg # Super I/O - device pnp 2e.0 on # Floppy + chip superio/winbond/w83627ehg // Super I/O + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Parallel port + device pnp 2e.1 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 (N/A on this board) + device pnp 2e.3 off // Com2 (N/A on this board) io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 off # PS/2 keyboard & mouse (off) + device pnp 2e.5 off // PS/2 keyboard & mouse (off) end - device pnp 2e.106 off # Serial flash interface (SFI) + device pnp 2e.106 off // Serial flash interface (SFI) io 0x60 = 0x100 end - device pnp 2e.007 off # GPIO 1 + device pnp 2e.007 off // GPIO 1 end - device pnp 2e.107 on # Game port + device pnp 2e.107 on // Game port io 0x60 = 0x201 end - device pnp 2e.207 on # MIDI + device pnp 2e.207 on // MIDI io 0x62 = 0x330 irq 0x70 = 0xa end - device pnp 2e.307 off # GPIO 6 + device pnp 2e.307 off // GPIO 6 end - device pnp 2e.8 off # WDTO#, PLED + device pnp 2e.8 off // WDTO#, PLED end - device pnp 2e.009 on # GPIO 2 + device pnp 2e.009 on // GPIO 2 end - device pnp 2e.109 off # GPIO 3 + device pnp 2e.109 off // GPIO 3 end - device pnp 2e.209 off # GPIO 4 + device pnp 2e.209 off // GPIO 4 end - device pnp 2e.309 on # GPIO 5 + device pnp 2e.309 on // GPIO 5 end - device pnp 2e.a off # ACPI + device pnp 2e.a off // ACPI end - device pnp 2e.b on # Hardware monitor + device pnp 2e.b on // Hardware monitor io 0x60 = 0x290 irq 0x70 = 0 end end end - device pci 12.0 off end # VIA LAN (off, other chip used) + device pci 12.0 off end // VIA LAN (off, other chip used) end - chip southbridge/via/k8t890 # "Southbridge" K8T890 + chip southbridge/via/k8t890 // "Southbridge" K8T890 end end device pci 18.1 on end diff --git a/src/mainboard/asus/a8v-e_se/devicetree.cb b/src/mainboard/asus/a8v-e_se/devicetree.cb index 3da93fe..bef66b6 100644 --- a/src/mainboard/asus/a8v-e_se/devicetree.cb +++ b/src/mainboard/asus/a8v-e_se/devicetree.cb @@ -1,92 +1,92 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device lapic_cluster 0 on # APIC cluster - chip cpu/amd/socket_939 # CPU - device lapic 0 on end # APIC +chip northbridge/amd/amdk8/root_complex // Root complex + device lapic_cluster 0 on // APIC cluster + chip cpu/amd/socket_939 // CPU + device lapic 0 on end // APIC end end - device pci_domain 0 on # PCI domain + device pci_domain 0 on // PCI domain subsystemid 0x1043 0 inherit - chip northbridge/amd/amdk8 # mc0 - device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 - chip southbridge/via/vt8237r # Southbridge - register "ide0_enable" = "1" # Enable IDE channel 0 - register "ide1_enable" = "1" # Enable IDE channel 1 - register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 - register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 - register "fn_ctrl_lo" = "0" # Enable SB functions - register "fn_ctrl_hi" = "0xad" # Enable SB functions - device pci 0.0 on end # HT - device pci f.1 on end # IDE - device pci 11.0 on # LPC - chip drivers/generic/generic # DIMM 0-0-0 + chip northbridge/amd/amdk8 // mc0 + device pci 18.0 on // Northbridge + // Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r // Southbridge + register "ide0_enable" = "1" // Enable IDE channel 0 + register "ide1_enable" = "1" // Enable IDE channel 1 + register "ide0_80pin_cable" = "1" // 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" // 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0" // Enable SB functions + register "fn_ctrl_hi" = "0xad" // Enable SB functions + device pci 0.0 on end // HT + device pci f.1 on end // IDE + device pci 11.0 on // LPC + chip drivers/generic/generic // DIMM 0-0-0 device i2c 50 on end end - chip drivers/generic/generic # DIMM 0-0-1 + chip drivers/generic/generic // DIMM 0-0-1 device i2c 51 on end end - chip drivers/generic/generic # DIMM 0-1-0 + chip drivers/generic/generic // DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 + chip drivers/generic/generic // DIMM 0-1-1 device i2c 53 on end end - chip superio/winbond/w83627ehg # Super I/O - device pnp 2e.0 on # Floppy + chip superio/winbond/w83627ehg // Super I/O + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Parallel port + device pnp 2e.1 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 (N/A on this board) + device pnp 2e.3 off // Com2 (N/A on this board) io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 off # PS/2 keyboard & mouse (off) + device pnp 2e.5 off // PS/2 keyboard & mouse (off) end - device pnp 2e.106 off # Serial flash interface (SFI) + device pnp 2e.106 off // Serial flash interface (SFI) io 0x60 = 0x100 end - device pnp 2e.007 off # GPIO 1 + device pnp 2e.007 off // GPIO 1 end - device pnp 2e.107 on # Game port + device pnp 2e.107 on // Game port io 0x60 = 0x201 end - device pnp 2e.207 on # MIDI + device pnp 2e.207 on // MIDI io 0x62 = 0x330 irq 0x70 = 0xa end - device pnp 2e.307 off # GPIO 6 + device pnp 2e.307 off // GPIO 6 end - device pnp 2e.8 off # WDTO#, PLED + device pnp 2e.8 off // WDTO#, PLED end - device pnp 2e.009 on # GPIO 2 + device pnp 2e.009 on // GPIO 2 end - device pnp 2e.109 off # GPIO 3 + device pnp 2e.109 off // GPIO 3 end - device pnp 2e.209 off # GPIO 4 + device pnp 2e.209 off // GPIO 4 end - device pnp 2e.309 on # GPIO 5 + device pnp 2e.309 on // GPIO 5 end - device pnp 2e.a off # ACPI + device pnp 2e.a off // ACPI end - device pnp 2e.b on # Hardware monitor + device pnp 2e.b on // Hardware monitor io 0x60 = 0x290 irq 0x70 = 0 end end end - device pci 12.0 off end # VIA LAN (off, other chip used) + device pci 12.0 off end // VIA LAN (off, other chip used) end - chip southbridge/via/k8t890 # "Southbridge" K8T890 + chip southbridge/via/k8t890 // "Southbridge" K8T890 end end device pci 18.1 on end diff --git a/src/mainboard/asus/m2n-e/devicetree.cb b/src/mainboard/asus/m2n-e/devicetree.cb index bf4de25..73b080f 100644 --- a/src/mainboard/asus/m2n-e/devicetree.cb +++ b/src/mainboard/asus/m2n-e/devicetree.cb @@ -1,117 +1,117 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Uwe Hermann uwe@hermann-uwe.de -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +// +// This file is part of the coreboot project. +// +// Copyright (C) 2010 Uwe Hermann uwe@hermann-uwe.de +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +//
-chip northbridge/amd/amdk8/root_complex # Root complex - device lapic_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_AM2 # CPU socket - device lapic 0 on end # Local APIC of the CPU +chip northbridge/amd/amdk8/root_complex // Root complex + device lapic_cluster 0 on // (L)APIC cluster + chip cpu/amd/socket_AM2 // CPU socket + device lapic 0 on end // Local APIC of the CPU end end - device pci_domain 0 on # PCI domain + device pci_domain 0 on // PCI domain subsystemid 0x1043 0x8239 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/ite/it8716f # Super I/O - device pnp 2e.0 on # Floppy + chip northbridge/amd/amdk8 // Northbridge / RAM controller + device pci 18.0 on // Link 0 == LDT 0 + chip southbridge/nvidia/mcp55 // Southbridge + device pci 0.0 on end // HT + device pci 1.0 on // LPC + chip superio/ite/it8716f // Super I/O + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Com1 + device pnp 2e.1 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 off # Com2 (N/A) + device pnp 2e.2 off // Com2 (N/A) end - device pnp 2e.3 on # Parallel port + device pnp 2e.3 on // Parallel port io 0x60 = 0x378 io 0x62 = 0x000 irq 0x70 = 7 drq 0x74 = 4 end - device pnp 2e.4 on # Environment controller + device pnp 2e.4 on // Environment controller io 0x60 = 0x290 io 0x62 = 0x000 irq 0x70 = 0 end - device pnp 2e.5 on # PS/2 keyboard + device pnp 2e.5 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard IRQ + irq 0x70 = 1 // PS/2 keyboard IRQ end - device pnp 2e.6 on # PS/2 mouse - irq 0x70 = 12 # PS/2 mouse IRQ + device pnp 2e.6 on // PS/2 mouse + irq 0x70 = 12 // PS/2 mouse IRQ end - device pnp 2e.7 off # GPIO - io 0x60 = 0x0000 # SMI# Normal Run Access - io 0x62 = 0x800 # Simple I/O - io 0x64 = 0x0000 # Serial Flash I/F + device pnp 2e.7 off // GPIO + io 0x60 = 0x0000 // SMI# Normal Run Access + io 0x62 = 0x800 // Simple I/O + io 0x64 = 0x0000 // Serial Flash I/F end - device pnp 2e.8 off # MIDI (N/A) + device pnp 2e.8 off // MIDI (N/A) end - device pnp 2e.9 off # Game port (N/A) + device pnp 2e.9 off // Game port (N/A) end - device pnp 2e.a off # Consumer IR (N/A) + device pnp 2e.a off // Consumer IR (N/A) end end end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 + device pci 1.1 on // SM 0 + chip drivers/generic/generic // DIMM 0-0-0 device i2c 50 on end end - chip drivers/generic/generic # DIMM 0-0-1 + chip drivers/generic/generic // DIMM 0-0-1 device i2c 51 on end end - chip drivers/generic/generic # DIMM 0-1-0 + chip drivers/generic/generic // DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 + chip drivers/generic/generic // DIMM 0-1-1 device i2c 53 on end end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on end # PCI - device pci 6.1 on end # Azalia (HD Audio) - device pci 8.0 on end # NIC - device pci 9.0 off end # NIC (N/A) - device pci a.0 on end # PCI E 5 (PCIEX4) - device pci b.0 off end # PCI E 4 - device pci c.0 on end # PCI E 3 (PCIEX1_2) - device pci d.0 on end # PCI E 2 (PCIEX1_1) - device pci e.0 off end # PCI E 1 - device pci f.0 on end # PCI E 0 (PCIEX16_1) - register "ide0_enable" = "1" # Primary IDE - register "ide1_enable" = "0" # Secondary IDE (N/A) + device pci 2.0 on end // USB 1.1 + device pci 2.1 on end // USB 2 + device pci 4.0 on end // IDE + device pci 5.0 on end // SATA 0 + device pci 5.1 on end // SATA 1 + device pci 5.2 on end // SATA 2 + device pci 6.0 on end // PCI + device pci 6.1 on end // Azalia (HD Audio) + device pci 8.0 on end // NIC + device pci 9.0 off end // NIC (N/A) + device pci a.0 on end // PCI E 5 (PCIEX4) + device pci b.0 off end // PCI E 4 + device pci c.0 on end // PCI E 3 (PCIEX1_2) + device pci d.0 on end // PCI E 2 (PCIEX1_1) + device pci e.0 off end // PCI E 1 + device pci f.0 on end // PCI E 0 (PCIEX16_1) + register "ide0_enable" = "1" // Primary IDE + register "ide1_enable" = "0" // Secondary IDE (N/A) register "sata0_enable" = "1" register "sata1_enable" = "1" end end - device pci 18.0 on end # Link 1 + device pci 18.0 on end // Link 1 device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end diff --git a/src/mainboard/asus/m2v-mx_se/devicetree.cb b/src/mainboard/asus/m2v-mx_se/devicetree.cb index 7e4c6d1..8239313 100644 --- a/src/mainboard/asus/m2v-mx_se/devicetree.cb +++ b/src/mainboard/asus/m2v-mx_se/devicetree.cb @@ -1,72 +1,72 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device lapic_cluster 0 on # APIC cluster - chip cpu/amd/socket_AM2 # CPU - device lapic 0 on end # APIC +chip northbridge/amd/amdk8/root_complex // Root complex + device lapic_cluster 0 on // APIC cluster + chip cpu/amd/socket_AM2 // CPU + device lapic 0 on end // APIC end end - device pci_domain 0 on # PCI domain + device pci_domain 0 on // PCI domain subsystemid 0x1043 0 inherit - chip northbridge/amd/amdk8 # mc0 - device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 - chip southbridge/via/vt8237r # Southbridge - register "ide0_enable" = "1" # Enable IDE channel 0 - register "ide1_enable" = "1" # Enable IDE channel 1 - register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 - register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 - register "fn_ctrl_lo" = "0xc0" # Enable SB functions - register "fn_ctrl_hi" = "0x1d" # Enable SB functions - device pci 0.0 on end # HT - device pci f.1 on end # IDE - device pci 11.0 on # LPC - chip drivers/generic/generic # DIMM 0-0-0 + chip northbridge/amd/amdk8 // mc0 + device pci 18.0 on // Northbridge + // Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r // Southbridge + register "ide0_enable" = "1" // Enable IDE channel 0 + register "ide1_enable" = "1" // Enable IDE channel 1 + register "ide0_80pin_cable" = "1" // 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" // 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0xc0" // Enable SB functions + register "fn_ctrl_hi" = "0x1d" // Enable SB functions + device pci 0.0 on end // HT + device pci f.1 on end // IDE + device pci 11.0 on // LPC + chip drivers/generic/generic // DIMM 0-0-0 device i2c 50 on end end - chip drivers/generic/generic # DIMM 0-0-1 + chip drivers/generic/generic // DIMM 0-0-1 device i2c 51 on end end - chip drivers/generic/generic # DIMM 0-1-0 + chip drivers/generic/generic // DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 + chip drivers/generic/generic // DIMM 0-1-1 device i2c 53 on end end - chip superio/ite/it8712f # Super I/O - device pnp 2e.0 on # Floppy + chip superio/ite/it8712f // Super I/O + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Com1 + device pnp 2e.1 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 off # Com2 + device pnp 2e.2 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 on # Parallel port + device pnp 2e.3 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.4 on # Environment controller + device pnp 2e.4 on // Environment controller io 0x60 = 0x290 io 0x62 = 0x230 irq 0x70 = 0x00 end - device pnp 2e.5 off end # PS/2 keyboard - device pnp 2e.6 off end # PS/2 mouse - device pnp 2e.7 off end # GPIO config - device pnp 2e.8 off end # Midi port - device pnp 2e.9 off end # Game port - device pnp 2e.a off end # IR + device pnp 2e.5 off end // PS/2 keyboard + device pnp 2e.6 off end // PS/2 mouse + device pnp 2e.7 off end // GPIO config + device pnp 2e.8 off end // Midi port + device pnp 2e.9 off end // Game port + device pnp 2e.a off end // IR end end - device pci 12.0 on end # VIA LAN - device pci 13.0 on end # br - device pci 13.1 on end # br2 need to have it here to discover it + device pci 12.0 on end // VIA LAN + device pci 13.0 on end // br + device pci 13.1 on end // br2 need to have it here to discover it end - chip southbridge/via/k8t890 # "Southbridge" K8M890 + chip southbridge/via/k8t890 // "Southbridge" K8M890 end end device pci 18.1 on end diff --git a/src/mainboard/asus/m2v/devicetree.cb b/src/mainboard/asus/m2v/devicetree.cb index 376dbf1..26d9d12 100644 --- a/src/mainboard/asus/m2v/devicetree.cb +++ b/src/mainboard/asus/m2v/devicetree.cb @@ -1,70 +1,70 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device lapic_cluster 0 on # APIC cluster - chip cpu/amd/socket_AM2 # CPU - device lapic 0 on end # APIC +chip northbridge/amd/amdk8/root_complex // Root complex + device lapic_cluster 0 on // APIC cluster + chip cpu/amd/socket_AM2 // CPU + device lapic 0 on end // APIC end end - device pci_domain 0 on # PCI domain + device pci_domain 0 on // PCI domain subsystemid 0x1043 0 inherit - chip northbridge/amd/amdk8 # mc0 - device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 - chip southbridge/via/vt8237r # Southbridge - register "ide0_enable" = "1" # Enable IDE channel 0 - register "ide1_enable" = "1" # Enable IDE channel 1 - register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 - register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 - register "fn_ctrl_lo" = "0xc0" # Enable SB functions - register "fn_ctrl_hi" = "0x0d" # Enable SB functions - device pci 0.0 on end # HT - device pci f.1 on end # IDE - device pci 11.0 on # LPC - chip drivers/generic/generic # DIMM 0-0-0 + chip northbridge/amd/amdk8 // mc0 + device pci 18.0 on // Northbridge + // Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r // Southbridge + register "ide0_enable" = "1" // Enable IDE channel 0 + register "ide1_enable" = "1" // Enable IDE channel 1 + register "ide0_80pin_cable" = "1" // 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" // 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0xc0" // Enable SB functions + register "fn_ctrl_hi" = "0x0d" // Enable SB functions + device pci 0.0 on end // HT + device pci f.1 on end // IDE + device pci 11.0 on // LPC + chip drivers/generic/generic // DIMM 0-0-0 device i2c 50 on end end - chip drivers/generic/generic # DIMM 0-0-1 + chip drivers/generic/generic // DIMM 0-0-1 device i2c 51 on end end - chip drivers/generic/generic # DIMM 0-1-0 + chip drivers/generic/generic // DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 + chip drivers/generic/generic // DIMM 0-1-1 device i2c 53 on end end - chip superio/ite/it8712f # Super I/O - device pnp 2e.0 on # Floppy + chip superio/ite/it8712f // Super I/O + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Com1 + device pnp 2e.1 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 off end # Com2 (N/A on this board) - device pnp 2e.3 on # Lpt1 + device pnp 2e.2 off end // Com2 (N/A on this board) + device pnp 2e.3 on // Lpt1 io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 end - device pnp 2e.4 on # Environment controller + device pnp 2e.4 on // Environment controller io 0x60 = 0xd00 io 0x62 = 0xc00 irq 0x70 = 0x00 end - device pnp 2e.5 off end # PS/2 keyboard - device pnp 2e.6 off end # PS/2 mouse - device pnp 2e.7 off end # GPIO config - device pnp 2e.8 off end # Midi port - device pnp 2e.9 off end # Game port - device pnp 2e.a off end # IR + device pnp 2e.5 off end // PS/2 keyboard + device pnp 2e.6 off end // PS/2 mouse + device pnp 2e.7 off end // GPIO config + device pnp 2e.8 off end // Midi port + device pnp 2e.9 off end // Game port + device pnp 2e.a off end // IR end end - device pci 12.0 off end # VIA LAN (off, other chip used) - device pci 13.0 on end # br - device pci 13.1 on end # br2, need to have it here to discover it + device pci 12.0 off end // VIA LAN (off, other chip used) + device pci 13.0 on end // br + device pci 13.1 on end // br2, need to have it here to discover it end - chip southbridge/via/k8t890 # "Southbridge" K8T890 + chip southbridge/via/k8t890 // "Southbridge" K8T890 end end device pci 18.1 on end diff --git a/src/mainboard/asus/m4a78-em/devicetree.cb b/src/mainboard/asus/m4a78-em/devicetree.cb index c463d71..4fdc831 100644 --- a/src/mainboard/asus/m4a78-em/devicetree.cb +++ b/src/mainboard/asus/m4a78-em/devicetree.cb @@ -1,27 +1,27 @@ chip northbridge/amd/amdfam10/root_complex device lapic_cluster 0 on - chip cpu/amd/socket_AM3 #L1 and DDR2 + chip cpu/amd/socket_AM3 //L1 and DDR2 device lapic 0 on end end end device pci_domain 0 on subsystemid 0x1043 0x83f1 inherit chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge + device pci 18.0 on // northbridge chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # bridge to RTL8112 PCI Express Gigabit Ethernet - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default + device pci 0.0 on end // HT 0x9600 + device pci 1.0 on end // Internal Graphics P2P bridge 0x9602 + device pci 2.0 on end // PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 on end // PCIE P2P bridge 0x960b + device pci 4.0 on end // PCIE P2P bridge 0x9604 + device pci 5.0 off end // PCIE P2P bridge 0x9605 + device pci 6.0 off end // PCIE P2P bridge 0x9606 + device pci 7.0 off end // PCIE P2P bridge 0x9607 + device pci 8.0 off end // NB/SB Link P2P bridge + device pci 9.0 on end // + device pci a.0 on end // bridge to RTL8112 PCI Express Gigabit Ethernet + register "gppsb_configuration" = "1" // Configuration B + register "gpp_configuration" = "3" // Configuration D default register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "2" @@ -32,68 +32,68 @@ chip northbridge/amd/amdfam10/root_complex register "gfx_reconfiguration" = "1" register "gfx_link_width" = "0" end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 + chip southbridge/amd/sb700 // it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end // SATA + device pci 12.0 on end // USB + device pci 12.1 on end // USB + device pci 12.2 on end // USB + device pci 13.0 on end // USB + device pci 13.1 on end // USB + device pci 13.2 on end // USB + device pci 14.0 on // SM + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 + chip drivers/generic/generic //dimm 0-0-1 device i2c 51 on end end - chip drivers/generic/generic #dimm 0-1-0 + chip drivers/generic/generic //dimm 0-1-0 device i2c 52 on end end - chip drivers/generic/generic #dimm 0-1-1 + chip drivers/generic/generic //dimm 0-1-1 device i2c 53 on end end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d + end // SM + device pci 14.1 on end // IDE 0x439c + device pci 14.2 on end // HDA 0x4383 + device pci 14.3 on // LPC 0x439d chip superio/ite/it8712f - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on # Com1 + device pnp 2e.0 off end // Floppy + device pnp 2e.1 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 off # Com2 + device pnp 2e.2 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 off # Parallel Port + device pnp 2e.3 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.4 off end # Environment Controller - device pnp 2e.5 on # Keyboard + device pnp 2e.4 off end // Environment Controller + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.6 on # Mouse + device pnp 2e.6 on // Mouse irq 0x70 = 12 end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + device pnp 2e.7 off // GPIO, must be closed for unresolved reason. end - device pnp 2e.8 off # MIDI + device pnp 2e.8 off // MIDI end - device pnp 2e.9 off # GAME + device pnp 2e.9 off // GAME end - device pnp 2e.a off end # CIR - end #superio - end #LPC - device pci 14.4 on end # PCI to PCI Bridge [1002:4384] - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 + device pnp 2e.a off end // CIR + end //superio + end //LPC + device pci 14.4 on end // PCI to PCI Bridge [1002:4384] + device pci 14.5 on end // USB 2 + register "boot_switch_sata_ide" = "0" // 0: boot from SATA. 1: IDE + end //southbridge/amd/sb700 + end // device pci 18.0
device pci 18.0 on end device pci 18.0 on end @@ -101,6 +101,6 @@ chip northbridge/amd/amdfam10/root_complex device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end - end # chip northbridge - end #pci_domain -end # northbridge/amd/amdfam10/root_complex + end // chip northbridge + end //pci_domain +end // northbridge/amd/amdfam10/root_complex diff --git a/src/mainboard/asus/m4a785-m/devicetree.cb b/src/mainboard/asus/m4a785-m/devicetree.cb index e8764b1..988a930 100644 --- a/src/mainboard/asus/m4a785-m/devicetree.cb +++ b/src/mainboard/asus/m4a785-m/devicetree.cb @@ -1,27 +1,27 @@ chip northbridge/amd/amdfam10/root_complex device lapic_cluster 0 on - chip cpu/amd/socket_AM3 #L1 and DDR2 + chip cpu/amd/socket_AM3 //L1 and DDR2 device lapic 0 on end end end device pci_domain 0 on subsystemid 0x1043 0x83a2 inherit chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge + device pci 18.0 on // northbridge chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 off end # PCIE P2P bridge 0x960b - device pci 4.0 off end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 off end # - device pci a.0 on end # bridge to RTL8111/8168B PCI Express Gigabit Ethernet - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default + device pci 0.0 on end // HT 0x9600 + device pci 1.0 on end // Internal Graphics P2P bridge 0x9602 + device pci 2.0 off end // PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 off end // PCIE P2P bridge 0x960b + device pci 4.0 off end // PCIE P2P bridge 0x9604 + device pci 5.0 off end // PCIE P2P bridge 0x9605 + device pci 6.0 off end // PCIE P2P bridge 0x9606 + device pci 7.0 off end // PCIE P2P bridge 0x9607 + device pci 8.0 off end // NB/SB Link P2P bridge + device pci 9.0 off end // + device pci a.0 on end // bridge to RTL8111/8168B PCI Express Gigabit Ethernet + register "gppsb_configuration" = "1" // Configuration B + register "gpp_configuration" = "3" // Configuration D default register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "2" @@ -32,68 +32,68 @@ chip northbridge/amd/amdfam10/root_complex register "gfx_reconfiguration" = "1" register "gfx_link_width" = "0" end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 + chip southbridge/amd/sb700 // it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end // SATA + device pci 12.0 on end // USB + device pci 12.1 on end // USB + device pci 12.2 on end // USB + device pci 13.0 on end // USB + device pci 13.1 on end // USB + device pci 13.2 on end // USB + device pci 14.0 on // SM + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 + chip drivers/generic/generic //dimm 0-0-1 device i2c 51 on end end - chip drivers/generic/generic #dimm 0-1-0 + chip drivers/generic/generic //dimm 0-1-0 device i2c 52 on end end - chip drivers/generic/generic #dimm 0-1-1 + chip drivers/generic/generic //dimm 0-1-1 device i2c 53 on end end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d + end // SM + device pci 14.1 on end // IDE 0x439c + device pci 14.2 on end // HDA 0x4383 + device pci 14.3 on // LPC 0x439d chip superio/ite/it8712f - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on # Com1 + device pnp 2e.0 off end // Floppy + device pnp 2e.1 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 off # Com2 + device pnp 2e.2 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 off # Parallel Port + device pnp 2e.3 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.4 off end # Environment Controller - device pnp 2e.5 on # Keyboard + device pnp 2e.4 off end // Environment Controller + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.6 on # Mouse + device pnp 2e.6 on // Mouse irq 0x70 = 12 end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + device pnp 2e.7 off // GPIO, must be closed for unresolved reason. end - device pnp 2e.8 off # MIDI + device pnp 2e.8 off // MIDI end - device pnp 2e.9 off # GAME + device pnp 2e.9 off // GAME end - device pnp 2e.a off end # CIR - end #superio - end #LPC - device pci 14.4 on end # PCI to PCI Bridge [1002:4384] - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 + device pnp 2e.a off end // CIR + end //superio + end //LPC + device pci 14.4 on end // PCI to PCI Bridge [1002:4384] + device pci 14.5 on end // USB 2 + register "boot_switch_sata_ide" = "0" // 0: boot from SATA. 1: IDE + end //southbridge/amd/sb700 + end // device pci 18.0
device pci 18.0 on end device pci 18.0 on end @@ -101,6 +101,6 @@ chip northbridge/amd/amdfam10/root_complex device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end - end # chip northbridge - end #pci_domain -end # northbridge/amd/amdfam10/root_complex + end // chip northbridge + end //pci_domain +end // northbridge/amd/amdfam10/root_complex diff --git a/src/mainboard/asus/mew-am/devicetree.cb b/src/mainboard/asus/mew-am/devicetree.cb index a4b80e1..6bbbeae 100644 --- a/src/mainboard/asus/mew-am/devicetree.cb +++ b/src/mainboard/asus/mew-am/devicetree.cb @@ -1,60 +1,60 @@ -chip northbridge/intel/i82810 # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device lapic 0 on end # APIC +chip northbridge/intel/i82810 // Northbridge + device lapic_cluster 0 on // APIC cluster + chip cpu/intel/socket_PGA370 // CPU + device lapic 0 on end // APIC end end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) - device pci 1.0 on end # Chipset Graphics Controller (CGC) - chip southbridge/intel/i82801ax # Southbridge + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Graphics Memory Controller Hub (GMCH) + device pci 1.0 on end // Chipset Graphics Controller (CGC) + chip southbridge/intel/i82801ax // Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1"
- device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA bridge - chip superio/smsc/smscsuperio # Super I/O - device pnp 2e.0 on # Floppy + device pci 1e.0 on end // PCI bridge + device pci 1f.0 on // ISA bridge + chip superio/smsc/smscsuperio // Super I/O + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.3 on # Parallel port + device pnp 2e.3 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 4 end - device pnp 2e.4 on # COM1 + device pnp 2e.4 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.5 on # COM2 / IR + device pnp 2e.5 on // COM2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.7 on # PS/2 keyboard / mouse + device pnp 2e.7 on // PS/2 keyboard / mouse io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt + irq 0x70 = 1 // PS/2 keyboard interrupt + irq 0x72 = 12 // PS/2 mouse interrupt end - device pnp 2e.9 on # Game port + device pnp 2e.9 on // Game port io 0x60 = 0x201 end - device pnp 2e.a on # Power-management events (PME) + device pnp 2e.a on // Power-management events (PME) io 0x60 = 0x600 end - device pnp 2e.b on # MIDI port (MPU-401) + device pnp 2e.b on // MIDI port (MPU-401) io 0x60 = 0x330 irq 0x70 = 5 end end end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMbus - device pci 1f.5 off end # AC'97 audio (N/A, uses CS4280 chip) - device pci 1f.6 off end # AC'97 modem (N/A) + device pci 1f.1 on end // IDE + device pci 1f.2 on end // USB + device pci 1f.3 on end // SMbus + device pci 1f.5 off end // AC'97 audio (N/A, uses CS4280 chip) + device pci 1f.6 off end // AC'97 modem (N/A) end end end diff --git a/src/mainboard/asus/mew-vm/devicetree.cb b/src/mainboard/asus/mew-vm/devicetree.cb index 29d706c..5735a6b 100644 --- a/src/mainboard/asus/mew-vm/devicetree.cb +++ b/src/mainboard/asus/mew-vm/devicetree.cb @@ -1,49 +1,49 @@ chip northbridge/intel/i82810 device pci_domain 0 on - device pci 0.0 on end # Host bridge - device pci 1.0 on # Onboard Video - # device pci 1.0 on end + device pci 0.0 on end // Host bridge + device pci 1.0 on // Onboard Video + // device pci 1.0 on end end - chip southbridge/intel/i82801ax # Southbridge + chip southbridge/intel/i82801ax // Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1"
- device pci 1e.0 on # PCI Bridge - # device pci 1.0 on end + device pci 1e.0 on // PCI Bridge + // device pci 1.0 on end end - device pci 1f.0 on # ISA/LPC? Bridge + device pci 1f.0 on // ISA/LPC? Bridge chip superio/smsc/lpc47b272 - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.3 off # Parallel Port + device pnp 2e.3 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.4 on # Com1 + device pnp 2e.4 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.5 off # Com2 + device pnp 2e.5 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.7 on # Keyboard + device pnp 2e.7 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # Keyboard interrupt - irq 0x72 = 12 # Mouse interrupt + irq 0x70 = 1 // Keyboard interrupt + irq 0x72 = 12 // Mouse interrupt end - device pnp 2e.a off end # ACPI + device pnp 2e.a off end // ACPI end end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # AC'97, no header on MEW-VM - device pci 1f.6 off end # AC'97 Modem (MC'97) + device pci 1f.1 on end // IDE + device pci 1f.2 on end // USB + device pci 1f.3 on end // SMBus + device pci 1f.5 off end // AC'97, no header on MEW-VM + device pci 1f.6 off end // AC'97 Modem (MC'97) end end chip cpu/intel/socket_PGA370 diff --git a/src/mainboard/asus/p2b-d/devicetree.cb b/src/mainboard/asus/p2b-d/devicetree.cb index 64219b7..9d50267 100644 --- a/src/mainboard/asus/p2b-d/devicetree.cb +++ b/src/mainboard/asus/p2b-d/devicetree.cb @@ -1,58 +1,58 @@ -chip northbridge/intel/i440bx # Northbridge - device lapic_cluster 0 on # (L)APIC cluster - chip cpu/intel/slot_1 # CPU socket 0 - device lapic 0 on end # Local APIC of CPU 0 +chip northbridge/intel/i440bx // Northbridge + device lapic_cluster 0 on // (L)APIC cluster + chip cpu/intel/slot_1 // CPU socket 0 + device lapic 0 on end // Local APIC of CPU 0 end - chip cpu/intel/slot_1 # CPU socket 1 - device lapic 1 on end # Local APIC of CPU 1 + chip cpu/intel/slot_1 // CPU socket 1 + device lapic 1 on end // Local APIC of CPU 1 end end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O - device pnp 3f0.0 on # Floppy + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + device pci 1.0 on end // PCI/AGP bridge + chip southbridge/intel/i82371eb // Southbridge + device pci 4.0 on // ISA bridge + chip superio/winbond/w83977tf // Super I/O + device pnp 3f0.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 3f0.1 on # Parallel port + device pnp 3f0.1 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 3f0.2 on # COM1 + device pnp 3f0.2 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 3f0.3 on # COM2 / IR + device pnp 3f0.3 on // COM2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 3f0.5 on # PS/2 keyboard / mouse + device pnp 3f0.5 on // PS/2 keyboard / mouse io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt + irq 0x70 = 1 // PS/2 keyboard interrupt + irq 0x72 = 12 // PS/2 mouse interrupt end - device pnp 3f0.7 on # GPIO 1 + device pnp 3f0.7 on // GPIO 1 end - device pnp 3f0.8 on # GPIO 2 + device pnp 3f0.8 on // GPIO 2 end - device pnp 3f0.9 on # GPIO 3 + device pnp 3f0.9 on // GPIO 3 end - device pnp 3f0.a on # ACPI + device pnp 3f0.a on // ACPI end end end - device pci 4.1 on end # IDE - device pci 4.2 on end # USB - device pci 4.3 on end # ACPI + device pci 4.1 on end // IDE + device pci 4.2 on end // USB + device pci 4.3 on end // ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. + // Enable UDMA/33 for higher speed if your IDE device(s) support it. register "ide0_drive0_udma33_enable" = "1" register "ide0_drive1_udma33_enable" = "1" register "ide1_drive0_udma33_enable" = "1" diff --git a/src/mainboard/asus/p2b-ds/devicetree.cb b/src/mainboard/asus/p2b-ds/devicetree.cb index 8a00f57..3a467bd 100644 --- a/src/mainboard/asus/p2b-ds/devicetree.cb +++ b/src/mainboard/asus/p2b-ds/devicetree.cb @@ -1,59 +1,59 @@ -chip northbridge/intel/i440bx # Northbridge - device lapic_cluster 0 on # (L)APIC cluster - chip cpu/intel/slot_1 # CPU socket 0 - device lapic 0 on end # Local APIC of CPU 0 +chip northbridge/intel/i440bx // Northbridge + device lapic_cluster 0 on // (L)APIC cluster + chip cpu/intel/slot_1 // CPU socket 0 + device lapic 0 on end // Local APIC of CPU 0 end - chip cpu/intel/slot_1 # CPU socket 1 - device lapic 1 on end # Local APIC of CPU 1 + chip cpu/intel/slot_1 // CPU socket 1 + device lapic 1 on end // Local APIC of CPU 1 end end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O - device pnp 3f0.0 on # Floppy + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + device pci 1.0 on end // PCI/AGP bridge + chip southbridge/intel/i82371eb // Southbridge + device pci 4.0 on // ISA bridge + chip superio/winbond/w83977tf // Super I/O + device pnp 3f0.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 3f0.1 on # Parallel port + device pnp 3f0.1 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 3f0.2 on # COM1 + device pnp 3f0.2 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 3f0.3 on # COM2 / IR + device pnp 3f0.3 on // COM2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 3f0.5 on # PS/2 keyboard / mouse + device pnp 3f0.5 on // PS/2 keyboard / mouse io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt + irq 0x70 = 1 // PS/2 keyboard interrupt + irq 0x72 = 12 // PS/2 mouse interrupt end - device pnp 3f0.7 on # GPIO 1 + device pnp 3f0.7 on // GPIO 1 end - device pnp 3f0.8 on # GPIO 2 + device pnp 3f0.8 on // GPIO 2 end - device pnp 3f0.9 on # GPIO 3 + device pnp 3f0.9 on // GPIO 3 end - device pnp 3f0.a on # ACPI + device pnp 3f0.a on // ACPI end end end - device pci 4.1 on end # IDE - device pci 4.2 on end # USB - device pci 4.3 on end # ACPI - device pci 6.0 on end # Onboard SCSI + device pci 4.1 on end // IDE + device pci 4.2 on end // USB + device pci 4.3 on end // ACPI + device pci 6.0 on end // Onboard SCSI register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. + // Enable UDMA/33 for higher speed if your IDE device(s) support it. register "ide0_drive0_udma33_enable" = "1" register "ide0_drive1_udma33_enable" = "1" register "ide1_drive0_udma33_enable" = "1" diff --git a/src/mainboard/asus/p2b-f/devicetree.cb b/src/mainboard/asus/p2b-f/devicetree.cb index 6fae008..6a6835e 100644 --- a/src/mainboard/asus/p2b-f/devicetree.cb +++ b/src/mainboard/asus/p2b-f/devicetree.cb @@ -1,55 +1,55 @@ -chip northbridge/intel/i440bx # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/slot_1 # CPU - device lapic 0 on end # APIC +chip northbridge/intel/i440bx // Northbridge + device lapic_cluster 0 on // APIC cluster + chip cpu/intel/slot_1 // CPU + device lapic 0 on end // APIC end end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) - device pnp 3f0.0 on # Floppy + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + device pci 1.0 on end // PCI/AGP bridge + chip southbridge/intel/i82371eb // Southbridge + device pci 4.0 on // ISA bridge + chip superio/winbond/w83977tf // Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 3f0.1 on # Parallel port + device pnp 3f0.1 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 3f0.2 on # COM1 + device pnp 3f0.2 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 3f0.3 on # COM2 / IR + device pnp 3f0.3 on // COM2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 3f0.5 on # PS/2 keyboard + device pnp 3f0.5 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt + irq 0x70 = 1 // PS/2 keyboard interrupt + irq 0x72 = 12 // PS/2 mouse interrupt end - device pnp 3f0.6 on # Consumer IR + device pnp 3f0.6 on // Consumer IR end - device pnp 3f0.7 on # GPIO 1 + device pnp 3f0.7 on // GPIO 1 end - device pnp 3f0.8 on # GPIO 2 + device pnp 3f0.8 on // GPIO 2 end - device pnp 3f0.a on # ACPI + device pnp 3f0.a on // ACPI end end end - device pci 4.1 on end # IDE - device pci 4.2 on end # USB - device pci 4.3 on end # ACPI + device pci 4.1 on end // IDE + device pci 4.2 on end // USB + device pci 4.3 on end // ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. + // Enable UDMA/33 for higher speed if your IDE device(s) support it. register "ide0_drive0_udma33_enable" = "0" register "ide0_drive1_udma33_enable" = "0" register "ide1_drive0_udma33_enable" = "0" diff --git a/src/mainboard/asus/p2b-ls/devicetree.cb b/src/mainboard/asus/p2b-ls/devicetree.cb index cc8281b..709ee21 100644 --- a/src/mainboard/asus/p2b-ls/devicetree.cb +++ b/src/mainboard/asus/p2b-ls/devicetree.cb @@ -1,55 +1,55 @@ -chip northbridge/intel/i440bx # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/slot_1 # CPU - device lapic 0 on end # APIC +chip northbridge/intel/i440bx // Northbridge + device lapic_cluster 0 on // APIC cluster + chip cpu/intel/slot_1 // CPU + device lapic 0 on end // APIC end end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) - device pnp 3f0.0 on # Floppy + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + device pci 1.0 on end // PCI/AGP bridge + chip southbridge/intel/i82371eb // Southbridge + device pci 4.0 on // ISA bridge + chip superio/winbond/w83977tf // Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 3f0.1 on # Parallel port + device pnp 3f0.1 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 3f0.2 on # COM1 + device pnp 3f0.2 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 3f0.3 on # COM2 / IR + device pnp 3f0.3 on // COM2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 3f0.5 on # PS/2 keyboard + device pnp 3f0.5 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt + irq 0x70 = 1 // PS/2 keyboard interrupt + irq 0x72 = 12 // PS/2 mouse interrupt end - device pnp 3f0.7 on # GPIO 1 + device pnp 3f0.7 on // GPIO 1 end - device pnp 3f0.8 on # GPIO 2 + device pnp 3f0.8 on // GPIO 2 end - device pnp 3f0.a on # ACPI + device pnp 3f0.a on // ACPI end end end - device pci 4.1 on end # IDE - device pci 4.2 on end # USB - device pci 4.3 on end # ACPI - device pci 6.0 on end # Onboard SCSI - device pci 7.0 on end # Onboard LAN + device pci 4.1 on end // IDE + device pci 4.2 on end // USB + device pci 4.3 on end // ACPI + device pci 6.0 on end // Onboard SCSI + device pci 7.0 on end // Onboard LAN register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. + // Enable UDMA/33 for higher speed if your IDE device(s) support it. register "ide0_drive0_udma33_enable" = "0" register "ide0_drive1_udma33_enable" = "0" register "ide1_drive0_udma33_enable" = "0" diff --git a/src/mainboard/asus/p2b/devicetree.cb b/src/mainboard/asus/p2b/devicetree.cb index f4bfbad..bae62ac 100644 --- a/src/mainboard/asus/p2b/devicetree.cb +++ b/src/mainboard/asus/p2b/devicetree.cb @@ -1,55 +1,55 @@ -chip northbridge/intel/i440bx # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/slot_1 # CPU - device lapic 0 on end # APIC +chip northbridge/intel/i440bx // Northbridge + device lapic_cluster 0 on // APIC cluster + chip cpu/intel/slot_1 // CPU + device lapic 0 on end // APIC end end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O - device pnp 3f0.0 on # Floppy + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + device pci 1.0 on end // PCI/AGP bridge + chip southbridge/intel/i82371eb // Southbridge + device pci 4.0 on // ISA bridge + chip superio/winbond/w83977tf // Super I/O + device pnp 3f0.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 3f0.1 on # Parallel port + device pnp 3f0.1 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 3f0.2 on # COM1 + device pnp 3f0.2 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 3f0.3 on # COM2 / IR + device pnp 3f0.3 on // COM2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 3f0.5 on # PS/2 keyboard / mouse + device pnp 3f0.5 on // PS/2 keyboard / mouse io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt + irq 0x70 = 1 // PS/2 keyboard interrupt + irq 0x72 = 12 // PS/2 mouse interrupt end - device pnp 3f0.7 on # GPIO 1 + device pnp 3f0.7 on // GPIO 1 end - device pnp 3f0.8 on # GPIO 2 + device pnp 3f0.8 on // GPIO 2 end - device pnp 3f0.9 on # GPIO 3 + device pnp 3f0.9 on // GPIO 3 end - device pnp 3f0.a on # ACPI + device pnp 3f0.a on // ACPI end end end - device pci 4.1 on end # IDE - device pci 4.2 on end # USB - device pci 4.3 on end # ACPI + device pci 4.1 on end // IDE + device pci 4.2 on end // USB + device pci 4.3 on end // ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. + // Enable UDMA/33 for higher speed if your IDE device(s) support it. register "ide0_drive0_udma33_enable" = "0" register "ide0_drive1_udma33_enable" = "0" register "ide1_drive0_udma33_enable" = "0" diff --git a/src/mainboard/asus/p3b-f/devicetree.cb b/src/mainboard/asus/p3b-f/devicetree.cb index 6fae008..6a6835e 100644 --- a/src/mainboard/asus/p3b-f/devicetree.cb +++ b/src/mainboard/asus/p3b-f/devicetree.cb @@ -1,55 +1,55 @@ -chip northbridge/intel/i440bx # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/slot_1 # CPU - device lapic 0 on end # APIC +chip northbridge/intel/i440bx // Northbridge + device lapic_cluster 0 on // APIC cluster + chip cpu/intel/slot_1 // CPU + device lapic 0 on end // APIC end end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) - device pnp 3f0.0 on # Floppy + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + device pci 1.0 on end // PCI/AGP bridge + chip southbridge/intel/i82371eb // Southbridge + device pci 4.0 on // ISA bridge + chip superio/winbond/w83977tf // Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 3f0.1 on # Parallel port + device pnp 3f0.1 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 3f0.2 on # COM1 + device pnp 3f0.2 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 3f0.3 on # COM2 / IR + device pnp 3f0.3 on // COM2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 3f0.5 on # PS/2 keyboard + device pnp 3f0.5 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt + irq 0x70 = 1 // PS/2 keyboard interrupt + irq 0x72 = 12 // PS/2 mouse interrupt end - device pnp 3f0.6 on # Consumer IR + device pnp 3f0.6 on // Consumer IR end - device pnp 3f0.7 on # GPIO 1 + device pnp 3f0.7 on // GPIO 1 end - device pnp 3f0.8 on # GPIO 2 + device pnp 3f0.8 on // GPIO 2 end - device pnp 3f0.a on # ACPI + device pnp 3f0.a on // ACPI end end end - device pci 4.1 on end # IDE - device pci 4.2 on end # USB - device pci 4.3 on end # ACPI + device pci 4.1 on end // IDE + device pci 4.2 on end // USB + device pci 4.3 on end // ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. + // Enable UDMA/33 for higher speed if your IDE device(s) support it. register "ide0_drive0_udma33_enable" = "0" register "ide0_drive1_udma33_enable" = "0" register "ide1_drive0_udma33_enable" = "0" diff --git a/src/mainboard/axus/tc320/devicetree.cb b/src/mainboard/axus/tc320/devicetree.cb index cf670c7..9f35b4a 100644 --- a/src/mainboard/axus/tc320/devicetree.cb +++ b/src/mainboard/axus/tc320/devicetree.cb @@ -1,55 +1,55 @@ -chip northbridge/amd/gx1 # Northbridge - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - chip southbridge/amd/cs5530 # Southbridge - device pci 12.0 on # ISA bridge - chip superio/nsc/pc97317 # Super I/O - device pnp 2e.0 on # PS/2 keyboard +chip northbridge/amd/gx1 // Northbridge + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + chip southbridge/amd/cs5530 // Southbridge + device pci 12.0 on // ISA bridge + chip superio/nsc/pc97317 // Super I/O + device pnp 2e.0 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.1 on # PS/2 mouse + device pnp 2e.1 on // PS/2 mouse irq 0x70 = 12 end - device pnp 2e.2 on # RTC, advanced power control (APC) + device pnp 2e.2 on // RTC, advanced power control (APC) io 0x60 = 0x70 irq 0x70 = 8 end - device pnp 2e.3 off # Floppy (N/A on this board) + device pnp 2e.3 off // Floppy (N/A on this board) io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.4 on # Parallel port + device pnp 2e.4 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.5 off # COM2 + device pnp 2e.5 off // COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.6 on # COM1 + device pnp 2e.6 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.7 on # GPIO + device pnp 2e.7 on // GPIO io 0x60 = 0xe0 end - device pnp 2e.8 on # Power management + device pnp 2e.8 on // Power management io 0x60 = 0xe800 end end end - device pci 12.1 off end # SMI - device pci 12.2 off end # IDE - device pci 12.3 on end # Audio - device pci 12.4 on end # VGA (onboard) - device pci 13.0 on end # USB - # register "ide0_enable" = "1" - # register "ide1_enable" = "1" + device pci 12.1 off end // SMI + device pci 12.2 off end // IDE + device pci 12.3 on end // Audio + device pci 12.4 on end // VGA (onboard) + device pci 13.0 on end // USB + // register "ide0_enable" = "1" + // register "ide1_enable" = "1" end end - chip cpu/amd/model_gx1 # CPU + chip cpu/amd/model_gx1 // CPU end end diff --git a/src/mainboard/azza/pt-6ibd/devicetree.cb b/src/mainboard/azza/pt-6ibd/devicetree.cb index 2448601..fc23329 100644 --- a/src/mainboard/azza/pt-6ibd/devicetree.cb +++ b/src/mainboard/azza/pt-6ibd/devicetree.cb @@ -1,55 +1,55 @@ -chip northbridge/intel/i440bx # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/slot_1 # CPU - device lapic 0 on end # APIC +chip northbridge/intel/i440bx // Northbridge + device lapic_cluster 0 on // APIC cluster + chip cpu/intel/slot_1 // CPU + device lapic 0 on end // APIC end end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 7.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) - device pnp 3f0.0 on # Floppy + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + device pci 1.0 on end // PCI/AGP bridge + chip southbridge/intel/i82371eb // Southbridge + device pci 7.0 on // ISA bridge + chip superio/winbond/w83977tf // Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 3f0.1 on # Parallel port + device pnp 3f0.1 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 3f0.2 on # COM1 + device pnp 3f0.2 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 3f0.3 on # COM2 / IR + device pnp 3f0.3 on // COM2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 3f0.5 on # PS/2 keyboard / mouse + device pnp 3f0.5 on // PS/2 keyboard / mouse io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt + irq 0x70 = 1 // PS/2 keyboard interrupt + irq 0x72 = 12 // PS/2 mouse interrupt end - device pnp 3f0.6 on # Consumer IR + device pnp 3f0.6 on // Consumer IR end - device pnp 3f0.7 on # GPIO 1 + device pnp 3f0.7 on // GPIO 1 end - device pnp 3f0.8 on # GPIO 2 + device pnp 3f0.8 on // GPIO 2 end - device pnp 3f0.a on # ACPI + device pnp 3f0.a on // ACPI end end end - device pci 7.1 on end # IDE - device pci 7.2 on end # USB - device pci 7.3 on end # ACPI + device pci 7.1 on end // IDE + device pci 7.2 on end // USB + device pci 7.3 on end // ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. + // Enable UDMA/33 for higher speed if your IDE device(s) support it. register "ide0_drive0_udma33_enable" = "0" register "ide0_drive1_udma33_enable" = "0" register "ide1_drive0_udma33_enable" = "0" diff --git a/src/mainboard/bcom/winnet100/devicetree.cb b/src/mainboard/bcom/winnet100/devicetree.cb index 872b8f3..dba82ba 100644 --- a/src/mainboard/bcom/winnet100/devicetree.cb +++ b/src/mainboard/bcom/winnet100/devicetree.cb @@ -1,56 +1,56 @@ -chip northbridge/amd/gx1 # Northbridge - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - chip southbridge/amd/cs5530 # Southbridge - device pci 0f.0 on end # Ethernet (onboard) - device pci 12.0 on # ISA bridge - chip superio/nsc/pc97317 # Super I/O - device pnp 2e.0 on # PS/2 keyboard +chip northbridge/amd/gx1 // Northbridge + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + chip southbridge/amd/cs5530 // Southbridge + device pci 0f.0 on end // Ethernet (onboard) + device pci 12.0 on // ISA bridge + chip superio/nsc/pc97317 // Super I/O + device pnp 2e.0 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.1 on # PS/2 mouse + device pnp 2e.1 on // PS/2 mouse irq 0x70 = 12 end - device pnp 2e.2 on # RTC, Advanced power control (APC) + device pnp 2e.2 on // RTC, Advanced power control (APC) io 0x60 = 0x70 irq 0x70 = 8 end - device pnp 2e.3 off # Floppy (N/A on this board) + device pnp 2e.3 off // Floppy (N/A on this board) io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.4 on # Parallel port + device pnp 2e.4 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.5 on # COM2 (used for smartcard reader) + device pnp 2e.5 on // COM2 (used for smartcard reader) io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.6 on # COM1 + device pnp 2e.6 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.7 on # GPIO + device pnp 2e.7 on // GPIO io 0x60 = 0xe0 end - device pnp 2e.8 on # Power management + device pnp 2e.8 on // Power management io 0x60 = 0xe8 end end end - device pci 12.1 off end # SMI - device pci 12.2 on end # IDE - device pci 12.3 on end # Audio - device pci 12.4 on end # VGA (onboard) - device pci 13.0 on end # USB + device pci 12.1 off end // SMI + device pci 12.2 on end // IDE + device pci 12.3 on end // Audio + device pci 12.4 on end // VGA (onboard) + device pci 13.0 on end // USB register "ide0_enable" = "1" - register "ide1_enable" = "0" # Not available/needed on this board + register "ide1_enable" = "0" // Not available/needed on this board end end - chip cpu/amd/model_gx1 # CPU + chip cpu/amd/model_gx1 // CPU end end diff --git a/src/mainboard/bcom/winnetp680/devicetree.cb b/src/mainboard/bcom/winnetp680/devicetree.cb index c86bc6a..742e3eb 100644 --- a/src/mainboard/bcom/winnetp680/devicetree.cb +++ b/src/mainboard/bcom/winnetp680/devicetree.cb @@ -1,64 +1,64 @@ -chip northbridge/via/cn700 # Northbridge - device pci_domain 0 on # PCI domain - device pci 0.0 on end # AGP Bridge - device pci 0.1 on end # Error Reporting - device pci 0.2 on end # Host Bus Control - device pci 0.3 on end # Memory Controller - device pci 0.4 on end # Power Management - device pci 0.7 on end # V-Link Controller - device pci 1.0 on end # PCI Bridge - chip southbridge/via/vt8237r # Southbridge - # Enable both IDE channels. +chip northbridge/via/cn700 // Northbridge + device pci_domain 0 on // PCI domain + device pci 0.0 on end // AGP Bridge + device pci 0.1 on end // Error Reporting + device pci 0.2 on end // Host Bus Control + device pci 0.3 on end // Memory Controller + device pci 0.4 on end // Power Management + device pci 0.7 on end // V-Link Controller + device pci 1.0 on end // PCI Bridge + chip southbridge/via/vt8237r // Southbridge + // Enable both IDE channels. register "ide0_enable" = "1" register "ide1_enable" = "1" - # Both cables are 40pin. + // Both cables are 40pin. register "ide0_80pin_cable" = "0" register "ide1_80pin_cable" = "0" register "fn_ctrl_lo" = "0x80" register "fn_ctrl_hi" = "0x1d" - device pci f.0 on end # IDE - device pci 10.0 on end # UHCI - device pci 10.1 on end # UHCI - device pci 10.2 on end # UHCI - device pci 10.3 on end # UHCI - device pci 10.4 on end # EHCI - device pci 11.0 on # Southbridge LPC - chip superio/winbond/w83697hf # Super I/O - device pnp 2e.0 off # Floppy + device pci f.0 on end // IDE + device pci 10.0 on end // UHCI + device pci 10.1 on end // UHCI + device pci 10.2 on end // UHCI + device pci 10.3 on end // UHCI + device pci 10.4 on end // EHCI + device pci 11.0 on // Southbridge LPC + chip superio/winbond/w83697hf // Super I/O + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Parallel Port + device pnp 2e.1 on // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 end - device pnp 2e.2 on # COM1 + device pnp 2e.2 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # COM2 + device pnp 2e.3 on // COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.6 off end # Consumer IR - device pnp 2e.7 off end # Game port, GPIO 1 - device pnp 2e.8 off end # MIDI port, GPIO 5 - device pnp 2e.9 off end # GPIO 2-4 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HWM + device pnp 2e.6 off end // Consumer IR + device pnp 2e.7 off end // Game port, GPIO 1 + device pnp 2e.8 off end // MIDI port, GPIO 5 + device pnp 2e.9 off end // GPIO 2-4 + device pnp 2e.a off end // ACPI + device pnp 2e.b on // HWM io 0x60 = 0x290 end end end - device pci 11.5 on end # AC'97 audio - device pci 12.0 on end # Ethernet + device pci 11.5 on end // AC'97 audio + device pci 12.0 on end // Ethernet end end - device lapic_cluster 0 on # APIC cluster - chip cpu/via/model_c7 # VIA C7 - device lapic 0 on end # APIC + device lapic_cluster 0 on // APIC cluster + chip cpu/via/model_c7 // VIA C7 + device lapic 0 on end // APIC end end end diff --git a/src/mainboard/biostar/m6tba/devicetree.cb b/src/mainboard/biostar/m6tba/devicetree.cb index faeb73a..5da92ac 100644 --- a/src/mainboard/biostar/m6tba/devicetree.cb +++ b/src/mainboard/biostar/m6tba/devicetree.cb @@ -1,49 +1,49 @@ -chip northbridge/intel/i440bx # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/slot_1 # CPU - device lapic 0 on end # APIC +chip northbridge/intel/i440bx // Northbridge + device lapic_cluster 0 on // APIC cluster + chip cpu/intel/slot_1 // CPU + device lapic 0 on end // APIC end end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 7.0 on # ISA bridge - chip superio/smsc/smscsuperio # Super I/O - device pnp 3f0.0 on # Floppy + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + device pci 1.0 on end // PCI/AGP bridge + chip southbridge/intel/i82371eb // Southbridge + device pci 7.0 on // ISA bridge + chip superio/smsc/smscsuperio // Super I/O + device pnp 3f0.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 3f0.3 on # Parallel port + device pnp 3f0.3 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 3f0.4 on # COM1 + device pnp 3f0.4 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 3f0.5 on # COM2 / IR + device pnp 3f0.5 on // COM2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 3f0.7 on # PS/2 keyboard / mouse + device pnp 3f0.7 on // PS/2 keyboard / mouse io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt + irq 0x70 = 1 // PS/2 keyboard interrupt + irq 0x72 = 12 // PS/2 mouse interrupt end - device pnp 3f0.8 on # Aux I/O + device pnp 3f0.8 on // Aux I/O end end end - device pci 7.1 on end # IDE - device pci 7.2 on end # USB - device pci 7.3 on end # ACPI + device pci 7.1 on end // IDE + device pci 7.2 on end // USB + device pci 7.3 on end // ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. + // Enable UDMA/33 for higher speed if your IDE device(s) support it. register "ide0_drive0_udma33_enable" = "0" register "ide0_drive1_udma33_enable" = "0" register "ide1_drive0_udma33_enable" = "0" diff --git a/src/mainboard/broadcom/blast/devicetree.cb b/src/mainboard/broadcom/blast/devicetree.cb index 6779a7a..3ae5f4a 100644 --- a/src/mainboard/broadcom/blast/devicetree.cb +++ b/src/mainboard/broadcom/blast/devicetree.cb @@ -7,108 +7,108 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on subsystemid 0x161f 0x3050 inherit chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge - # devices on link 0 - chip southbridge/broadcom/bcm5780 # HT2000 - device pci 0.0 on end # PXB 1 0x0130 - device pci 1.0 on # PXB 2 0x0130 - device pci 4.0 on end # GB E 0x1668 vid = 0x14e4 - device pci 4.1 on end # GB E 0x1669 vid = 0x14e4 + device pci 18.0 on // northbridge + // devices on link 0 + chip southbridge/broadcom/bcm5780 // HT2000 + device pci 0.0 on end // PXB 1 0x0130 + device pci 1.0 on // PXB 2 0x0130 + device pci 4.0 on end // GB E 0x1668 vid = 0x14e4 + device pci 4.1 on end // GB E 0x1669 vid = 0x14e4 end - device pci 2.0 on end # PCI E 1 #0x0132 - device pci 3.0 on end # PCI E 2 - device pci 4.0 on end # PCI E 3 - device pci 5.0 on end # PCI E 4 + device pci 2.0 on end // PCI E 1 #0x0132 + device pci 3.0 on end // PCI E 2 + device pci 4.0 on end // PCI E 3 + device pci 5.0 on end // PCI E 4 end - chip southbridge/broadcom/bcm5785 # HT1000 - device pci 0.0 on # HT PXB 0x0036 - device pci d.0 on end # PPBX 0x0104 - device pci e.0 on end # SATA 0x024a + chip southbridge/broadcom/bcm5785 // HT1000 + device pci 0.0 on // HT PXB 0x0036 + device pci d.0 on end // PPBX 0x0104 + device pci e.0 on end // SATA 0x024a end - device pci 1.0 on # Legacy pci main 0x0205 - chip drivers/i2c/i2cmux2 # pca9554 smbus mux - device i2c 71 on end #0 pca9554 0 - device i2c 71 on end #0 pca9554 1 - device i2c 71 on end #0 pca9554 2 - device i2c 71 on end #0 pca9554 3 - device i2c 71 on end #0 pca9554 4 - device i2c 71 on end #0 pca9554 5 - device i2c 71 on #0 pca9554 6 - chip drivers/generic/generic #dimm 0-0-0 + device pci 1.0 on // Legacy pci main 0x0205 + chip drivers/i2c/i2cmux2 // pca9554 smbus mux + device i2c 71 on end //0 pca9554 0 + device i2c 71 on end //0 pca9554 1 + device i2c 71 on end //0 pca9554 2 + device i2c 71 on end //0 pca9554 3 + device i2c 71 on end //0 pca9554 4 + device i2c 71 on end //0 pca9554 5 + device i2c 71 on //0 pca9554 6 + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 + chip drivers/generic/generic //dimm 0-0-1 device i2c 51 on end end - chip drivers/generic/generic #dimm 0-1-0 + chip drivers/generic/generic //dimm 0-1-0 device i2c 52 on end end - chip drivers/generic/generic #dimm 0-1-1 + chip drivers/generic/generic //dimm 0-1-1 device i2c 53 on end end end - device i2c 71 on #1 pca9554 7 - chip drivers/generic/generic #dimm 1-0-0 + device i2c 71 on //1 pca9554 7 + chip drivers/generic/generic //dimm 1-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 1-0-1 + chip drivers/generic/generic //dimm 1-0-1 device i2c 51 on end end - chip drivers/generic/generic #dimm 1-1-0 + chip drivers/generic/generic //dimm 1-1-0 device i2c 52 on end end - chip drivers/generic/generic #dimm 1-1-1 + chip drivers/generic/generic //dimm 1-1-1 device i2c 53 on end end end end
end - device pci 1.1 on end # IDE 0x0214 - device pci 1.2 on # LPC 0x0234 + device pci 1.1 on end // IDE 0x0214 + device pci 1.2 on // LPC 0x0234 chip superio/nsc/pc87417 - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 off # Com 2 + device pnp 2e.2 off // Com 2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 on # Com 1 + device pnp 2e.3 on // Com 1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.4 off end # SWC - device pnp 2e.5 off end # Mouse - device pnp 2e.6 on # Keyboard + device pnp 2e.4 off end // SWC + device pnp 2e.5 off end // Mouse + device pnp 2e.6 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.7 off end # GPIO - device pnp 2e.f off end # XBUS - device pnp 2e.10 on #RTC + device pnp 2e.7 off end // GPIO + device pnp 2e.f off end // XBUS + device pnp 2e.10 on //RTC io 0x60 = 0x70 io 0x62 = 0x72 end end end - device pci 1.3 on end # WDTimer 0x0238 - device pci 1.4 on end # XIOAPIC0 0x0235 - device pci 1.5 on end # XIOAPIC1 - device pci 1.6 on end # XIOAPIC2 - device pci 2.0 on end # USB 0x0223 - device pci 2.1 on end # USB - device pci 2.2 on end # USB - device pci 4.0 on end # it is in bcm5785_0 bus + device pci 1.3 on end // WDTimer 0x0238 + device pci 1.4 on end // XIOAPIC0 0x0235 + device pci 1.5 on end // XIOAPIC1 + device pci 1.6 on end // XIOAPIC2 + device pci 2.0 on end // USB 0x0223 + device pci 2.1 on end // USB + device pci 2.2 on end // USB + device pci 4.0 on end // it is in bcm5785_0 bus end - end # device pci 18.0 + end // device pci 18.0
device pci 18.0 on end device pci 18.0 on end @@ -118,17 +118,17 @@ chip northbridge/amd/amdk8/root_complex end
- end #pci_domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# end + end //pci_domain +// chip drivers/generic/debug +// device pnp 0.0 off end # chip name +// device pnp 0.1 on end # pci_regs_all +// device pnp 0.2 off end # mem +// device pnp 0.3 off end # cpuid +// device pnp 0.4 off end # smbus_regs_all +// device pnp 0.5 off end # dual core msr +// device pnp 0.6 off end # cache size +// device pnp 0.7 off end # tsc +// end
end
diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb b/src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb index a745126..2b786d8 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb +++ b/src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb @@ -1,59 +1,59 @@ -chip northbridge/intel/i440bx # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/slot_1 # CPU - device lapic 0 on end # APIC +chip northbridge/intel/i440bx // Northbridge + device lapic_cluster 0 on // APIC cluster + chip cpu/intel/slot_1 // CPU + device lapic 0 on end // APIC end end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - device pci a.0 on end # NIC (onboard) - chip southbridge/intel/i82371eb # Southbridge - device pci 14.0 on # ISA bridge - # chip superio/nsc/pc97307 # Super I/O - chip superio/nsc/pc97317 # Super I/O (FIXME: Should be PC97307!) - device pnp 15c.0 on # PS/2 keyboard + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + device pci 1.0 on end // PCI/AGP bridge + device pci a.0 on end // NIC (onboard) + chip southbridge/intel/i82371eb // Southbridge + device pci 14.0 on // ISA bridge + // chip superio/nsc/pc97307 # Super I/O + chip superio/nsc/pc97317 // Super I/O (FIXME: Should be PC97307!) + device pnp 15c.0 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 15c.1 on # PS/2 mouse + device pnp 15c.1 on // PS/2 mouse irq 0x70 = 12 end - device pnp 15c.2 on # RTC, APC + device pnp 15c.2 on // RTC, APC io 0x60 = 0x70 irq 0x70 = 8 end - device pnp 15c.3 on # Floppy + device pnp 15c.3 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 15c.4 on # Parallel port + device pnp 15c.4 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 15c.5 on # COM2 / IR + device pnp 15c.5 on // COM2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 15c.6 on # COM1 + device pnp 15c.6 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 15c.7 on # GPIO 1 + device pnp 15c.7 on // GPIO 1 end - device pnp 15c.8 on # Power management + device pnp 15c.8 on // Power management end end end - device pci 14.1 on end # IDE - device pci 14.2 on end # USB - device pci 14.3 on end # ACPI + device pci 14.1 on end // IDE + device pci 14.2 on end // USB + device pci 14.3 on end // ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. + // Enable UDMA/33 for higher speed if your IDE device(s) support it. register "ide0_drive0_udma33_enable" = "0" register "ide0_drive1_udma33_enable" = "0" register "ide1_drive0_udma33_enable" = "0" diff --git a/src/mainboard/dell/s1850/devicetree.cb b/src/mainboard/dell/s1850/devicetree.cb index c56fd37..b259042 100644 --- a/src/mainboard/dell/s1850/devicetree.cb +++ b/src/mainboard/dell/s1850/devicetree.cb @@ -1,18 +1,18 @@ -chip northbridge/intel/e7520 # mch +chip northbridge/intel/e7520 // mch device pci_domain 0 on subsystemid 0x15d9 0x5580 inherit - chip southbridge/intel/i82801ex # i82801er - # USB ports + chip southbridge/intel/i82801ex // i82801er + // USB ports device pci 1d.0 on end device pci 1d.1 on end device pci 1d.2 on end device pci 1d.3 on end device pci 1d.7 on end
- # -> Bridge + // -> Bridge device pci 1e.0 on end
- # -> ISA + // -> ISA device pci 1f.0 on chip superio/nsc/pc8374 device pnp 2e.0 off end @@ -29,9 +29,9 @@ chip northbridge/intel/e7520 # mch device pnp 2e.8 off end end end - # -> IDE + // -> IDE device pci 1f.1 on end - # -> SATA + // -> SATA device pci 1f.2 on end device pci 1f.3 on end
@@ -42,10 +42,10 @@ chip northbridge/intel/e7520 # mch device pci 00.1 on end device pci 01.0 on end device pci 02.0 on - chip southbridge/intel/pxhd # pxhd1 - # Bus bridges and ioapics usually bus 1 + chip southbridge/intel/pxhd // pxhd1 + // Bus bridges and ioapics usually bus 1 device pci 0.0 on - # On board gig e1000 + // On board gig e1000 chip drivers/generic/generic device pci 03.0 on end device pci 03.1 on end @@ -60,10 +60,10 @@ chip northbridge/intel/e7520 # mch device pci 06.0 on end end device lapic_cluster 0 on - chip cpu/intel/socket_mPGA604 # cpu 0 + chip cpu/intel/socket_mPGA604 // cpu 0 device lapic 0 on end end - chip cpu/intel/socket_mPGA604 # cpu 1 + chip cpu/intel/socket_mPGA604 // cpu 1 device lapic 6 on end end end diff --git a/src/mainboard/digitallogic/adl855pc/devicetree.cb b/src/mainboard/digitallogic/adl855pc/devicetree.cb index 756cb50..410b5e6 100644 --- a/src/mainboard/digitallogic/adl855pc/devicetree.cb +++ b/src/mainboard/digitallogic/adl855pc/devicetree.cb @@ -3,51 +3,51 @@ chip northbridge/intel/i855 device pci 0.0 on end device pci 1.0 on end chip southbridge/intel/i82801dx -# pci 11.0 on end -# pci 11.1 on end -# pci 11.2 on end -# pci 11.3 on end -# pci 11.4 on end -# pci 11.5 on end -# pci 11.6 on end -# pci 12.0 on end +// pci 11.0 on end +// pci 11.1 on end +// pci 11.2 on end +// pci 11.3 on end +// pci 11.4 on end +// pci 11.5 on end +// pci 11.6 on end +// pci 12.0 on end register "enable_usb" = "0" register "enable_native_ide" = "0" - chip superio/winbond/w83627hf # link 1 - device pnp 2e.0 on # Floppy + chip superio/winbond/w83627hf // link 1 + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.3 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GAME_MIDI_GIPO1 - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.6 off end // CIR + device pnp 2e.7 off end // GAME_MIDI_GIPO1 + device pnp 2e.8 off end // GPIO2 + device pnp 2e.9 off end // GPIO3 + device pnp 2e.a off end // ACPI + device pnp 2e.b on // HW Monitor io 0x60 = 0x290 end register "com1" = "{1}" - # register "com1" = "{1, 0, 0x3f8, 4}" - # register "lpt" = "{1}" + // register "com1" = "{1, 0, 0x3f8, 4}" + // register "lpt" = "{1}" end end end diff --git a/src/mainboard/digitallogic/msm586seg/devicetree.cb b/src/mainboard/digitallogic/msm586seg/devicetree.cb index 1ccf39f..edacdc9 100644 --- a/src/mainboard/digitallogic/msm586seg/devicetree.cb +++ b/src/mainboard/digitallogic/msm586seg/devicetree.cb @@ -1,10 +1,10 @@ chip cpu/amd/sc520 device pci_domain 0 on device pci 0.0 on end - device pci 12.0 on end # enet - device pci 14.0 on end # 69000 -# register "com1" = "{1}" -# register "com1" = "{1, 0, 0x3f8, 4}" + device pci 12.0 on end // enet + device pci 14.0 on end // 69000 +// register "com1" = "{1}" +// register "com1" = "{1, 0, 0x3f8, 4}" end
end diff --git a/src/mainboard/digitallogic/msm800sev/devicetree.cb b/src/mainboard/digitallogic/msm800sev/devicetree.cb index c4dfa17..5b9f079 100644 --- a/src/mainboard/digitallogic/msm800sev/devicetree.cb +++ b/src/mainboard/digitallogic/msm800sev/devicetree.cb @@ -3,79 +3,79 @@ chip northbridge/amd/lx device pci 1.0 on end device pci 1.1 on end chip southbridge/amd/cs5536 - # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK - # SIRQ Mode = Active(Quiet) mode. Save power.... - # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK - # How to get these? Boot linux and do this: - # rdmsr 0x51400025 + // IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + // SIRQ Mode = Active(Quiet) mode. Save power.... + // Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK + // How to get these? Boot linux and do this: + // rdmsr 0x51400025 register "lpc_serirq_enable" = "0x0000105a" - # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits + // rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits register "lpc_serirq_polarity" = "0x0000EFA5" - # mode is high 10 bits (determined from code) + // mode is high 10 bits (determined from code) register "lpc_serirq_mode" = "1" - # Don't yet know how to find this. + // Don't yet know how to find this. register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "0" #0: host, 1:device - register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "enable_ide_nand_flash" = "0" // 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" //0: host, 1:device + register "enable_USBP4_overcurrent" = "0" //0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) register "com1_enable" = "0" register "com1_address" = "0x3F8" register "com1_irq" = "4" register "com2_enable" = "0" register "com2_address" = "0x2F8" register "com2_irq" = "3" - register "unwanted_vpci[0]" = "0" # End of list has a zero - device pci f.0 on # ISA Bridge + register "unwanted_vpci[0]" = "0" // End of list has a zero + device pci f.0 on // ISA Bridge chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # Com2 + device pnp 2e.3 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # CIR + device pnp 2e.6 off // CIR io 0x60 = 0x100 end - device pnp 2e.7 off # GAME_MIDI_GIPO1 + device pnp 2e.7 off // GAME_MIDI_GIPO1 io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.8 off end // GPIO2 + device pnp 2e.9 off end // GPIO3 + device pnp 2e.a off end // ACPI + device pnp 2e.b on // HW Monitor io 0x60 = 0x290 irq 0x70 = 5 end end end - device pci f.1 on end # Flash controller - device pci f.2 on end # IDE controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI + device pci f.1 on end // Flash controller + device pci f.2 on end // IDE controller + device pci f.3 on end // Audio + device pci f.4 on end // OHCI + device pci f.5 on end // EHCI end end
- # APIC cluster is late CPU init. + // APIC cluster is late CPU init. device lapic_cluster 0 on chip cpu/amd/model_lx device lapic 0 on end diff --git a/src/mainboard/eaglelion/5bcm/devicetree.cb b/src/mainboard/eaglelion/5bcm/devicetree.cb index 7e55bca..98e7704 100644 --- a/src/mainboard/eaglelion/5bcm/devicetree.cb +++ b/src/mainboard/eaglelion/5bcm/devicetree.cb @@ -4,45 +4,45 @@ chip northbridge/amd/gx1 chip southbridge/amd/cs5530 device pci 12.0 on chip superio/nsc/pc97317 - device pnp 2e.0 on # Keyboard + device pnp 2e.0 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.1 on # Mouse + device pnp 2e.1 on // Mouse irq 0x70 = 12 end - device pnp 2e.2 on # RTC + device pnp 2e.2 on // RTC io 0x60 = 0x70 irq 0x70 = 8 end - device pnp 2e.3 off # FDC + device pnp 2e.3 off // FDC end - device pnp 2e.4 on # Parallel Port + device pnp 2e.4 on // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.5 on # COM2 + device pnp 2e.5 on // COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.6 on # COM1 + device pnp 2e.6 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.7 on # GPIO + device pnp 2e.7 on // GPIO io 0x60 = 0xe0 end - device pnp 2e.8 on # Power Management + device pnp 2e.8 on // Power Management io 0x60 = 0xe800 end register "com1" = "{115200}" register "com2" = "{38400}" end - device pci 12.1 off end # SMI - device pci 12.2 on end # IDE - device pci 12.3 off end # Audio - device pci 12.4 off end # VGA + device pci 12.1 off end // SMI + device pci 12.2 on end // IDE + device pci 12.3 off end // Audio + device pci 12.4 off end // VGA end end end diff --git a/src/mainboard/ecs/p6iwp-fe/devicetree.cb b/src/mainboard/ecs/p6iwp-fe/devicetree.cb index d2b8249..0b0c53c 100644 --- a/src/mainboard/ecs/p6iwp-fe/devicetree.cb +++ b/src/mainboard/ecs/p6iwp-fe/devicetree.cb @@ -1,86 +1,86 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Anders Jenbo anders@jenbo.dk -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +// +// This file is part of the coreboot project. +// +// Copyright (C) 2010 Anders Jenbo anders@jenbo.dk +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +//
-chip northbridge/intel/i82810 # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device lapic 0 on end # APIC +chip northbridge/intel/i82810 // Northbridge + device lapic_cluster 0 on // APIC cluster + chip cpu/intel/socket_PGA370 // CPU + device lapic 0 on end // APIC end end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) - device pci 1.0 on end # Chipset Graphics Controller (CGC) - chip southbridge/intel/i82801ax # Southbridge + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Graphics Memory Controller Hub (GMCH) + device pci 1.0 on end // Chipset Graphics Controller (CGC) + chip southbridge/intel/i82801ax // Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1"
- device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA bridge - chip superio/ite/it8712f # Super I/O - device pnp 2e.0 off # Floppy + device pci 1e.0 on end // PCI bridge + device pci 1f.0 on // ISA bridge + chip superio/ite/it8712f // Super I/O + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Com1 + device pnp 2e.1 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 on # Com2 + device pnp 2e.2 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 on # Parallel port + device pnp 2e.3 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.4 on # EC + device pnp 2e.4 on // EC io 0x60 = 0x290 io 0x62 = 0x230 irq 0x70 = 9 end - device pnp 2e.5 on # PS/2 keyboard + device pnp 2e.5 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.6 on # PS/2 mouse + device pnp 2e.6 on // PS/2 mouse irq 0x70 = 12 end - device pnp 2e.7 on # GPIO + device pnp 2e.7 on // GPIO io 0x62 = 0x1220 io 0x64 = 0x1200 end - device pnp 2e.8 off # MIDI + device pnp 2e.8 off // MIDI io 0x60 = 0x300 irq 0x70 = 9 end - device pnp 2e.9 off # Game port + device pnp 2e.9 off // Game port io 0x60 = 0x220 end - device pnp 2e.a off end # CIR + device pnp 2e.a off end // CIR end end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMBus + device pci 1f.1 on end // IDE + device pci 1f.2 on end // USB + device pci 1f.3 on end // SMBus end end end diff --git a/src/mainboard/emulation/qemu-x86/devicetree.cb b/src/mainboard/emulation/qemu-x86/devicetree.cb index 471cc33..13e04e4 100644 --- a/src/mainboard/emulation/qemu-x86/devicetree.cb +++ b/src/mainboard/emulation/qemu-x86/devicetree.cb @@ -2,14 +2,14 @@ chip mainboard/emulation/qemu-x86 device pci_domain 0 on device pci 0.0 on end
- chip southbridge/intel/i82371eb # southbridge + chip southbridge/intel/i82371eb // southbridge device pci 01.0 on end device pci 01.1 on end register "ide0_enable" = "1" register "ide1_enable" = "1" end
-# register "com1" = "{1}" -# register "com1" = "{1, 0, 0x3f8, 4}" +// register "com1" = "{1}" +// register "com1" = "{1, 0, 0x3f8, 4}" end end diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index 9b376c7..2cee768 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -1,23 +1,23 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2009 coresystems GmbH -## -## This program is free software; you can redistribute it and/or -## modify it under the terms of the GNU General Public License as -## published by the Free Software Foundation; version 2 of -## the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -## MA 02110-1301 USA -## +// +// This file is part of the coreboot project. +// +// Copyright (C) 2007-2009 coresystems GmbH +// +// This program is free software; you can redistribute it and/or +// modify it under the terms of the GNU General Public License as +// published by the Free Software Foundation; version 2 of +// the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +// MA 02110-1301 USA +//
chip northbridge/intel/i945
@@ -28,11 +28,11 @@ chip northbridge/intel/i945 end
device pci_domain 0 on - device pci 00.0 on end # host bridge - # autodetect: - #device pci 01.0 off end # i945 PCIe root port - #device pci 02.0 on end # vga controller - #device pci 02.1 on end # display controller + device pci 00.0 on end // host bridge + // autodetect: + //device pci 01.0 off end # i945 PCIe root port + //device pci 02.0 on end # vga controller + //device pci 02.1 on end # display controller
chip southbridge/intel/i82801gx register "pirqa_routing" = "0x0a" @@ -44,14 +44,14 @@ chip northbridge/intel/i945 register "pirqg_routing" = "0x0a" register "pirqh_routing" = "0x0a"
- # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) - register "gpi8_routing" = "1" # EXTSMI low active - register "gpi7_routing" = "2" # ECSCI low active + // GPI routing + // 0 No effect (default) + // 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + // 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi8_routing" = "1" // EXTSMI low active + register "gpi7_routing" = "2" // ECSCI low active
- # GPE0 Enables + // GPE0 Enables register "gpe0_en" = "0x00800106" register "alt_gp_smi_en" = "0x0100"
@@ -60,89 +60,89 @@ chip northbridge/intel/i945 register "ide_enable_secondary" = "0x0" register "sata_ahci" = "0x0"
- device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe port 1 - device pci 1c.1 on end # PCIe port 2 - device pci 1c.2 on end # PCIe port 3 - device pci 1c.3 on end # PCIe port 4 - #device pci 1c.4 off end # PCIe port 5 - #device pci 1c.5 off end # PCIe port 6 - device pci 1d.0 on end # USB UHCI - device pci 1d.1 on end # USB UHCI - device pci 1d.2 on end # USB UHCI - device pci 1d.3 on end # USB UHCI - device pci 1d.7 on end # USB2 EHCI + device pci 1b.0 on end // High Definition Audio + device pci 1c.0 on end // PCIe port 1 + device pci 1c.1 on end // PCIe port 2 + device pci 1c.2 on end // PCIe port 3 + device pci 1c.3 on end // PCIe port 4 + //device pci 1c.4 off end # PCIe port 5 + //device pci 1c.5 off end # PCIe port 6 + device pci 1d.0 on end // USB UHCI + device pci 1d.1 on end // USB UHCI + device pci 1d.2 on end // USB UHCI + device pci 1d.3 on end // USB UHCI + device pci 1d.7 on end // USB2 EHCI device pci 1e.0 on chip southbridge/ti/pcixx12 end - end # PCI bridge - #device pci 1e.2 off end # AC'97 Audio - #device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge + end // PCI bridge + //device pci 1e.2 off end # AC'97 Audio + //device pci 1e.3 off end # AC'97 Modem + device pci 1f.0 on // LPC bridge chip superio/smsc/fdc37n972 - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy end - device pnp 2e.1 off # ACPI PM + device pnp 2e.1 off // ACPI PM end - # 2e.2 does not exist - device pnp 2e.3 on # Parallel port + // 2e.2 does not exist + device pnp 2e.3 on // Parallel port io 0x60 = 0x378 irq 0x70 = 5 end - device pnp 2e.4 on # COM1 + device pnp 2e.4 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.5 off end - #device pnp 2e.6 on # RTC - # io 0x60 = 0x70 - # io 0x62 = 0x74 - #end - device pnp 2e.7 off # Keyboard + //device pnp 2e.6 on # RTC + // io 0x60 = 0x70 + // io 0x62 = 0x74 + //end + device pnp 2e.7 off // Keyboard end - device pnp 2e.8 off # EC + device pnp 2e.8 off // EC io 0x60 = 0x62 end - #device pnp 2e.9 on # Mailbox - #end + //device pnp 2e.9 on # Mailbox + //end end chip superio/smsc/sio10n268 - device pnp 4e.0 off # Floppy + device pnp 4e.0 off // Floppy end - device pnp 4e.1 off # Parport + device pnp 4e.1 off // Parport end - #device pnp 4e.2 on # COM3 - # io 0x60 = 0x3e8 - # irq 0x70 = 11 - #end - #device pnp 4e.3 on # COM4 - # io 0x60 = 0x2e8 - # irq 0x70 = 10 - #end - device pnp 4e.5 on # Keyboard + //device pnp 4e.2 on # COM3 + // io 0x60 = 0x3e8 + // irq 0x70 = 11 + //end + //device pnp 4e.3 on # COM4 + // io 0x60 = 0x2e8 + // irq 0x70 = 10 + //end + device pnp 4e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 end - device pnp 4e.7 off # GPIO1, GAME, MIDI + device pnp 4e.7 off // GPIO1, GAME, MIDI end - device pnp 4e.8 off # GPIO2 + device pnp 4e.8 off // GPIO2 end - device pnp 4e.9 off # GPIO3/4 + device pnp 4e.9 off // GPIO3/4 end - device pnp 4e.a off # ACPI + device pnp 4e.a off // ACPI end - device pnp 4e.b off # HWM + device pnp 4e.b off // HWM end chip ec/acpi end end
end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus + device pci 1f.1 on end // IDE + device pci 1f.2 on end // SATA + device pci 1f.3 on end // SMBus end end end diff --git a/src/mainboard/gigabyte/ga-6bxc/devicetree.cb b/src/mainboard/gigabyte/ga-6bxc/devicetree.cb index b5a4b5a..b506b69 100644 --- a/src/mainboard/gigabyte/ga-6bxc/devicetree.cb +++ b/src/mainboard/gigabyte/ga-6bxc/devicetree.cb @@ -1,53 +1,53 @@ -chip northbridge/intel/i440bx # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/slot_1 # CPU - device lapic 0 on end # APIC +chip northbridge/intel/i440bx // Northbridge + device lapic_cluster 0 on // APIC cluster + chip cpu/intel/slot_1 // CPU + device lapic 0 on end // APIC end end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 7.0 on # ISA bridge - chip superio/ite/it8671f # Super I/O - device pnp 3f0.0 on # Floppy + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + device pci 1.0 on end // PCI/AGP bridge + chip southbridge/intel/i82371eb // Southbridge + device pci 7.0 on // ISA bridge + chip superio/ite/it8671f // Super I/O + device pnp 3f0.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 3f0.1 on # COM1 + device pnp 3f0.1 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 3f0.2 on # COM2 / IR + device pnp 3f0.2 on // COM2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 3f0.3 on # Parallel port + device pnp 3f0.3 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 3f0.4 on # APC + device pnp 3f0.4 on // APC end - device pnp 3f0.5 on # PS/2 keyboard + device pnp 3f0.5 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 3f0.6 on # PS/2 mouse + device pnp 3f0.6 on // PS/2 mouse irq 0x70 = 12 end - device pnp 3f0.7 on # GPIO + device pnp 3f0.7 on // GPIO end end end - device pci 7.1 on end # IDE - device pci 7.2 on end # USB - device pci 7.3 on end # ACPI + device pci 7.1 on end // IDE + device pci 7.2 on end // USB + device pci 7.3 on end // ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. + // Enable UDMA/33 for higher speed if your IDE device(s) support it. register "ide0_drive0_udma33_enable" = "0" register "ide0_drive1_udma33_enable" = "0" register "ide1_drive0_udma33_enable" = "0" diff --git a/src/mainboard/gigabyte/ga-6bxe/devicetree.cb b/src/mainboard/gigabyte/ga-6bxe/devicetree.cb index f84c7b3..51caa78 100644 --- a/src/mainboard/gigabyte/ga-6bxe/devicetree.cb +++ b/src/mainboard/gigabyte/ga-6bxe/devicetree.cb @@ -1,53 +1,53 @@ -chip northbridge/intel/i440bx # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/slot_1 # CPU - device lapic 0 on end # APIC +chip northbridge/intel/i440bx // Northbridge + device lapic_cluster 0 on // APIC cluster + chip cpu/intel/slot_1 // CPU + device lapic 0 on end // APIC end end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 7.0 on # ISA bridge - chip superio/ite/it8671f # Super I/O - device pnp 3f0.0 on # Floppy + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + device pci 1.0 on end // PCI/AGP bridge + chip southbridge/intel/i82371eb // Southbridge + device pci 7.0 on // ISA bridge + chip superio/ite/it8671f // Super I/O + device pnp 3f0.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 3f0.1 on # COM1 + device pnp 3f0.1 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 3f0.2 on # COM2 / IR + device pnp 3f0.2 on // COM2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 3f0.3 on # Parallel port + device pnp 3f0.3 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 3f0.4 on # APC + device pnp 3f0.4 on // APC end - device pnp 3f0.5 on # PS/2 keyboard + device pnp 3f0.5 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 3f0.6 on # PS/2 mouse + device pnp 3f0.6 on // PS/2 mouse irq 0x70 = 12 end - device pnp 3f0.7 on # GPIO + device pnp 3f0.7 on // GPIO end end end - device pci 7.1 on end # IDE - device pci 7.2 on end # USB - device pci 7.3 on end # ACPI + device pci 7.1 on end // IDE + device pci 7.2 on end // USB + device pci 7.3 on end // ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. + // Enable UDMA/33 for higher speed if your IDE device(s) support it. register "ide0_drive0_udma33_enable" = "1" register "ide0_drive1_udma33_enable" = "1" register "ide1_drive0_udma33_enable" = "1" diff --git a/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb b/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb index e1aac4e..dd43632 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb +++ b/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb @@ -6,99 +6,99 @@ chip northbridge/amd/amdk8/root_complex end device pci_domain 0 on subsystemid 0x1039 0x1234 inherit - chip northbridge/amd/amdk8 #mc0 + chip northbridge/amd/amdk8 //mc0 device pci 18.0 on - # devices on link 0, link 0 == LDT 0 + // devices on link 0, link 0 == LDT 0 chip southbridge/sis/sis966 - device pci 0.0 on end # Northbridge - device pci 1.0 on # AGP bridge + device pci 0.0 on end // Northbridge + device pci 1.0 on // AGP bridge device pci 0.0 on end end - device pci 2.0 on # LPC + device pci 2.0 on // LPC chip superio/ite/it8716f - device pnp 2e.0 off # Floppy (N/A) + device pnp 2e.0 off // Floppy (N/A) io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Com1 + device pnp 2e.1 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 off # Com2 (N/A) + device pnp 2e.2 off // Com2 (N/A) io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 off # Parallel port (N/A) + device pnp 2e.3 off // Parallel port (N/A) io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.4 on # EC + device pnp 2e.4 on // EC io 0x60 = 0x290 io 0x62 = 0x230 irq 0x70 = 9 end - device pnp 2e.5 off # PS/2 keyboard (N/A) + device pnp 2e.5 off // PS/2 keyboard (N/A) io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.6 off # Mouse (N/A) + device pnp 2e.6 off // Mouse (N/A) irq 0x70 = 12 end - device pnp 2e.8 off # MIDI (N/A) + device pnp 2e.8 off // MIDI (N/A) io 0x60 = 0x300 irq 0x70 = 10 end - device pnp 2e.9 off # GAME (N/A) + device pnp 2e.9 off // GAME (N/A) io 0x60 = 0x220 end - device pnp 2e.a off end # CIR (N/A) + device pnp 2e.a off end // CIR (N/A) end end
- device pci 2.5 off end # IDE (SiS5513) - device pci 2.6 off end # Modem (SiS7013) - device pci 2.7 off end # Audio (SiS7012) - device pci 3.0 on end # USB (SiS7001,USB1.1) - device pci 3.1 on end # USB (SiS7001,USB1.1) - device pci 3.3 on end # USB (SiS7002,USB2.0) - device pci 4.0 on end # NIC (SiS191) - device pci 5.0 on end # SATA (SiS1183,Native Mode) - device pci 6.0 on end # PCI-e x1 - device pci 7.0 on end # PCI-e x1 + device pci 2.5 off end // IDE (SiS5513) + device pci 2.6 off end // Modem (SiS7013) + device pci 2.7 off end // Audio (SiS7012) + device pci 3.0 on end // USB (SiS7001,USB1.1) + device pci 3.1 on end // USB (SiS7001,USB1.1) + device pci 3.3 on end // USB (SiS7002,USB2.0) + device pci 4.0 on end // NIC (SiS191) + device pci 5.0 on end // SATA (SiS1183,Native Mode) + device pci 6.0 on end // PCI-e x1 + device pci 7.0 on end // PCI-e x1 device pci a.0 off end device pci b.0 off end device pci c.0 off end device pci d.0 off end device pci e.0 off end - device pci f.0 off end # HD Audio (SiS7502) + device pci f.0 off end // HD Audio (SiS7502)
register "ide0_enable" = "1" register "ide1_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" end - end # device pci 18.0 - device pci 18.0 on end # Link 1 + end // device pci 18.0 + device pci 18.0 on end // Link 1 device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end - end # mc0 + end // mc0
- end # PCI domain + end // PCI domain
-# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 off end # io -# end -end #root_complex +// chip drivers/generic/debug +// device pnp 0.0 off end # chip name +// device pnp 0.1 on end # pci_regs_all +// device pnp 0.2 off end # mem +// device pnp 0.3 off end # cpuid +// device pnp 0.4 off end # smbus_regs_all +// device pnp 0.5 off end # dual core msr +// device pnp 0.6 off end # cache size +// device pnp 0.7 off end # tsc +// device pnp 0.8 off end # io +// device pnp 0.9 off end # io +// end +end //root_complex diff --git a/src/mainboard/gigabyte/m57sli/devicetree.cb b/src/mainboard/gigabyte/m57sli/devicetree.cb index 2184de5..8991574 100644 --- a/src/mainboard/gigabyte/m57sli/devicetree.cb +++ b/src/mainboard/gigabyte/m57sli/devicetree.cb @@ -1,166 +1,166 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device lapic_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_AM2 # CPU socket - device lapic 0 on end # Local APIC of the CPU +chip northbridge/amd/amdk8/root_complex // Root complex + device lapic_cluster 0 on // (L)APIC cluster + chip cpu/amd/socket_AM2 // CPU socket + device lapic 0 on end // Local APIC of the CPU end end -device pci_domain 0 on # PCI domain +device pci_domain 0 on // PCI domain subsystemid 0x1022 0x2b80 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/ite/it8716f # Super I/O - device pnp 2e.0 on # Floppy and any LDN - # Watchdog from CLKIN (24 MHz) + chip northbridge/amd/amdk8 // Northbridge / RAM controller + device pci 18.0 on // Link 0 == LDT 0 + chip southbridge/nvidia/mcp55 // Southbridge + device pci 0.0 on end // HT + device pci 1.0 on // LPC + chip superio/ite/it8716f // Super I/O + device pnp 2e.0 on // Floppy and any LDN + // Watchdog from CLKIN (24 MHz) irq 0x23 = 0x11 - # Serial Flash (SPI only) - # 0x24 = 0x1a + // Serial Flash (SPI only) + // 0x24 = 0x1a io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Com1 + device pnp 2e.1 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 off # Com2 + device pnp 2e.2 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 on # Parallel port + device pnp 2e.3 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.4 on # Embedded controller + device pnp 2e.4 on // Embedded controller io 0x60 = 0x290 io 0x62 = 0x230 irq 0x70 = 9 end - device pnp 2e.5 on # PS/2 keyboard + device pnp 2e.5 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.6 on # PS/2 mouse + device pnp 2e.6 on // PS/2 mouse irq 0x70 = 12 end - device pnp 2e.7 on # GPIO, SPI flash - # Pin 84 is not GP10 + device pnp 2e.7 on // GPIO, SPI flash + // Pin 84 is not GP10 irq 0x25 = 0x0 - # Pin 21 is GP26, pin 26 is GP21, pin 27 is GP20 + // Pin 21 is GP26, pin 26 is GP21, pin 27 is GP20 irq 0x26 = 0x43 - # Pin 13 is GP35 + // Pin 13 is GP35 irq 0x27 = 0x20 - # Pin 70 is not GP46 - # irq 0x28 = 0x0 - # Pin 6,3,128,127,126 is GP63,64,65,66,67 + // Pin 70 is not GP46 + // irq 0x28 = 0x0 + // Pin 6,3,128,127,126 is GP63,64,65,66,67 irq 0x29 = 0x81 - # Enable FAN_CTL/FAN_TAC set to 5 (pin 21, 23), - # enable FAN_CTL/FAN_TAC set to 4 (pin 20, 22), - # pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal - # voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal - # voltage divider for VCC5V - # irq 0x2c = 0x1f - # Simple I/O base + // Enable FAN_CTL/FAN_TAC set to 5 (pin 21, 23), + // enable FAN_CTL/FAN_TAC set to 4 (pin 20, 22), + // pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal + // voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal + // voltage divider for VCC5V + // irq 0x2c = 0x1f + // Simple I/O base io 0x62 = 0x800 - # Serial Flash I/O (SPI only) + // Serial Flash I/O (SPI only) io 0x64 = 0x820 - # Watchdog force timeout (parallel flash only) - # irq 0x71 = 0x1 - # No WDT interrupt + // Watchdog force timeout (parallel flash only) + // irq 0x71 = 0x1 + // No WDT interrupt irq 0x72 = 0x0 - # GPIO pin set 1 disable internal pullup + // GPIO pin set 1 disable internal pullup irq 0xb8 = 0x0 - # GPIO pin set 5 enable internal pullup + // GPIO pin set 5 enable internal pullup irq 0xbc = 0x01 - # SIO pin set 1 alternate function - # irq 0xc0 = 0x0 - # SIO pin set 2 mixed function + // SIO pin set 1 alternate function + // irq 0xc0 = 0x0 + // SIO pin set 2 mixed function irq 0xc1 = 0x43 - # SIO pin set 3 mixed function + // SIO pin set 3 mixed function irq 0xc2 = 0x20 - # SIO pin set 4 alternate function - # irq 0xc3 = 0x0 - # SIO pin set 1 input mode - # irq 0xc8 = 0x0 - # SIO pin set 2 input mode + // SIO pin set 4 alternate function + // irq 0xc3 = 0x0 + // SIO pin set 1 input mode + // irq 0xc8 = 0x0 + // SIO pin set 2 input mode irq 0xc9 = 0x0 - # SIO pin set 4 input mode - # irq 0xcb = 0x0 - # Generate SMI# on EC IRQ - # irq 0xf0 = 0x10 - # SMI# level trigger - # irq 0xf1 = 0x40 - # HWMON alert beep pin location + // SIO pin set 4 input mode + // irq 0xcb = 0x0 + // Generate SMI# on EC IRQ + // irq 0xf0 = 0x10 + // SMI# level trigger + // irq 0xf1 = 0x40 + // HWMON alert beep pin location irq 0xf6 = 0x28 end - device pnp 2e.8 off # MIDI + device pnp 2e.8 off // MIDI io 0x60 = 0x300 irq 0x70 = 10 end - device pnp 2e.9 off # Game port + device pnp 2e.9 off // Game port io 0x60 = 0x220 end - device pnp 2e.a off end # Consumer IR + device pnp 2e.a off end // Consumer IR end end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 + device pci 1.1 on // SM 0 + chip drivers/generic/generic // DIMM 0-0-0 device i2c 50 on end end - chip drivers/generic/generic # DIMM 0-0-1 + chip drivers/generic/generic // DIMM 0-0-1 device i2c 51 on end end - chip drivers/generic/generic # DIMM 0-1-0 + chip drivers/generic/generic // DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 + chip drivers/generic/generic // DIMM 0-1-1 device i2c 53 on end end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on end # PCI - device pci 6.1 on end # AUDIO - device pci 8.0 on end # NIC - device pci 9.0 off end # N/A - device pci a.0 on end # PCI E 5 - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 + device pci 2.0 on end // USB 1.1 + device pci 2.1 on end // USB 2 + device pci 4.0 on end // IDE + device pci 5.0 on end // SATA 0 + device pci 5.1 on end // SATA 1 + device pci 5.2 on end // SATA 2 + device pci 6.0 on end // PCI + device pci 6.1 on end // AUDIO + device pci 8.0 on end // NIC + device pci 9.0 off end // N/A + device pci a.0 on end // PCI E 5 + device pci b.0 on end // PCI E 4 + device pci c.0 on end // PCI E 3 + device pci d.0 on end // PCI E 2 + device pci e.0 on end // PCI E 1 + device pci f.0 on end // PCI E 0 register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 + // 1: SMBus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" end end - device pci 18.0 on end # Link 1 + device pci 18.0 on end // Link 1 device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end # chip name - # device pnp 0.1 on end # pci_regs_all - # device pnp 0.2 on end # mem - # device pnp 0.3 off end # cpuid - # device pnp 0.4 on end # smbus_regs_all - # device pnp 0.5 off end # dual core msr - # device pnp 0.6 off end # cache size - # device pnp 0.7 off end # tsc - # device pnp 0.8 off end # io - # device pnp 0.9 off end # io - # end + // chip drivers/generic/debug + // device pnp 0.0 off end # chip name + // device pnp 0.1 on end # pci_regs_all + // device pnp 0.2 on end # mem + // device pnp 0.3 off end # cpuid + // device pnp 0.4 on end # smbus_regs_all + // device pnp 0.5 off end # dual core msr + // device pnp 0.6 off end # cache size + // device pnp 0.7 off end # tsc + // device pnp 0.8 off end # io + // device pnp 0.9 off end # io + // end end diff --git a/src/mainboard/gigabyte/ma785gmt/devicetree.cb b/src/mainboard/gigabyte/ma785gmt/devicetree.cb index 02e4bc8..585d909 100644 --- a/src/mainboard/gigabyte/ma785gmt/devicetree.cb +++ b/src/mainboard/gigabyte/ma785gmt/devicetree.cb @@ -1,28 +1,28 @@ -# sample config for gigabyte ga785gmt +// sample config for gigabyte ga785gmt chip northbridge/amd/amdfam10/root_complex device lapic_cluster 0 on - chip cpu/amd/socket_AM3 #L1 and DDR3 + chip cpu/amd/socket_AM3 //L1 and DDR3 device lapic 0 on end end end device pci_domain 0 on subsystemid 0x1022 0x3060 inherit chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge + device pci 18.0 on // northbridge chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default + device pci 0.0 on end // HT 0x9600 + device pci 1.0 on end // Internal Graphics P2P bridge 0x9602 + device pci 2.0 on end // PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 on end // PCIE P2P bridge 0x960b + device pci 4.0 on end // PCIE P2P bridge 0x9604 + device pci 5.0 off end // PCIE P2P bridge 0x9605 + device pci 6.0 off end // PCIE P2P bridge 0x9606 + device pci 7.0 off end // PCIE P2P bridge 0x9607 + device pci 8.0 off end // NB/SB Link P2P bridge + device pci 9.0 on end // + device pci a.0 on end // + register "gppsb_configuration" = "1" // Configuration B + register "gpp_configuration" = "3" // Configuration D default register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "2" @@ -33,75 +33,75 @@ chip northbridge/amd/amdfam10/root_complex register "gfx_reconfiguration" = "1" register "gfx_link_width" = "0" end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 + chip southbridge/amd/sb700 // it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end // SATA + device pci 12.0 on end // USB + device pci 12.1 on end // USB + device pci 12.2 on end // USB + device pci 13.0 on end // USB + device pci 13.1 on end // USB + device pci 13.2 on end // USB + device pci 14.0 on // SM + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 + chip drivers/generic/generic //dimm 0-0-1 device i2c 51 on end end - chip drivers/generic/generic #dimm 0-1-0 + chip drivers/generic/generic //dimm 0-1-0 device i2c 52 on end end - chip drivers/generic/generic #dimm 0-1-1 + chip drivers/generic/generic //dimm 0-1-1 device i2c 53 on end end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d + end // SM + device pci 14.1 on end // IDE 0x439c + device pci 14.2 on end // HDA 0x4383 + device pci 14.3 on // LPC 0x439d chip superio/ite/it8718f - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Com1 + device pnp 2e.1 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 off # Com2 + device pnp 2e.2 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 off # Parallel Port + device pnp 2e.3 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard + device pnp 2e.4 off end // EC + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.6 on # Mouse + device pnp 2e.6 on // Mouse irq 0x70 = 12 end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + device pnp 2e.7 off // GPIO, must be closed for unresolved reason. end - device pnp 2e.8 off # MIDI + device pnp 2e.8 off // MIDI io 0x60 = 0x300 irq 0x70 = 9 end - device pnp 2e.9 off # GAME + device pnp 2e.9 off // GAME io 0x60 = 0x220 end - device pnp 2e.a off end # CIR - end #superio/ite/it8718f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 + device pnp 2e.a off end // CIR + end //superio/ite/it8718f + end //LPC + device pci 14.4 on end // PCI 0x4384 + device pci 14.5 on end // USB 2 + register "boot_switch_sata_ide" = "0" // 0: boot from SATA. 1: IDE + end //southbridge/amd/sb700 + end // device pci 18.0
device pci 18.0 on end device pci 18.0 on end @@ -110,6 +110,6 @@ chip northbridge/amd/amdfam10/root_complex device pci 18.3 on end device pci 18.4 on end end - end #pci_domain - #for node 32 to node 63 + end //pci_domain + //for node 32 to node 63 end diff --git a/src/mainboard/gigabyte/ma78gm/devicetree.cb b/src/mainboard/gigabyte/ma78gm/devicetree.cb index 1aa859f..60ab1c9 100644 --- a/src/mainboard/gigabyte/ma78gm/devicetree.cb +++ b/src/mainboard/gigabyte/ma78gm/devicetree.cb @@ -1,28 +1,28 @@ -# sample config for gigabyte/ma78gm +// sample config for gigabyte/ma78gm chip northbridge/amd/amdfam10/root_complex device lapic_cluster 0 on - chip cpu/amd/socket_AM2r2 #L1 and DDR2 + chip cpu/amd/socket_AM2r2 //L1 and DDR2 device lapic 0 on end end end device pci_domain 0 on subsystemid 0x1022 0x3060 inherit chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge + device pci 18.0 on // northbridge chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default + device pci 0.0 on end // HT 0x9600 + device pci 1.0 on end // Internal Graphics P2P bridge 0x9602 + device pci 2.0 on end // PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 on end // PCIE P2P bridge 0x960b + device pci 4.0 on end // PCIE P2P bridge 0x9604 + device pci 5.0 off end // PCIE P2P bridge 0x9605 + device pci 6.0 off end // PCIE P2P bridge 0x9606 + device pci 7.0 off end // PCIE P2P bridge 0x9607 + device pci 8.0 off end // NB/SB Link P2P bridge + device pci 9.0 on end // + device pci a.0 on end // + register "gppsb_configuration" = "1" // Configuration B + register "gpp_configuration" = "3" // Configuration D default register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "1" @@ -32,75 +32,75 @@ chip northbridge/amd/amdfam10/root_complex register "gfx_reconfiguration" = "1" register "gfx_link_width" = "0" end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 + chip southbridge/amd/sb700 // it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end // SATA + device pci 12.0 on end // USB + device pci 12.1 on end // USB + device pci 12.2 on end // USB + device pci 13.0 on end // USB + device pci 13.1 on end // USB + device pci 13.2 on end // USB + device pci 14.0 on // SM + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 + chip drivers/generic/generic //dimm 0-0-1 device i2c 51 on end end - chip drivers/generic/generic #dimm 0-1-0 + chip drivers/generic/generic //dimm 0-1-0 device i2c 52 on end end - chip drivers/generic/generic #dimm 0-1-1 + chip drivers/generic/generic //dimm 0-1-1 device i2c 53 on end end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d + end // SM + device pci 14.1 on end // IDE 0x439c + device pci 14.2 on end // HDA 0x4383 + device pci 14.3 on // LPC 0x439d chip superio/ite/it8718f - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Com1 + device pnp 2e.1 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 off # Com2 + device pnp 2e.2 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 off # Parallel Port + device pnp 2e.3 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard + device pnp 2e.4 off end // EC + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.6 on # Mouse + device pnp 2e.6 on // Mouse irq 0x70 = 12 end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + device pnp 2e.7 off // GPIO, must be closed for unresolved reason. end - device pnp 2e.8 off # MIDI + device pnp 2e.8 off // MIDI io 0x60 = 0x300 irq 0x70 = 9 end - device pnp 2e.9 off # GAME + device pnp 2e.9 off // GAME io 0x60 = 0x220 end - device pnp 2e.a off end # CIR - end #superio/ite/it8718f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 + device pnp 2e.a off end // CIR + end //superio/ite/it8718f + end //LPC + device pci 14.4 on end // PCI 0x4384 + device pci 14.5 on end // USB 2 + register "boot_switch_sata_ide" = "0" // 0: boot from SATA. 1: IDE + end //southbridge/amd/sb700 + end // device pci 18.0
device pci 18.0 on end device pci 18.0 on end @@ -108,8 +108,8 @@ chip northbridge/amd/amdfam10/root_complex device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end -# device pci 00.5 on end +// device pci 00.5 on end end - end #pci_domain - #for node 32 to node 63 + end //pci_domain + //for node 32 to node 63 end diff --git a/src/mainboard/hp/dl145_g1/devicetree.cb b/src/mainboard/hp/dl145_g1/devicetree.cb index 3237723..2f5b4f7 100644 --- a/src/mainboard/hp/dl145_g1/devicetree.cb +++ b/src/mainboard/hp/dl145_g1/devicetree.cb @@ -7,11 +7,11 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on subsystemid 0x1022 0x7460 inherit chip northbridge/amd/amdk8 - device pci 18.0 on end # link 0 - device pci 18.0 on end # link 1 - device pci 18.0 on # link 2 + device pci 18.0 on end // link 0 + device pci 18.0 on end // link 1 + device pci 18.0 on // link 2 chip southbridge/amd/amd8131 - # the on/off keyword is mandatory + // the on/off keyword is mandatory device pci 0.0 on end device pci 0.1 on end device pci 1.0 on end @@ -21,57 +21,57 @@ chip northbridge/amd/amdk8/root_complex device pci 3.0 off end end chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge + // this "device pci 0.0" is the parent the next one + // PCI bridge device pci 0.0 on - device pci 0.0 on end # LPC - device pci 0.1 on end # IDE - device pci 0.2 on end # SMbus - device pci 0.3 on end # ACPI + device pci 0.0 on end // LPC + device pci 0.1 on end // IDE + device pci 0.2 on end // SMbus + device pci 0.3 on end // ACPI device pci 1.0 off end - #device pci 5.0 on end # SiI - #device pci 6.0 on end + //device pci 5.0 on end # SiI + //device pci 6.0 on end end device pci 1.0 on chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 1 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # Com2 + device pnp 2e.3 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # CIR + device pnp 2e.6 off // CIR end - device pnp 2e.7 off # GAM_MIDI_GIPO1 + device pnp 2e.7 off // GAM_MIDI_GIPO1 io 0x60 = 0x201 io 0x62 = 0x330 irq 0x70 = 9 end - device pnp 2e.8 on # GPIO2 + device pnp 2e.8 on // GPIO2 end - device pnp 2e.9 on # GPIO3 + device pnp 2e.9 on // GPIO3 end - device pnp 2e.a on # ACPI + device pnp 2e.a on // ACPI end - device pnp 2e.b on # HW Monitor + device pnp 2e.b on // HW Monitor io 0x60 = 0x290 irq 0x70 = 5 end @@ -80,76 +80,76 @@ chip northbridge/amd/amdk8/root_complex device pci 1.1 on end device pci 1.2 on end device pci 1.3 on - chip drivers/generic/generic # ??? + chip drivers/generic/generic // ??? device i2c 08 on end end - chip drivers/i2c/i2cmux # pca9556 smbus mux - device i2c 18 on #0 pca9516 1 - # I don't know what 30-33 are for, - # they seem to have something to do with the DIMM's - chip drivers/generic/generic # ??? + chip drivers/i2c/i2cmux // pca9556 smbus mux + device i2c 18 on //0 pca9516 1 + // I don't know what 30-33 are for, + // they seem to have something to do with the DIMM's + chip drivers/generic/generic // ??? device i2c 30 on end end - chip drivers/generic/generic # ??? + chip drivers/generic/generic // ??? device i2c 31 on end end - chip drivers/generic/generic # ??? + chip drivers/generic/generic // ??? device i2c 32 on end end - chip drivers/generic/generic # ??? + chip drivers/generic/generic // ??? device i2c 33 on end end - chip drivers/generic/generic #dimm H0-0 + chip drivers/generic/generic //dimm H0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm H0-1 + chip drivers/generic/generic //dimm H0-1 device i2c 51 on end end - chip drivers/generic/generic #dimm H0-2 + chip drivers/generic/generic //dimm H0-2 device i2c 52 on end end - chip drivers/generic/generic #dimm H0-3 + chip drivers/generic/generic //dimm H0-3 device i2c 53 on end end end - device i2c 18 on #1 pca9516 2 - chip drivers/generic/generic # ??? + device i2c 18 on //1 pca9516 2 + chip drivers/generic/generic // ??? device i2c 30 on end end - chip drivers/generic/generic # ??? + chip drivers/generic/generic // ??? device i2c 31 on end end - chip drivers/generic/generic # ??? + chip drivers/generic/generic // ??? device i2c 32 on end end - chip drivers/generic/generic # ??? + chip drivers/generic/generic // ??? device i2c 33 on end end - chip drivers/generic/generic #dimm H1-0 + chip drivers/generic/generic //dimm H1-0 device i2c 50 on end end - chip drivers/generic/generic #dimm H1-1 + chip drivers/generic/generic //dimm H1-1 device i2c 51 on end end - chip drivers/generic/generic #dimm H1-2 + chip drivers/generic/generic //dimm H1-2 device i2c 52 on end end - chip drivers/generic/generic #dimm H1-3 + chip drivers/generic/generic //dimm H1-3 device i2c 53 on end end end end - chip drivers/generic/generic # ??? + chip drivers/generic/generic // ??? device i2c 69 on end end - end # acpi + end // acpi device pci 1.4 off end - device pci 1.5 off end # AC97 Audio - device pci 1.6 off end # MC97 Modem + device pci 1.5 off end // AC97 Audio + device pci 1.6 off end // MC97 Modem register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 + end // device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end diff --git a/src/mainboard/hp/dl145_g3/devicetree.cb b/src/mainboard/hp/dl145_g3/devicetree.cb index 1f4f042..1216bfc 100644 --- a/src/mainboard/hp/dl145_g3/devicetree.cb +++ b/src/mainboard/hp/dl145_g3/devicetree.cb @@ -5,73 +5,73 @@ chip northbridge/amd/amdk8/root_complex end end device pci_domain 0 on - chip northbridge/amd/amdk8 # northbridge - device pci 18.0 on # devices on link 0 - chip southbridge/broadcom/bcm21000 # HT2100 + chip northbridge/amd/amdk8 // northbridge + device pci 18.0 on // devices on link 0 + chip southbridge/broadcom/bcm21000 // HT2100 device pci 0.0 on - end # bridge to slot PCI-E 4x ?? + end // bridge to slot PCI-E 4x ?? device pci 1.0 on end device pci 2.0 on - end # unused - device pci 3.0 on # bridge to slot PCI-E 16x ?? + end // unused + device pci 3.0 on // bridge to slot PCI-E 16x ?? end device pci 4.0 on - end # unused + end // unused device pci 5.0 on - device pci 4.0 on end # BCM5715 NIC - device pci 4.1 on end # BCM5715 NIC + device pci 4.0 on end // BCM5715 NIC + device pci 4.1 on end // BCM5715 NIC end end - chip southbridge/broadcom/bcm5785 # HT1000 - device pci 0.0 on # HT PXB 0x0036 - device pci d.0 on end # PCI/PCI-X bridge 0x0104 - device pci e.0 on end # SATA 0x024a + chip southbridge/broadcom/bcm5785 // HT1000 + device pci 0.0 on // HT PXB 0x0036 + device pci d.0 on end // PCI/PCI-X bridge 0x0104 + device pci e.0 on end // SATA 0x024a end - device pci 1.0 on end # Legacy pci main 0x0205 - device pci 1.1 on end # IDE 0x0214 - device pci 1.2 on # LPC 0x0234 + device pci 1.0 on end // Legacy pci main 0x0205 + device pci 1.1 on end // IDE 0x0214 + device pci 1.2 on // LPC 0x0234 chip superio/nsc/pc87417 - device pnp 4e.0 off # Floppy + device pnp 4e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 4e.1 off # Parallel Port + device pnp 4e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 4e.2 off # Com 2 + device pnp 4e.2 off // Com 2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 4e.3 off # Com 1 + device pnp 4e.3 off // Com 1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 4e.4 off end # SWC - device pnp 4e.5 off end # Mouse - device pnp 4e.6 off # Keyboard + device pnp 4e.4 off end // SWC + device pnp 4e.5 off end // Mouse + device pnp 4e.6 off // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 4e.7 off end # GPIO - device pnp 4e.f off end # XBUS - device pnp 4e.10 on #RTC + device pnp 4e.7 off end // GPIO + device pnp 4e.f off end // XBUS + device pnp 4e.10 on //RTC io 0x60 = 0x70 io 0x62 = 0x72 end - end # end superio - end # end pci 1.2 - device pci 1.3 off end # WDTimer 0x0238 - device pci 1.4 on end # XIOAPIC0 0x0235 - device pci 1.5 on end # XIOAPIC1 - device pci 1.6 on end # XIOAPIC2 - device pci 2.0 on end # USB 0x0223 - device pci 2.1 on end # USB - device pci 2.2 on end # USB - device pci 3.0 on end # VGA + end // end superio + end // end pci 1.2 + device pci 1.3 off end // WDTimer 0x0238 + device pci 1.4 on end // XIOAPIC0 0x0235 + device pci 1.5 on end // XIOAPIC1 + device pci 1.6 on end // XIOAPIC2 + device pci 2.0 on end // USB 0x0223 + device pci 2.1 on end // USB + device pci 2.2 on end // USB + device pci 3.0 on end // VGA end end device pci 18.0 on end @@ -79,9 +79,9 @@ chip northbridge/amd/amdk8/root_complex device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end - end # amdk8 + end // amdk8
- end #pci_domain + end //pci_domain end
diff --git a/src/mainboard/hp/dl165_g6_fam10/devicetree.cb b/src/mainboard/hp/dl165_g6_fam10/devicetree.cb index 3c1302b..5fad8f1 100644 --- a/src/mainboard/hp/dl165_g6_fam10/devicetree.cb +++ b/src/mainboard/hp/dl165_g6_fam10/devicetree.cb @@ -5,75 +5,75 @@ chip northbridge/amd/amdfam10/root_complex end end device pci_domain 0 on - chip northbridge/amd/amdfam10 # northbridge + chip northbridge/amd/amdfam10 // northbridge device pci 18.0 on end device pci 18.0 on end - device pci 18.0 on # devices on link 2 - chip southbridge/broadcom/bcm21000 # HT2100 + device pci 18.0 on // devices on link 2 + chip southbridge/broadcom/bcm21000 // HT2100 device pci 0.0 on - end # bridge to slot PCI-E 4x ?? + end // bridge to slot PCI-E 4x ?? device pci 1.0 on end device pci 2.0 on - end # unused - device pci 3.0 on # bridge to slot PCI-E 16x ?? + end // unused + device pci 3.0 on // bridge to slot PCI-E 16x ?? end device pci 4.0 on - end # unused + end // unused device pci 5.0 on - device pci 4.0 on end # BCM5715 NIC - device pci 4.1 on end # BCM5715 NIC + device pci 4.0 on end // BCM5715 NIC + device pci 4.1 on end // BCM5715 NIC end end - chip southbridge/broadcom/bcm5785 # HT1000 - device pci 0.0 on # HT PXB 0x0036 - device pci d.0 on end # PCI/PCI-X bridge 0x0104 - device pci e.0 on end # SATA 0x024a + chip southbridge/broadcom/bcm5785 // HT1000 + device pci 0.0 on // HT PXB 0x0036 + device pci d.0 on end // PCI/PCI-X bridge 0x0104 + device pci e.0 on end // SATA 0x024a end - device pci 1.0 on end # Legacy pci main 0x0205 - device pci 1.1 on end # IDE 0x0214 - device pci 1.2 on # LPC 0x0234 + device pci 1.0 on end // Legacy pci main 0x0205 + device pci 1.1 on end // IDE 0x0214 + device pci 1.2 on // LPC 0x0234 chip superio/nsc/pc87417 - device pnp 4e.0 off # Floppy + device pnp 4e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 4e.1 off # Parallel Port + device pnp 4e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 4e.2 off # Com 2 + device pnp 4e.2 off // Com 2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 4e.3 off # Com 1 + device pnp 4e.3 off // Com 1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 4e.4 off end # SWC - device pnp 4e.5 off end # Mouse - device pnp 4e.6 off # Keyboard + device pnp 4e.4 off end // SWC + device pnp 4e.5 off end // Mouse + device pnp 4e.6 off // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 4e.7 off end # GPIO - device pnp 4e.f off end # XBUS - device pnp 4e.10 on #RTC + device pnp 4e.7 off end // GPIO + device pnp 4e.f off end // XBUS + device pnp 4e.10 on //RTC io 0x60 = 0x70 io 0x62 = 0x72 end - end # end superio - end # end pci 1.2 - device pci 1.3 off end # WDTimer 0x0238 - device pci 1.4 on end # XIOAPIC0 0x0235 - device pci 1.5 on end # XIOAPIC1 - device pci 1.6 on end # XIOAPIC2 - device pci 2.0 on end # USB 0x0223 - device pci 2.1 on end # USB - device pci 2.2 on end # USB - device pci 3.0 on end # VGA + end // end superio + end // end pci 1.2 + device pci 1.3 off end // WDTimer 0x0238 + device pci 1.4 on end // XIOAPIC0 0x0235 + device pci 1.5 on end // XIOAPIC1 + device pci 1.6 on end // XIOAPIC2 + device pci 2.0 on end // USB 0x0223 + device pci 2.1 on end // USB + device pci 2.2 on end // USB + device pci 3.0 on end // VGA end end device pci 18.0 on end @@ -82,9 +82,9 @@ chip northbridge/amd/amdfam10/root_complex device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end - end # amdfam10 + end // amdfam10
- end #pci_domain + end //pci_domain end
diff --git a/src/mainboard/hp/e_vectra_p2706t/devicetree.cb b/src/mainboard/hp/e_vectra_p2706t/devicetree.cb index 4a65844..6d9f454 100644 --- a/src/mainboard/hp/e_vectra_p2706t/devicetree.cb +++ b/src/mainboard/hp/e_vectra_p2706t/devicetree.cb @@ -1,58 +1,58 @@ -# TODO: i810E actually! -chip northbridge/intel/i82810 # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device lapic 0 on end # APIC +// TODO: i810E actually! +chip northbridge/intel/i82810 // Northbridge + device lapic_cluster 0 on // APIC cluster + chip cpu/intel/socket_PGA370 // CPU + device lapic 0 on end // APIC end end device pci_domain 0 on - device pci 0.0 on end # Host bridge - device pci 1.0 on end # Onboard VGA - chip southbridge/intel/i82801ax # Southbridge + device pci 0.0 on end // Host bridge + device pci 1.0 on end // Onboard VGA + chip southbridge/intel/i82801ax // Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1"
- device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA/LPC bridge - # TODO: PC87364 actually! - # TODO: Check Super I/O settings and compare to superiotool -d. - chip superio/nsc/pc87360 # Super I/O - device pnp 2e.0 on # Floppy + device pci 1e.0 on end // PCI bridge + device pci 1f.0 on // ISA/LPC bridge + // TODO: PC87364 actually! + // TODO: Check Super I/O settings and compare to superiotool -d. + chip superio/nsc/pc87360 // Super I/O + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Parallel port + device pnp 2e.1 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 end - device pnp 2e.2 on # Com2 + device pnp 2e.2 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 on # Com1 + device pnp 2e.3 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.4 off end # SWC - device pnp 2e.5 off end # PS/2 mouse - device pnp 2e.6 on # PS/2 keyboard + device pnp 2e.4 off end // SWC + device pnp 2e.5 off end // PS/2 mouse + device pnp 2e.6 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end # ACB - device pnp 2e.9 off end # FSCM - device pnp 2e.a off end # WDT + device pnp 2e.7 off end // GPIO + device pnp 2e.8 off end // ACB + device pnp 2e.9 off end // FSCM + device pnp 2e.a off end // WDT end end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMBus - device pci 1f.5 on end # AC'97 audio - device pci 1f.6 off end # AC'97 modem (N/A ?) + device pci 1f.1 on end // IDE + device pci 1f.2 on end // USB + device pci 1f.3 on end // SMBus + device pci 1f.5 on end // AC'97 audio + device pci 1f.6 off end // AC'97 modem (N/A ?) end end end diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index 3fbe863..044bba7 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -7,10 +7,10 @@ chip northbridge/intel/i945 end
device pci_domain 0 on - device pci 00.0 on end # host bridge - device pci 01.0 off end # i945 PCIe root port - device pci 02.0 on end # vga controller - device pci 02.1 on end # display controller + device pci 00.0 on end // host bridge + device pci 01.0 off end // i945 PCIe root port + device pci 02.0 on end // vga controller + device pci 02.1 on end // display controller
chip southbridge/intel/i82801gx register "pirqa_routing" = "0x05" @@ -22,10 +22,10 @@ chip northbridge/intel/i945 register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x06"
- # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) + // GPI routing + // 0 No effect (default) + // 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + // 2 SCI (if corresponding GPIO_EN bit is also set) register "gpi13_routing" = "1"
register "ide_legacy_combined" = "0x0" @@ -33,67 +33,67 @@ chip northbridge/intel/i945 register "ide_enable_secondary" = "0x0" register "sata_ahci" = "0x1"
- #device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe - device pci 1c.1 on end # PCIe - device pci 1c.2 on end # PCIe - #device pci 1c.3 off end # PCIe port 4 - #device pci 1c.4 off end # PCIe port 5 - #device pci 1c.5 off end # PCIe port 6 - device pci 1d.0 on end # USB UHCI - device pci 1d.1 on end # USB UHCI - device pci 1d.2 on end # USB UHCI - device pci 1d.3 on end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on end # PCI bridge - #device pci 1e.2 off end # AC'97 Audio - #device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge + //device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end // PCIe + device pci 1c.1 on end // PCIe + device pci 1c.2 on end // PCIe + //device pci 1c.3 off end # PCIe port 4 + //device pci 1c.4 off end # PCIe port 5 + //device pci 1c.5 off end # PCIe port 6 + device pci 1d.0 on end // USB UHCI + device pci 1d.1 on end // USB UHCI + device pci 1d.2 on end // USB UHCI + device pci 1d.3 on end // USB UHCI + device pci 1d.7 on end // USB2 EHCI + device pci 1e.0 on end // PCI bridge + //device pci 1e.2 off end # AC'97 Audio + //device pci 1e.3 off end # AC'97 Modem + device pci 1f.0 on // LPC bridge chip superio/winbond/w83627ehg - device pnp 4e.0 off # Floppy + device pnp 4e.0 off // Floppy end - device pnp 4e.1 off # Parport + device pnp 4e.1 off // Parport end - device pnp 4e.2 on # COM1 + device pnp 4e.2 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 4e.3 on # COM2 + device pnp 4e.3 on // COM2 io 0x60 = 0x2f8 irq 0x70 = 3 - irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq + irq 0xf1 = 4 // set IRMODE 0 # XXX not an irq end - device pnp 4e.5 on # PS/2 keyboard & mouse + device pnp 4e.5 on // PS/2 keyboard & mouse io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 - irq 0xf0 = 0x82 # HW accel A20. + irq 0xf0 = 0x82 // HW accel A20. end - device pnp 4e.106 off end # Serial flash interface (SFI) - device pnp 4e.007 off end # GPIO 1 - device pnp 4e.107 off end # Game port - device pnp 4e.207 on # MIDI + device pnp 4e.106 off end // Serial flash interface (SFI) + device pnp 4e.007 off end // GPIO 1 + device pnp 4e.107 off end // Game port + device pnp 4e.207 on // MIDI io 0x62 = 0x330 irq 0x70 = 9 end - device pnp 4e.307 off end # GPIO 6 - device pnp 4e.8 off end # WDTO#, PLED - device pnp 4e.009 on # GPIO 2 - # All default + device pnp 4e.307 off end // GPIO 6 + device pnp 4e.8 off end // WDTO#, PLED + device pnp 4e.009 on // GPIO 2 + // All default end - device pnp 4e.109 on # GPIO 3 - irq 0xf0 = 0xfb # set inputs/outputs + device pnp 4e.109 on // GPIO 3 + irq 0xf0 = 0xfb // set inputs/outputs irq 0xf1 = 0x66 end - device pnp 4e.209 on # GPIO 4 + device pnp 4e.209 on // GPIO 4 end - device pnp 4e.309 off # GPIO 5 + device pnp 4e.309 off // GPIO 5 end - device pnp 4e.a on # ACPI - # TODO: IRQ + device pnp 4e.a on // ACPI + // TODO: IRQ end - device pnp 4e.b on # HWM + device pnp 4e.b on // HWM io 0x60 = 0x290 irq 0x70 = 0 end @@ -101,10 +101,10 @@ chip northbridge/intel/i945 end
end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - #device pci 1f.4 off end # Realtek ID Codec + device pci 1f.1 on end // IDE + device pci 1f.2 on end // SATA + device pci 1f.3 on end // SMBus + //device pci 1f.4 off end # Realtek ID Codec end end end diff --git a/src/mainboard/ibm/e325/devicetree.cb b/src/mainboard/ibm/e325/devicetree.cb index 331e632..7bc253c 100644 --- a/src/mainboard/ibm/e325/devicetree.cb +++ b/src/mainboard/ibm/e325/devicetree.cb @@ -6,8 +6,8 @@ chip northbridge/amd/amdk8/root_complex end device pci_domain 0 on chip northbridge/amd/amdk8 - device pci 18.0 on end # LDT 0 - device pci 18.0 on # LDT 1 + device pci 18.0 on end // LDT 0 + device pci 18.0 on // LDT 1 chip southbridge/amd/amd8131 device pci 0.0 on end device pci 0.1 on end @@ -23,34 +23,34 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.0 on chip superio/nsc/pc87366 - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 off # Com 2 + device pnp 2e.2 off // Com 2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 on # Com 1 + device pnp 2e.3 on // Com 1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.4 off end # SWC - device pnp 2e.5 off end # Mouse - device pnp 2e.6 on # Keyboard + device pnp 2e.4 off end // SWC + device pnp 2e.5 off end // Mouse + device pnp 2e.6 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end # ACB - device pnp 2e.9 off end # FSCM - device pnp 2e.a off end # WDT + device pnp 2e.7 off end // GPIO + device pnp 2e.8 off end // ACB + device pnp 2e.9 off end // FSCM + device pnp 2e.a off end // WDT end end device pci 1.1 on end @@ -59,8 +59,8 @@ chip northbridge/amd/amdk8/root_complex device pci 1.5 off end device pci 1.6 off end end - end # device pci 18.0 - device pci 18.0 on end # LDT2 + end // device pci 18.0 + device pci 18.0 on end // LDT2 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end diff --git a/src/mainboard/ibm/e326/devicetree.cb b/src/mainboard/ibm/e326/devicetree.cb index 8826439..65797fc 100644 --- a/src/mainboard/ibm/e326/devicetree.cb +++ b/src/mainboard/ibm/e326/devicetree.cb @@ -7,8 +7,8 @@ chip northbridge/amd/amdk8/root_complex
device pci_domain 0 on chip northbridge/amd/amdk8 - device pci 18.0 on end # LDT 0 - device pci 18.0 on # LDT 1 + device pci 18.0 on end // LDT 0 + device pci 18.0 on // LDT 1 chip southbridge/amd/amd8131 device pci 0.0 on end device pci 0.1 on end @@ -21,38 +21,38 @@ chip northbridge/amd/amdk8/root_complex device pci 0.1 on end device pci 0.2 on end device pci 1.0 off end - device pci 5.0 on end # ATI Rage XL + device pci 5.0 on end // ATI Rage XL end device pci 1.0 on chip superio/nsc/pc87366 - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 off # Com 2 + device pnp 2e.2 off // Com 2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 on # Com 1 + device pnp 2e.3 on // Com 1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.4 off end # SWC - device pnp 2e.5 off end # Mouse - device pnp 2e.6 on # Keyboard + device pnp 2e.4 off end // SWC + device pnp 2e.5 off end // Mouse + device pnp 2e.6 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end # ACB - device pnp 2e.9 off end # FSCM - device pnp 2e.a off end # WDT + device pnp 2e.7 off end // GPIO + device pnp 2e.8 off end // ACB + device pnp 2e.9 off end // FSCM + device pnp 2e.a off end // WDT end end device pci 1.1 on end @@ -63,8 +63,8 @@ chip northbridge/amd/amdk8/root_complex register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 - device pci 18.0 on end # LDT2 + end // device pci 18.0 + device pci 18.0 on end // LDT2 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end diff --git a/src/mainboard/iei/juki-511p/devicetree.cb b/src/mainboard/iei/juki-511p/devicetree.cb index 486fbd5..aef9b3c 100644 --- a/src/mainboard/iei/juki-511p/devicetree.cb +++ b/src/mainboard/iei/juki-511p/devicetree.cb @@ -5,49 +5,49 @@ chip northbridge/amd/gx1
device pci 12.0 on chip superio/winbond/w83977f - device pnp 3f0.0 on # FDC + device pnp 3f0.0 on // FDC irq 0x70 = 6 end - device pnp 3f0.1 on # Parallel port + device pnp 3f0.1 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 3f0.2 on # COM1 + device pnp 3f0.2 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end register "com1" = "{115200}" - device pnp 3f0.3 on # COM2 + device pnp 3f0.3 on // COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end register "com2" = "{115200}" - device pnp 3f0.4 on # RTC + device pnp 3f0.4 on // RTC io 0x60 = 0x070 irq 0x70 = 8 end - device pnp 3f0.5 on # Keyboard + device pnp 3f0.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # Int 1 for PS/2 keyboard - irq 0x72 = 12 # Int 12 for PS/2 mouse + irq 0x70 = 1 // Int 1 for PS/2 keyboard + irq 0x72 = 12 // Int 12 for PS/2 mouse end - device pnp 3f0.6 off # IR + device pnp 3f0.6 off // IR end - device pnp 3f0.7 off # GPIO1 + device pnp 3f0.7 off // GPIO1 end - device pnp 3f0.8 off # GPIO + device pnp 3f0.8 off // GPIO end end - device pci 12.1 on end # SMI - device pci 12.2 on end # IDE - device pci 12.3 on end # Audio - device pci 12.4 on end # VGA onboard + device pci 12.1 on end // SMI + device pci 12.2 on end // IDE + device pci 12.3 on end // Audio + device pci 12.4 on end // VGA onboard
end
- device pci 0e.0 on end # ETH0 - device pci 13.0 on end # USB + device pci 0e.0 on end // ETH0 + device pci 13.0 on end // USB
end end diff --git a/src/mainboard/iei/kino-780am2-fam10/devicetree.cb b/src/mainboard/iei/kino-780am2-fam10/devicetree.cb index 3f0b361..b9aaf01 100644 --- a/src/mainboard/iei/kino-780am2-fam10/devicetree.cb +++ b/src/mainboard/iei/kino-780am2-fam10/devicetree.cb @@ -1,27 +1,27 @@ -# Config for iei/kino-780am2-fam10 +// Config for iei/kino-780am2-fam10 chip northbridge/amd/amdfam10/root_complex device lapic_cluster 0 on - chip cpu/amd/socket_AM2r2 #L1 and DDR2 + chip cpu/amd/socket_AM2r2 //L1 and DDR2 device lapic 0 on end end end device pci_domain 0 on chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge + device pci 18.0 on // northbridge chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default + device pci 0.0 on end // HT 0x9600 + device pci 1.0 on end // Internal Graphics P2P bridge 0x9602 + device pci 2.0 on end // PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 on end // PCIE P2P bridge 0x960b + device pci 4.0 on end // PCIE P2P bridge 0x9604 + device pci 5.0 off end // PCIE P2P bridge 0x9605 + device pci 6.0 off end // PCIE P2P bridge 0x9606 + device pci 7.0 off end // PCIE P2P bridge 0x9607 + device pci 8.0 off end // NB/SB Link P2P bridge + device pci 9.0 on end // + device pci a.0 on end // + register "gppsb_configuration" = "1" // Configuration B + register "gpp_configuration" = "3" // Configuration D default register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "1" @@ -31,41 +31,41 @@ chip northbridge/amd/amdfam10/root_complex register "gfx_reconfiguration" = "1" register "gfx_link_width" = "0" end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 + chip southbridge/amd/sb700 // it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end // SATA + device pci 12.0 on end // USB + device pci 12.1 on end // USB + device pci 12.2 on end // USB + device pci 13.0 on end // USB + device pci 13.1 on end // USB + device pci 13.2 on end // USB + device pci 14.0 on // SM + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 + chip drivers/generic/generic //dimm 0-0-1 device i2c 51 on end end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d + end // SM + device pci 14.1 on end // IDE 0x439c + device pci 14.2 on end // HDA 0x4383 + device pci 14.3 on // LPC 0x439d chip superio/fintek/f71859 - device pnp 2e.3 on # Com1 + device pnp 2e.3 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - end #SIO - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 + end //SIO + end //LPC + device pci 14.4 on end // PCI 0x4384 + device pci 14.5 on end // USB 2 + register "boot_switch_sata_ide" = "0" // 0: boot from SATA. 1: IDE + end //southbridge/amd/sb700 + end // device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end - end #pci_domain -end #root_complex + end //pci_domain +end //root_complex
diff --git a/src/mainboard/iei/nova4899r/devicetree.cb b/src/mainboard/iei/nova4899r/devicetree.cb index f26db42..754aef7 100644 --- a/src/mainboard/iei/nova4899r/devicetree.cb +++ b/src/mainboard/iei/nova4899r/devicetree.cb @@ -2,60 +2,60 @@ chip northbridge/amd/gx1 device pci_domain 0 on device pci 0.0 on end chip southbridge/amd/cs5530 - device pci 0a.0 on end # ETH0 - device pci 0b.0 off end # ETH1 - device pci 0c.0 on end # ETH2 - device pci 0f.0 on end # PCI slot + device pci 0a.0 on end // ETH0 + device pci 0b.0 off end // ETH1 + device pci 0c.0 on end // ETH2 + device pci 0f.0 on end // PCI slot device pci 12.0 on chip superio/winbond/w83977tf - device pnp 2e.0 on # FDC + device pnp 2e.0 on // FDC irq 0x70 = 6 end - device pnp 2e.1 on # Parallel Port + device pnp 2e.1 on // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # COM1 + device pnp 2e.2 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end register "com1" = "{115200}" - device pnp 2e.3 on # COM2 + device pnp 2e.3 on // COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end register "com2" = "{115200}" - device pnp 2e.4 off # Reserved + device pnp 2e.4 off // Reserved end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 0x01 # Int 1 for PS/2 keyboard - irq 0x72 = 0x0c # Int 12 for PS/2 mouse + irq 0x70 = 0x01 // Int 1 for PS/2 keyboard + irq 0x72 = 0x0c // Int 12 for PS/2 mouse end - device pnp 2e.6 on # IR + device pnp 2e.6 on // IR io 0x60 = 0x2e8 irq 0x70 = 3 end - device pnp 2e.7 on # GAME/MIDI/GPIO1 + device pnp 2e.7 on // GAME/MIDI/GPIO1 io 0x60 = 0x290 end - device pnp 2e.8 on # GPIO2 + device pnp 2e.8 on // GPIO2 io 0x60 = 0x110 end - device pnp 2e.9 on # GPIO3 + device pnp 2e.9 on // GPIO3 io 0x60 = 0x120 end - device pnp 2e.A on # Power Management + device pnp 2e.A on // Power Management io 0x60 = 0xe800 end end - device pci 12.1 on end # SMI - device pci 12.2 on end # IDE - device pci 12.3 on end # Audio - device pci 12.4 on end # VGA onboard + device pci 12.1 on end // SMI + device pci 12.2 on end // IDE + device pci 12.3 on end // Audio + device pci 12.4 on end // VGA onboard end - device pci 13.0 on end # USB + device pci 13.0 on end // USB end end
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb b/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb index a7e74d0..b6d1ea7 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb +++ b/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb @@ -1,72 +1,72 @@ chip northbridge/amd/lx device pci_domain 0 on - device pci 1.0 on end # Northbridge - device pci 1.1 on end # Graphics + device pci 1.0 on end // Northbridge + device pci 1.1 on end // Graphics chip southbridge/amd/cs5536 - # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK - # SIRQ Mode = Active(Quiet) mode. Save power.... - # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK + // IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + // SIRQ Mode = Active(Quiet) mode. Save power.... + // Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK register "lpc_serirq_enable" = "0x0000105a" register "lpc_serirq_polarity" = "0x0000EFA5" register "lpc_serirq_mode" = "1" register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "1" # 0: host, 1:device - register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "enable_ide_nand_flash" = "0" // 0:ide mode, 1:flash + register "enable_USBP4_device" = "1" // 0: host, 1:device + register "enable_USBP4_overcurrent" = "0" //0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) register "com1_enable" = "0" register "com1_address" = "0x3F8" register "com1_irq" = "4" register "com2_enable" = "0" register "com2_address" = "0x2F8" register "com2_irq" = "3" - register "unwanted_vpci[0]" = "0" # End of list has a zero - device pci 9.0 on end # Slot1 - device pci a.0 on end # Slot2 - device pci b.0 on end # Slot3 - device pci c.0 on end # Slot4 - device pci e.0 on end # Ethernet 0 - device pci 10.0 on end # Ethernet 1 - device pci 11.0 on end # SATA - device pci f.0 on # ISA Bridge + register "unwanted_vpci[0]" = "0" // End of list has a zero + device pci 9.0 on end // Slot1 + device pci a.0 on end // Slot2 + device pci b.0 on end // Slot3 + device pci c.0 on end // Slot4 + device pci e.0 on end // Ethernet 0 + device pci 10.0 on end // Ethernet 1 + device pci 11.0 on end // SATA + device pci f.0 on // ISA Bridge chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel port + device pnp 2e.1 off // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # Com2 + device pnp 2e.3 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GAME_MIDI_GIPO1 - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b off end # HW Monitor + device pnp 2e.6 off end // CIR + device pnp 2e.7 off end // GAME_MIDI_GIPO1 + device pnp 2e.8 off end // GPIO2 + device pnp 2e.9 off end // GPIO3 + device pnp 2e.a off end // ACPI + device pnp 2e.b off end // HW Monitor end end - device pci f.2 on end # IDE Controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI + device pci f.2 on end // IDE Controller + device pci f.3 on end // Audio + device pci f.4 on end // OHCI + device pci f.5 on end // EHCI end end - # APIC cluster is late CPU init. + // APIC cluster is late CPU init. device lapic_cluster 0 on chip cpu/amd/model_lx device lapic 0 on end diff --git a/src/mainboard/intel/d810e2cb/devicetree.cb b/src/mainboard/intel/d810e2cb/devicetree.cb index 4129336..240196e 100644 --- a/src/mainboard/intel/d810e2cb/devicetree.cb +++ b/src/mainboard/intel/d810e2cb/devicetree.cb @@ -1,33 +1,33 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Joseph Smith joe@settoplinux.org -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +// +// This file is part of the coreboot project. +// +// Copyright (C) 2010 Joseph Smith joe@settoplinux.org +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +//
-chip northbridge/intel/i82810 # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/socket_FC_PGA370 # CPU - device lapic 0 on end # APIC +chip northbridge/intel/i82810 // Northbridge + device lapic_cluster 0 on // APIC cluster + chip cpu/intel/socket_FC_PGA370 // CPU + device lapic 0 on end // APIC end end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) - device pci 1.0 on end # Chipset Graphics Controller (CGC) - chip southbridge/intel/i82801bx # Southbridge + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Graphics Memory Controller Hub (GMCH) + device pci 1.0 on end // Chipset Graphics Controller (CGC) + chip southbridge/intel/i82801bx // Southbridge register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x06" register "pirqc_routing" = "0x07" @@ -40,43 +40,43 @@ chip northbridge/intel/i82810 # Northbridge register "ide0_enable" = "1" register "ide1_enable" = "1"
- device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA bridge - chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47M102) - device pnp 4e.0 on # Floppy + device pci 1e.0 on end // PCI bridge + device pci 1f.0 on // ISA bridge + chip superio/smsc/smscsuperio // Super I/O (SMSC LPC47M102) + device pnp 4e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 4e.3 on # Parallel port + device pnp 4e.3 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 4 end - device pnp 4e.4 on # COM1 + device pnp 4e.4 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 4e.5 off end # COM2 - device pnp 4e.7 on # PS/2 keyboard / mouse + device pnp 4e.5 off end // COM2 + device pnp 4e.7 on // PS/2 keyboard / mouse io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt + irq 0x70 = 1 // PS/2 keyboard interrupt + irq 0x72 = 12 // PS/2 mouse interrupt end - device pnp 4e.9 off end # Game port - device pnp 4e.a on # Runtime registers + device pnp 4e.9 off end // Game port + device pnp 4e.a on // Runtime registers io 0x60 = 0x800 end - device pnp 4e.b off end # MPU-401 + device pnp 4e.b off end // MPU-401 end end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMbus - device pci 1f.4 on end # USB - device pci 1f.5 on end # Audio controller - device pci 1f.6 off end # Modem controller + device pci 1f.1 on end // IDE + device pci 1f.2 on end // USB + device pci 1f.3 on end // SMbus + device pci 1f.4 on end // USB + device pci 1f.5 on end // Audio controller + device pci 1f.6 off end // Modem controller end end end diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index a58d99e..ed91ab8 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -1,21 +1,21 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or -## modify it under the terms of the GNU General Public License as -## published by the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +// +// This file is part of the coreboot project. +// +// Copyright (C) 2007-2008 coresystems GmbH +// +// This program is free software; you can redistribute it and/or +// modify it under the terms of the GNU General Public License as +// published by the Free Software Foundation; version 2 of the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +//
chip northbridge/intel/i945
@@ -27,10 +27,10 @@ chip northbridge/intel/i945
device pci_domain 0 on subsystemid 0x8086 0x464c inherit - device pci 00.0 on end # host bridge - device pci 01.0 off end # i945 PCIe root port - device pci 02.0 on end # vga controller - device pci 02.1 on end # display controller + device pci 00.0 on end // host bridge + device pci 01.0 off end // i945 PCIe root port + device pci 02.0 on end // vga controller + device pci 02.1 on end // display controller
chip southbridge/intel/i82801gx register "pirqa_routing" = "0x05" @@ -42,10 +42,10 @@ chip northbridge/intel/i945 register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x06"
- # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) + // GPI routing + // 0 No effect (default) + // 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + // 2 SCI (if corresponding GPIO_EN bit is also set) register "gpi13_routing" = "1" register "gpe0_en" = "0x20000601"
@@ -54,26 +54,26 @@ chip northbridge/intel/i945 register "ide_enable_secondary" = "0x0" register "sata_ahci" = "0x0"
- device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe - device pci 1c.1 on end # PCIe - device pci 1c.2 on end # PCIe - #device pci 1c.3 off end # PCIe port 4 - #device pci 1c.4 off end # PCIe port 5 - #device pci 1c.5 off end # PCIe port 6 - device pci 1d.0 on end # USB UHCI - device pci 1d.1 on end # USB UHCI - device pci 1d.2 on end # USB UHCI - device pci 1d.3 on end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on end # PCI bridge - #device pci 1e.2 off end # AC'97 Audio - #device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge + device pci 1b.0 on end // High Definition Audio + device pci 1c.0 on end // PCIe + device pci 1c.1 on end // PCIe + device pci 1c.2 on end // PCIe + //device pci 1c.3 off end # PCIe port 4 + //device pci 1c.4 off end # PCIe port 5 + //device pci 1c.5 off end # PCIe port 6 + device pci 1d.0 on end // USB UHCI + device pci 1d.1 on end // USB UHCI + device pci 1d.2 on end // USB UHCI + device pci 1d.3 on end // USB UHCI + device pci 1d.7 on end // USB2 EHCI + device pci 1e.0 on end // PCI bridge + //device pci 1e.2 off end # AC'97 Audio + //device pci 1e.3 off end # AC'97 Modem + device pci 1f.0 on // LPC bridge chip superio/smsc/lpc47m15x - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy end - device pnp 2e.3 off # Parport + device pnp 2e.3 off // Parport end device pnp 2e.4 on io 0x60 = 0x3f8 @@ -82,28 +82,28 @@ chip northbridge/intel/i945 device pnp 2e.5 on io 0x60 = 0x2f8 irq 0x70 = 3 - irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq + irq 0xf1 = 4 // set IRMODE 0 # XXX not an irq end - device pnp 2e.7 on # Keyboard+Mouse + device pnp 2e.7 on // Keyboard+Mouse io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 - irq 0xf0 = 0x82 # HW accel A20. + irq 0xf0 = 0x82 // HW accel A20. end - device pnp 2e.8 on # GAME - # all default + device pnp 2e.8 on // GAME + // all default end - device pnp 2e.a on # PME + device pnp 2e.a on // PME end - device pnp 2e.b on # MPU + device pnp 2e.b on // MPU end end end - #device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - #device pci 1f.4 off end # Realtek ID Codec + //device pci 1f.1 off end # IDE + device pci 1f.2 on end // SATA + device pci 1f.3 on end // SMBus + //device pci 1f.4 off end # Realtek ID Codec end end end diff --git a/src/mainboard/intel/eagleheights/devicetree.cb b/src/mainboard/intel/eagleheights/devicetree.cb index e628dda..d434a1d 100644 --- a/src/mainboard/intel/eagleheights/devicetree.cb +++ b/src/mainboard/intel/eagleheights/devicetree.cb @@ -1,67 +1,67 @@ chip northbridge/intel/i3100 device pci_domain 0 on - device pci 00.0 on end # IMCH - device pci 00.1 on end # IMCH error status - device pci 01.0 on end # IMCH EDMA engine - device pci 02.0 on end # PCIe port A/A0 - device pci 03.0 on end # PCIe port A1 + device pci 00.0 on end // IMCH + device pci 00.1 on end // IMCH error status + device pci 01.0 on end // IMCH EDMA engine + device pci 02.0 on end // PCIe port A/A0 + device pci 03.0 on end // PCIe port A1 chip southbridge/intel/i3100 - # PIRQ line -> legacy IRQ mappings + // PIRQ line -> legacy IRQ mappings register "pirq_a_d" = "0x8b808a8a" register "pirq_e_h" = "0x85808080"
- device pci 1c.0 on end # PCIe port B0 - device pci 1c.1 off end # PCIe port B1 - device pci 1c.2 off end # PCIe port B2 - device pci 1c.3 off end # PCIe port B3 - device pci 1d.0 on end # USB (UHCI) 1 - device pci 1d.1 on end # USB (UHCI) 2 - device pci 1d.7 on end # USB (EHCI) - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # LPC bridge + device pci 1c.0 on end // PCIe port B0 + device pci 1c.1 off end // PCIe port B1 + device pci 1c.2 off end // PCIe port B2 + device pci 1c.3 off end // PCIe port B3 + device pci 1d.0 on end // USB (UHCI) 1 + device pci 1d.1 on end // USB (UHCI) 2 + device pci 1d.7 on end // USB (EHCI) + device pci 1e.0 on end // PCI bridge + device pci 1f.0 on // LPC bridge chip superio/intel/i3100 - device pnp 4e.4 on # Com1 + device pnp 4e.4 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 4e.5 on # Com2 + device pnp 4e.5 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end end chip superio/smsc/smscsuperio - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.2 off # Serial Port 4 + device pnp 2e.2 off // Serial Port 4 io 0x60 = 0x2e8 irq 0x70 = 3 end - device pnp 2e.3 on # Parallel Port + device pnp 2e.3 on // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 2 end - device pnp 2e.4 off # Serial Port 3 + device pnp 2e.4 off // Serial Port 3 io 0x60 = 0x3e8 irq 0x70 = 4 end - device pnp 2e.7 on # PS/2 Keyboard / Mouse + device pnp 2e.7 on // PS/2 Keyboard / Mouse io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt + irq 0x70 = 1 // PS/2 keyboard interrupt + irq 0x72 = 12 // PS/2 mouse interrupt end - device pnp 2e.a off # Runtime registers + device pnp 2e.a off // Runtime registers io 0x60 = 0x600 end end end - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - device pci 1f.4 on end # Performance counters + device pci 1f.2 on end // SATA + device pci 1f.3 on end // SMBus + device pci 1f.4 on end // Performance counters end end device lapic_cluster 0 on diff --git a/src/mainboard/intel/jarrell/devicetree.cb b/src/mainboard/intel/jarrell/devicetree.cb index fb32a08..a89aebc 100644 --- a/src/mainboard/intel/jarrell/devicetree.cb +++ b/src/mainboard/intel/jarrell/devicetree.cb @@ -5,7 +5,7 @@ chip northbridge/intel/e7520 device pci 00.1 on end device pci 01.0 on end device pci 02.0 on - chip southbridge/intel/pxhd # pxhd1 + chip southbridge/intel/pxhd // pxhd1 device pci 00.0 on end device pci 00.1 on end device pci 00.2 on @@ -18,7 +18,7 @@ chip northbridge/intel/e7520 end end device pci 06.0 on end - chip southbridge/intel/i82801ex # i82801er + chip southbridge/intel/i82801ex // i82801er device pci 1d.0 on end device pci 1d.1 on end device pci 1d.2 on end @@ -33,14 +33,14 @@ chip northbridge/intel/e7520 chip superio/nsc/pc87427 device pnp 2e.0 off end device pnp 2e.2 on -# io 0x60 = 0x2f8 -# irq 0x70 = 3 +// io 0x60 = 0x2f8 +// irq 0x70 = 3 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.3 on -# io 0x60 = 0x3f8 -# irq 0x70 = 4 +// io 0x60 = 0x3f8 +// irq 0x70 = 4 io 0x60 = 0x2f8 irq 0x70 = 3 end @@ -70,10 +70,10 @@ chip northbridge/intel/e7520 end end device lapic_cluster 0 on - chip cpu/intel/socket_mPGA604 # cpu 0 + chip cpu/intel/socket_mPGA604 // cpu 0 device lapic 0 on end end - chip cpu/intel/socket_mPGA604 # cpu 1 + chip cpu/intel/socket_mPGA604 // cpu 1 device lapic 6 on end end end diff --git a/src/mainboard/intel/mtarvon/devicetree.cb b/src/mainboard/intel/mtarvon/devicetree.cb index cd7df2d..d0ebea8 100644 --- a/src/mainboard/intel/mtarvon/devicetree.cb +++ b/src/mainboard/intel/mtarvon/devicetree.cb @@ -1,40 +1,40 @@ chip northbridge/intel/i3100 device pci_domain 0 on subsystemid 0x8086 0x2680 inherit - device pci 00.0 on end # IMCH - device pci 00.1 on end # IMCH error status - device pci 01.0 on end # IMCH EDMA engine - device pci 02.0 on end # PCIe port A/A0 - device pci 03.0 on end # PCIe port A1 + device pci 00.0 on end // IMCH + device pci 00.1 on end // IMCH error status + device pci 01.0 on end // IMCH EDMA engine + device pci 02.0 on end // PCIe port A/A0 + device pci 03.0 on end // PCIe port A1 chip southbridge/intel/i3100 - # PIRQ line -> legacy IRQ mappings + // PIRQ line -> legacy IRQ mappings register "pirq_a_d" = "0x0b070a05" register "pirq_e_h" = "0x0a808080"
- device pci 1c.0 on end # PCIe port B0 - device pci 1c.1 on end # PCIe port B1 - device pci 1c.2 on end # PCIe port B2 - device pci 1c.3 on end # PCIe port B3 - device pci 1d.0 on end # USB (UHCI) 1 - device pci 1d.1 on end # USB (UHCI) 2 - device pci 1d.7 on end # USB (EHCI) - device pci 1e.0 on end # PCI bridge - device pci 1e.2 on end # audio - device pci 1e.3 on end # modem - device pci 1f.0 on # LPC bridge + device pci 1c.0 on end // PCIe port B0 + device pci 1c.1 on end // PCIe port B1 + device pci 1c.2 on end // PCIe port B2 + device pci 1c.3 on end // PCIe port B3 + device pci 1d.0 on end // USB (UHCI) 1 + device pci 1d.1 on end // USB (UHCI) 2 + device pci 1d.7 on end // USB (EHCI) + device pci 1e.0 on end // PCI bridge + device pci 1e.2 on end // audio + device pci 1e.3 on end // modem + device pci 1f.0 on // LPC bridge chip superio/intel/i3100 - device pnp 4e.4 on # Com1 + device pnp 4e.4 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 4e.5 on # Com2 + device pnp 4e.5 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end end end - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus + device pci 1f.2 on end // SATA + device pci 1f.3 on end // SMBus end end device lapic_cluster 0 on diff --git a/src/mainboard/intel/truxton/devicetree.cb b/src/mainboard/intel/truxton/devicetree.cb index 486601a..48cf811 100644 --- a/src/mainboard/intel/truxton/devicetree.cb +++ b/src/mainboard/intel/truxton/devicetree.cb @@ -1,29 +1,29 @@ chip northbridge/intel/i3100 device pci_domain 0 on subsystemid 0x8086 0x2680 inherit - device pci 00.0 on end # IMCH - device pci 00.1 on end # IMCH error status - device pci 01.0 on end # IMCH EDMA engine - device pci 02.0 on end # PCIe port A/A0 - device pci 03.0 on end # PCIe port A1 - device pci 04.0 on end # ? - device pci 08.0 off end # must be off to boot - device pci 0d.0 off end # must be off to boot - device pci 0d.1 off end # must be off to boot + device pci 00.0 on end // IMCH + device pci 00.1 on end // IMCH error status + device pci 01.0 on end // IMCH EDMA engine + device pci 02.0 on end // PCIe port A/A0 + device pci 03.0 on end // PCIe port A1 + device pci 04.0 on end // ? + device pci 08.0 off end // must be off to boot + device pci 0d.0 off end // must be off to boot + device pci 0d.1 off end // must be off to boot chip southbridge/intel/i3100 - # PIRQ line -> legacy IRQ mappings + // PIRQ line -> legacy IRQ mappings register "pirq_a_d" = "0x0b070a05" register "pirq_e_h" = "0x0a808080"
- device pci 1d.0 on end # USB (UHCI) - device pci 1d.7 on end # USB (EHCI) - device pci 1f.0 on # LPC bridge + device pci 1d.0 on end // USB (UHCI) + device pci 1d.7 on end // USB (EHCI) + device pci 1f.0 on // LPC bridge chip superio/intel/i3100 - device pnp 4e.4 on # Com1 + device pnp 4e.4 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 4e.5 on # Com2 + device pnp 4e.5 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end @@ -33,18 +33,18 @@ chip northbridge/intel/i3100 device pnp 2e.3 off end device pnp 2e.4 off end device pnp 2e.5 off end - device pnp 2e.7 on # PS/2 keyboard / mouse + device pnp 2e.7 on // PS/2 keyboard / mouse io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt + irq 0x70 = 1 // PS/2 keyboard interrupt + irq 0x72 = 12 // PS/2 mouse interrupt end device pnp 2e.a off end end end - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - device pci 1f.4 on end # ? + device pci 1f.2 on end // SATA + device pci 1f.3 on end // SMBus + device pci 1f.4 on end // ? end end device lapic_cluster 0 on diff --git a/src/mainboard/intel/xe7501devkit/devicetree.cb b/src/mainboard/intel/xe7501devkit/devicetree.cb index 18ee64e..b1911a7 100644 --- a/src/mainboard/intel/xe7501devkit/devicetree.cb +++ b/src/mainboard/intel/xe7501devkit/devicetree.cb @@ -1,67 +1,67 @@ chip northbridge/intel/e7501 device pci_domain 0 on subsystemid 0x8086 0x2480 inherit - device pci 0.0 on end # Chipset host controller - device pci 0.1 on end # Host RASUM controller - device pci 2.0 on # Hub interface B - chip southbridge/intel/i82870 # P64H2 - device pci 1c.0 on end # IOAPIC - bus B - device pci 1d.0 on end # Hub to PCI-B bridge - device pci 1e.0 on end # IOAPIC - bus A - device pci 1f.0 on end # Hub to PCI-A bridge + device pci 0.0 on end // Chipset host controller + device pci 0.1 on end // Host RASUM controller + device pci 2.0 on // Hub interface B + chip southbridge/intel/i82870 // P64H2 + device pci 1c.0 on end // IOAPIC - bus B + device pci 1d.0 on end // Hub to PCI-B bridge + device pci 1e.0 on end // IOAPIC - bus A + device pci 1f.0 on end // Hub to PCI-A bridge end end - device pci 3.0 off end # Hub interface C (82808AA connector - disable for now) - device pci 4.0 on # Hub interface D - chip southbridge/intel/i82870 # P64H2 - device pci 1c.0 on end # IOAPIC - bus B - device pci 1d.0 on end # Hub to PCI-B bridge - device pci 1e.0 on end # IOAPIC - bus A - device pci 1f.0 on end # Hub to PCI-A bridge + device pci 3.0 off end // Hub interface C (82808AA connector - disable for now) + device pci 4.0 on // Hub interface D + chip southbridge/intel/i82870 // P64H2 + device pci 1c.0 on end // IOAPIC - bus B + device pci 1d.0 on end // Hub to PCI-B bridge + device pci 1e.0 on end // IOAPIC - bus A + device pci 1f.0 on end // Hub to PCI-A bridge end end - device pci 6.0 on end # E7501 Power management registers? (undocumented) + device pci 6.0 on end // E7501 Power management registers? (undocumented) chip southbridge/intel/i82801cx - device pci 1d.0 off end # USB (might not work, Southbridge code needs looking at) - device pci 1d.1 off end # USB (not populated) - device pci 1d.2 off end # USB (not populated) - device pci 1e.0 on # Hub to PCI bridge + device pci 1d.0 off end // USB (might not work, Southbridge code needs looking at) + device pci 1d.1 off end // USB (not populated) + device pci 1d.2 off end // USB (not populated) + device pci 1e.0 on // Hub to PCI bridge device pci 0.0 on end end - device pci 1f.0 on # LPC bridge + device pci 1f.0 on // LPC bridge chip superio/smsc/lpc47b272 - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.3 off # Parallel Port + device pnp 2e.3 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.4 on # Com1 + device pnp 2e.4 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.5 off # Com2 + device pnp 2e.5 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.7 on # Keyboard + device pnp 2e.7 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # Keyboard interrupt - irq 0x72 = 12 # Mouse interrupt + irq 0x70 = 1 // Keyboard interrupt + irq 0x72 = 12 // Mouse interrupt end - device pnp 2e.a off end # ACPI + device pnp 2e.a off end // ACPI end end - device pci 1f.1 on end # IDE - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # AC97 Audio - device pci 1f.6 off end # AC97 Modem - end # SB - end # PCI_DOMAIN + device pci 1f.1 on end // IDE + device pci 1f.3 on end // SMBus + device pci 1f.5 off end // AC97 Audio + device pci 1f.6 off end // AC97 Modem + end // SB + end // PCI_DOMAIN device lapic_cluster 0 on chip cpu/intel/socket_mPGA604 device lapic 0 on end diff --git a/src/mainboard/iwave/iWRainbowG6/devicetree.cb b/src/mainboard/iwave/iWRainbowG6/devicetree.cb index efae82b..3df2c58 100644 --- a/src/mainboard/iwave/iWRainbowG6/devicetree.cb +++ b/src/mainboard/iwave/iWRainbowG6/devicetree.cb @@ -7,8 +7,8 @@ chip northbridge/intel/sch end
device pci_domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # Integrated Graphics and Video Device + device pci 00.0 on end // host bridge + device pci 02.0 on end // Integrated Graphics and Video Device
chip southbridge/intel/sch register "pirqa_routing" = "0xa" @@ -20,19 +20,19 @@ chip northbridge/intel/sch register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x80"
- device pci 1a.0 on end # 26 0 USB Client - device pci 1b.0 on end # 27 0 HD Audio Controller - device pci 1c.0 on end # 28 0 PCI Express Port 1 - device pci 1c.1 on end # 28 1 PCI Express Port 2 - device pci 1d.0 on end # USB Classic UHCI Controller 1 - device pci 1d.1 on end # USB Classic UHCI Controller 2 - device pci 1d.2 on end # USB Classic UHCI Controller 3 - device pci 1d.7 on end # USB2 EHCI Controller - device pci 1e.0 on end # SDIO/MMC Port 0 - device pci 1e.1 on end # SDIO/MMC Port 1 - device pci 1e.2 on end # SDIO/MMC Port 2 - device pci 1f.0 on end # LPC bridge - device pci 1f.1 on end # PATA Controller + device pci 1a.0 on end // 26 0 USB Client + device pci 1b.0 on end // 27 0 HD Audio Controller + device pci 1c.0 on end // 28 0 PCI Express Port 1 + device pci 1c.1 on end // 28 1 PCI Express Port 2 + device pci 1d.0 on end // USB Classic UHCI Controller 1 + device pci 1d.1 on end // USB Classic UHCI Controller 2 + device pci 1d.2 on end // USB Classic UHCI Controller 3 + device pci 1d.7 on end // USB2 EHCI Controller + device pci 1e.0 on end // SDIO/MMC Port 0 + device pci 1e.1 on end // SDIO/MMC Port 1 + device pci 1e.2 on end // SDIO/MMC Port 2 + device pci 1f.0 on end // LPC bridge + device pci 1f.1 on end // PATA Controller end end end diff --git a/src/mainboard/iwill/dk8_htx/devicetree.cb b/src/mainboard/iwill/dk8_htx/devicetree.cb index d0cff02..04a3ad0 100644 --- a/src/mainboard/iwill/dk8_htx/devicetree.cb +++ b/src/mainboard/iwill/dk8_htx/devicetree.cb @@ -9,17 +9,17 @@ chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8 device pci 18.0 on end device pci 18.0 on end - device pci 18.0 on # northbridge + device pci 18.0 on // northbridge chip southbridge/amd/amd8131 - # the on/off keyword is mandatory + // the on/off keyword is mandatory device pci 0.0 on end device pci 0.1 on end device pci 1.0 on end device pci 1.1 on end end chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge + // this "device pci 0.0" is the parent the next one + // PCI bridge device pci 0.0 on device pci 0.0 on end device pci 0.1 on end @@ -28,46 +28,46 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.0 on chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.3 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # CIR + device pnp 2e.6 off // CIR io 0x60 = 0x100 end - device pnp 2e.7 off # GAME_MIDI_GIPO1 + device pnp 2e.7 off // GAME_MIDI_GIPO1 io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 on # GPIO2 + device pnp 2e.8 on // GPIO2 io 0x07 = 0x08ff io 0x30 = 0x01ff io 0x2b = 0xd0ff io 0xf0 = 0xef16 end - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.9 off end // GPIO3 + device pnp 2e.a off end // ACPI + device pnp 2e.b on // HW Monitor io 0x60 = 0x290 irq 0x70 = 5 end @@ -76,54 +76,54 @@ chip northbridge/amd/amdk8/root_complex device pci 1.1 on end device pci 1.2 on end device pci 1.3 on - chip drivers/generic/generic #dimm 0-0-0 + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 + chip drivers/generic/generic //dimm 0-0-1 device i2c 51 on end end - chip drivers/generic/generic #dimm 0-1-0 + chip drivers/generic/generic //dimm 0-1-0 device i2c 52 on end end - chip drivers/generic/generic #dimm 0-1-1 + chip drivers/generic/generic //dimm 0-1-1 device i2c 53 on end end - chip drivers/generic/generic #dimm 1-0-0 + chip drivers/generic/generic //dimm 1-0-0 device i2c 54 on end end - chip drivers/generic/generic #dimm 1-0-1 + chip drivers/generic/generic //dimm 1-0-1 device i2c 55 on end end - chip drivers/generic/generic #dimm 1-1-0 + chip drivers/generic/generic //dimm 1-1-0 device i2c 56 on end end - chip drivers/generic/generic #dimm 1-1-1 + chip drivers/generic/generic //dimm 1-1-1 device i2c 57 on end end - end # acpi + end // acpi device pci 1.5 off end device pci 1.6 off end register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 + end // device pci 18.0
device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end
- end #pci_domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# end + end //pci_domain +// chip drivers/generic/debug +// device pnp 0.0 off end # chip name +// device pnp 0.1 on end # pci_regs_all +// device pnp 0.2 off end # mem +// device pnp 0.3 off end # cpuid +// device pnp 0.4 off end # smbus_regs_all +// device pnp 0.5 off end # dual core msr +// device pnp 0.6 off end # cache size +// device pnp 0.7 off end # tsc +// end
end
diff --git a/src/mainboard/iwill/dk8s2/devicetree.cb b/src/mainboard/iwill/dk8s2/devicetree.cb index 35b2307..ca2f8ff 100644 --- a/src/mainboard/iwill/dk8s2/devicetree.cb +++ b/src/mainboard/iwill/dk8s2/devicetree.cb @@ -7,7 +7,7 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on subsystemid 0x161f 0x3016 inherit chip northbridge/amd/amdk8 - device pci 18.0 on # LDT 0 + device pci 18.0 on // LDT 0 chip southbridge/amd/amd8131 device pci 0.0 on end device pci 0.1 on end @@ -15,8 +15,8 @@ chip northbridge/amd/amdk8/root_complex device pci 1.1 on end end chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge + // this "device pci 0.0" is the parent the next one + // PCI bridge device pci 0.0 on device pci 0.0 on end device pci 0.1 on end @@ -25,40 +25,40 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.0 on chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.3 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GAME_MIDI_GIPO1 - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.6 off end // CIR + device pnp 2e.7 off end // GAME_MIDI_GIPO1 + device pnp 2e.8 off end // GPIO2 + device pnp 2e.9 off end // GPIO3 + device pnp 2e.a off end // ACPI + device pnp 2e.b on // HW Monitor io 0x60 = 0x290 end register "com1" = "{1}" - # register "com1" = "{1, 0, 0x3f8, 4}" - # register "lpt" = "{1}" + // register "com1" = "{1, 0, 0x3f8, 4}" + // register "lpt" = "{1}" end end device pci 1.1 on end @@ -67,9 +67,9 @@ chip northbridge/amd/amdk8/root_complex device pci 1.5 off end device pci 1.6 off end end - end # LDT0 - device pci 18.0 on end # LDT1 - device pci 18.0 on end # LDT2 + end // LDT0 + device pci 18.0 on end // LDT1 + device pci 18.0 on end // LDT2 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end diff --git a/src/mainboard/iwill/dk8x/devicetree.cb b/src/mainboard/iwill/dk8x/devicetree.cb index 3888805..2939ead 100644 --- a/src/mainboard/iwill/dk8x/devicetree.cb +++ b/src/mainboard/iwill/dk8x/devicetree.cb @@ -6,18 +6,18 @@ chip northbridge/amd/amdk8/root_complex end device pci_domain 0 on chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 + device pci 18.0 on // northbridge + // devices on link 0, link 0 == LDT 0 chip southbridge/amd/amd8131 - # the on/off keyword is mandatory + // the on/off keyword is mandatory device pci 0.0 on end device pci 0.1 on end device pci 1.0 on end device pci 1.1 on end end chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge + // this "device pci 0.0" is the parent the next one + // PCI bridge device pci 0.0 on device pci 0.0 on end device pci 0.1 on end @@ -25,7 +25,7 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 off end end device pci 1.0 on - # TODO: This is incomplete. + // TODO: This is incomplete. chip superio/winbond/w83627thg device pnp 2e.0 on end device pnp 2e.1 on end @@ -45,9 +45,9 @@ chip northbridge/amd/amdk8/root_complex device pci 1.5 off end device pci 1.6 off end end - end # LDT0 - device pci 18.0 on end # LDT1 - device pci 18.0 on end # LDT2 + end // LDT0 + device pci 18.0 on end // LDT1 + device pci 18.0 on end // LDT2 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end diff --git a/src/mainboard/jetway/j7f24/devicetree.cb b/src/mainboard/jetway/j7f24/devicetree.cb index cbc45c3..c52e558 100644 --- a/src/mainboard/jetway/j7f24/devicetree.cb +++ b/src/mainboard/jetway/j7f24/devicetree.cb @@ -1,62 +1,62 @@ -chip northbridge/via/cn700 # Northbridge - device pci_domain 0 on # PCI domain - device pci 0.0 on end # AGP Bridge - device pci 0.1 on end # Error Reporting - device pci 0.2 on end # Host Bus Control - device pci 0.3 on end # Memory Controller - device pci 0.4 on end # Power Management - device pci 0.7 on end # V-Link Controller - device pci 1.0 on end # PCI Bridge - chip southbridge/via/vt8237r # Southbridge - # Enable both IDE channels. +chip northbridge/via/cn700 // Northbridge + device pci_domain 0 on // PCI domain + device pci 0.0 on end // AGP Bridge + device pci 0.1 on end // Error Reporting + device pci 0.2 on end // Host Bus Control + device pci 0.3 on end // Memory Controller + device pci 0.4 on end // Power Management + device pci 0.7 on end // V-Link Controller + device pci 1.0 on end // PCI Bridge + chip southbridge/via/vt8237r // Southbridge + // Enable both IDE channels. register "ide0_enable" = "1" register "ide1_enable" = "1" - # Both cables are 40pin. + // Both cables are 40pin. register "ide0_80pin_cable" = "0" register "ide1_80pin_cable" = "0" register "fn_ctrl_lo" = "0x80" register "fn_ctrl_hi" = "0x1d" - device pci a.0 on end # Firewire - device pci f.0 on end # SATA - device pci f.1 on end # IDE - device pci 10.0 on end # OHCI - device pci 10.1 on end # OHCI - device pci 10.2 on end # OHCI - device pci 10.3 on end # OHCI - device pci 10.4 on end # EHCI - device pci 11.0 on # Southbridge LPC - chip superio/fintek/f71805f # Super I/O - device pnp 2e.0 off # Floppy + device pci a.0 on end // Firewire + device pci f.0 on end // SATA + device pci f.1 on end // IDE + device pci 10.0 on end // OHCI + device pci 10.1 on end // OHCI + device pci 10.2 on end // OHCI + device pci 10.3 on end // OHCI + device pci 10.4 on end // EHCI + device pci 11.0 on // Southbridge LPC + chip superio/fintek/f71805f // Super I/O + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Parallel Port + device pnp 2e.1 on // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 end - device pnp 2e.2 on # COM1 + device pnp 2e.2 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # COM2 + device pnp 2e.3 on // COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.b on # HWM + device pnp 2e.b on // HWM io 0x60 = 0xec00 end end end - device pci 11.5 on end # AC'97 audio - # device pci 11.6 off end # AC'97 Modem - device pci 12.0 on end # Ethernet + device pci 11.5 on end // AC'97 audio + // device pci 11.6 off end # AC'97 Modem + device pci 12.0 on end // Ethernet end end - device lapic_cluster 0 on # APIC cluster - chip cpu/via/model_c7 # VIA C7 - device lapic 0 on end # APIC + device lapic_cluster 0 on // APIC cluster + chip cpu/via/model_c7 // VIA C7 + device lapic 0 on end // APIC end end end diff --git a/src/mainboard/jetway/pa78vm5/devicetree.cb b/src/mainboard/jetway/pa78vm5/devicetree.cb index 6913d79..1538e83 100644 --- a/src/mainboard/jetway/pa78vm5/devicetree.cb +++ b/src/mainboard/jetway/pa78vm5/devicetree.cb @@ -1,28 +1,28 @@ -# sample config for jetway/PA78VM5 +// sample config for jetway/PA78VM5 chip northbridge/amd/amdfam10/root_complex device lapic_cluster 0 on - chip cpu/amd/socket_AM2r2 #L1 and DDR2 + chip cpu/amd/socket_AM2r2 //L1 and DDR2 device lapic 0 on end end end device pci_domain 0 on subsystemid 0x1022 0x3060 inherit chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge + device pci 18.0 on // northbridge chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default + device pci 0.0 on end // HT 0x9600 + device pci 1.0 on end // Internal Graphics P2P bridge 0x9602 + device pci 2.0 on end // PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 on end // PCIE P2P bridge 0x960b + device pci 4.0 on end // PCIE P2P bridge 0x9604 + device pci 5.0 off end // PCIE P2P bridge 0x9605 + device pci 6.0 off end // PCIE P2P bridge 0x9606 + device pci 7.0 off end // PCIE P2P bridge 0x9607 + device pci 8.0 off end // NB/SB Link P2P bridge + device pci 9.0 on end // + device pci a.0 on end // + register "gppsb_configuration" = "1" // Configuration B + register "gpp_configuration" = "3" // Configuration D default register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "1" @@ -32,69 +32,69 @@ chip northbridge/amd/amdfam10/root_complex register "gfx_reconfiguration" = "1" register "gfx_link_width" = "0" end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 + chip southbridge/amd/sb700 // it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end // SATA + device pci 12.0 on end // USB + device pci 12.1 on end // USB + device pci 12.2 on end // USB + device pci 13.0 on end // USB + device pci 13.1 on end // USB + device pci 13.2 on end // USB + device pci 14.0 on // SM + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 + chip drivers/generic/generic //dimm 0-0-1 device i2c 51 on end end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d + end // SM + device pci 14.1 on end // IDE 0x439c + device pci 14.2 on end // HDA 0x4383 + device pci 14.3 on // LPC 0x439d chip superio/fintek/f71863fg - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Com1 + device pnp 2e.1 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 off # Com2 + device pnp 2e.2 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 off # Parallel Port + device pnp 2e.3 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard + device pnp 2e.4 off end // EC + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.6 on # Mouse + device pnp 2e.6 on // Mouse irq 0x70 = 12 end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + device pnp 2e.7 off // GPIO, must be closed for unresolved reason. end - device pnp 2e.8 off # MIDI + device pnp 2e.8 off // MIDI io 0x60 = 0x300 irq 0x70 = 9 end - device pnp 2e.9 off # GAME + device pnp 2e.9 off // GAME io 0x60 = 0x220 end - device pnp 2e.a off end # CIR - end #superio/ite/it8718f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 + device pnp 2e.a off end // CIR + end //superio/ite/it8718f + end //LPC + device pci 14.4 on end // PCI 0x4384 + device pci 14.5 on end // USB 2 + register "boot_switch_sata_ide" = "0" // 0: boot from SATA. 1: IDE + end //southbridge/amd/sb700 + end // device pci 18.0
device pci 18.0 on end device pci 18.0 on end @@ -102,9 +102,9 @@ chip northbridge/amd/amdfam10/root_complex device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end -# device pci 00.5 on end +// device pci 00.5 on end end - end #pci_domain - #for node 32 to node 63 + end //pci_domain + //for node 32 to node 63
end diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index b848d40..5481bbb 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -7,10 +7,10 @@ chip northbridge/intel/i945 end
device pci_domain 0 on - device pci 00.0 on end # host bridge - device pci 01.0 off end # i945 PCIe root port - device pci 02.0 on end # vga controller - device pci 02.1 on end # display controller + device pci 00.0 on end // host bridge + device pci 01.0 off end // i945 PCIe root port + device pci 02.0 on end // vga controller + device pci 02.1 on end // display controller
chip southbridge/intel/i82801gx register "pirqa_routing" = "0x05" @@ -22,10 +22,10 @@ chip northbridge/intel/i945 register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x06"
- # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) + // GPI routing + // 0 No effect (default) + // 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + // 2 SCI (if corresponding GPIO_EN bit is also set) register "gpi13_routing" = "1"
register "ide_legacy_combined" = "0x1" @@ -33,26 +33,26 @@ chip northbridge/intel/i945 register "ide_enable_secondary" = "0x1" register "sata_ahci" = "0x0"
- device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe - device pci 1c.1 on end # PCIe - device pci 1c.2 on end # PCIe - #device pci 1c.3 off end # PCIe port 4 - #device pci 1c.4 off end # PCIe port 5 - #device pci 1c.5 off end # PCIe port 6 - device pci 1d.0 on end # USB UHCI - device pci 1d.1 on end # USB UHCI - device pci 1d.2 on end # USB UHCI - device pci 1d.3 on end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on end # PCI bridge - #device pci 1e.2 off end # AC'97 Audio - #device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge + device pci 1b.0 on end // High Definition Audio + device pci 1c.0 on end // PCIe + device pci 1c.1 on end // PCIe + device pci 1c.2 on end // PCIe + //device pci 1c.3 off end # PCIe port 4 + //device pci 1c.4 off end # PCIe port 5 + //device pci 1c.5 off end # PCIe port 6 + device pci 1d.0 on end // USB UHCI + device pci 1d.1 on end // USB UHCI + device pci 1d.2 on end // USB UHCI + device pci 1d.3 on end // USB UHCI + device pci 1d.7 on end // USB2 EHCI + device pci 1e.0 on end // PCI bridge + //device pci 1e.2 off end # AC'97 Audio + //device pci 1e.3 off end # AC'97 Modem + device pci 1f.0 on // LPC bridge chip superio/winbond/w83627thg - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy end - device pnp 2e.1 on # Parallel port + device pnp 2e.1 on // Parallel port io 0x60 = 0x378 irq 0x70 = 5 end @@ -63,68 +63,68 @@ chip northbridge/intel/i945 device pnp 2e.3 on io 0x60 = 0x2f8 irq 0x70 = 3 - irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq + irq 0xf1 = 4 // set IRMODE 0 # XXX not an irq end - device pnp 2e.5 on # Keyboard+Mouse + device pnp 2e.5 on // Keyboard+Mouse io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 - irq 0xf0 = 0x82 # HW accel A20. + irq 0xf0 = 0x82 // HW accel A20. end - device pnp 2e.7 on # GPIO1, GAME, MIDI + device pnp 2e.7 on // GPIO1, GAME, MIDI io 0x62 = 0x330 irq 0x70 = 9 end - device pnp 2e.8 on # GPIO2 - # all default + device pnp 2e.8 on // GPIO2 + // all default end - device pnp 2e.9 on # GPIO3/4 - irq 0x30 = 0x03 # does this work? - irq 0xf0 = 0xfb # set inputs/outputs + device pnp 2e.9 on // GPIO3/4 + irq 0x30 = 0x03 // does this work? + irq 0xf0 = 0xfb // set inputs/outputs irq 0xf1 = 0x66 end - device pnp 2e.a off # ACPI + device pnp 2e.a off // ACPI end - device pnp 2e.b on # HWM + device pnp 2e.b on // HWM io 0x60 = 0xa00 irq 0x70 = 0 end
end chip superio/winbond/w83627thg - device pnp 4e.0 off # Floppy + device pnp 4e.0 off // Floppy end - device pnp 4e.1 off # Parport + device pnp 4e.1 off // Parport end - device pnp 4e.2 on # COM3 + device pnp 4e.2 on // COM3 io 0x60 = 0x3e8 irq 0x70 = 11 end - device pnp 4e.3 on # COM4 + device pnp 4e.3 on // COM4 io 0x60 = 0x2e8 irq 0x70 = 10 - irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq + irq 0xf1 = 4 // set IRMODE 0 # XXX not an irq end - device pnp 4e.5 off # Keyboard + device pnp 4e.5 off // Keyboard end - device pnp 4e.7 off # GPIO1, GAME, MIDI + device pnp 4e.7 off // GPIO1, GAME, MIDI end - device pnp 4e.8 off # GPIO2 + device pnp 4e.8 off // GPIO2 end - device pnp 4e.9 off # GPIO3/4 + device pnp 4e.9 off // GPIO3/4 end - device pnp 4e.a off # ACPI + device pnp 4e.a off // ACPI end - device pnp 4e.b off # HWM + device pnp 4e.b off // HWM end end
end - #device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - #device pci 1f.4 off end # Realtek ID Codec + //device pci 1f.1 off end # IDE + device pci 1f.2 on end // SATA + device pci 1f.3 on end // SMBus + //device pci 1f.4 off end # Realtek ID Codec end end end diff --git a/src/mainboard/kontron/kt690/devicetree.cb b/src/mainboard/kontron/kt690/devicetree.cb index 68741ae..03f9a3c 100644 --- a/src/mainboard/kontron/kt690/devicetree.cb +++ b/src/mainboard/kontron/kt690/devicetree.cb @@ -1,13 +1,13 @@ -#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) -#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, -# 1: the system allows a PCIE link to be established on Dev2 or Dev3. -#Define gfx_dual_slot, 0: single slot, 1: dual slot -#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable -#Define gfx_tmds, 0: didn't support TMDS, 1: support -#Define gfx_compliance, 0: didn't support compliance, 1: support -#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration -#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 +//Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +//Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) +//Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, +// 1: the system allows a PCIE link to be established on Dev2 or Dev3. +//Define gfx_dual_slot, 0: single slot, 1: dual slot +//Define gfx_lane_reversal, 0: disable lane reversal, 1: enable +//Define gfx_tmds, 0: didn't support TMDS, 1: support +//Define gfx_compliance, 0: didn't support compliance, 1: support +//Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration +//Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex device lapic_cluster 0 on chip cpu/amd/socket_S1G1 @@ -17,19 +17,19 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on subsystemid 0x1488 0x6900 inherit chip northbridge/amd/amdk8 - device pci 18.0 on # southbridge + device pci 18.0 on // southbridge chip southbridge/amd/rs690 - device pci 0.0 on end # HT 0x7910 - device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - device pci 5.0 on end # Internal Graphics 0x791F + device pci 0.0 on end // HT 0x7910 + device pci 1.0 on // Internal Graphics P2P bridge 0x7912 + device pci 5.0 on end // Internal Graphics 0x791F end - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 - device pci 3.0 off end # PCIE P2P bridge 0x791b - device pci 4.0 on end # PCIE P2P bridge 0x7914 - device pci 5.0 on end # PCIE P2P bridge 0x7915 - device pci 6.0 on end # PCIE P2P bridge 0x7916 - device pci 7.0 on end # PCIE P2P bridge 0x7917 - device pci 8.0 off end # NB/SB Link P2P bridge + device pci 2.0 on end // PCIE P2P bridge (external graphics) 0x7913 + device pci 3.0 off end // PCIE P2P bridge 0x791b + device pci 4.0 on end // PCIE P2P bridge 0x7914 + device pci 5.0 on end // PCIE P2P bridge 0x7915 + device pci 6.0 on end // PCIE P2P bridge 0x7916 + device pci 7.0 on end // PCIE P2P bridge 0x7917 + device pci 8.0 off end // NB/SB Link P2P bridge register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" @@ -40,87 +40,87 @@ chip northbridge/amd/amdk8/root_complex register "gfx_reconfiguration" = "1" register "gfx_link_width" = "0" end - chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus - device pci 12.0 on end # SATA 0x4380 - device pci 13.0 on end # USB 0x4387 - device pci 13.1 on end # USB 0x4388 - device pci 13.2 on end # USB 0x4389 - device pci 13.3 on end # USB 0x438a - device pci 13.4 on end # USB 0x438b - device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 - chip drivers/generic/generic #dimm 0-0-0 + chip southbridge/amd/sb600 // it is under NB/SB Link, but on the same pri bus + device pci 12.0 on end // SATA 0x4380 + device pci 13.0 on end // USB 0x4387 + device pci 13.1 on end // USB 0x4388 + device pci 13.2 on end // USB 0x4389 + device pci 13.3 on end // USB 0x438a + device pci 13.4 on end // USB 0x438b + device pci 13.5 on end // USB 2 0x4386 + device pci 14.0 on // SM 0x4385 + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 + chip drivers/generic/generic //dimm 0-0-1 device i2c 51 on end end - end # SM - device pci 14.1 on end # IDE 0x438c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x438d + end // SM + device pci 14.1 on end // IDE 0x438c + device pci 14.2 on end // HDA 0x4383 + device pci 14.3 on // LPC 0x438d chip superio/winbond/w83627dhg - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # Com2 + device pnp 2e.3 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - #device pnp 2e.6 off # SPI - #end - device pnp 2e.307 off # GPIO 1 + //device pnp 2e.6 off # SPI + //end + device pnp 2e.307 off // GPIO 1 end - device pnp 2e.8 on # WDTO#, PLED + device pnp 2e.8 on // WDTO#, PLED end - device pnp 2e.009 off # GPIO2 + device pnp 2e.009 off // GPIO2 end - device pnp 2e.109 off # GPIO3 + device pnp 2e.109 off // GPIO3 end - device pnp 2e.209 off # GPIO4 + device pnp 2e.209 off // GPIO4 end - device pnp 2e.309 off # GPIO5 + device pnp 2e.309 off // GPIO5 end - device pnp 2e.a off # ACPI + device pnp 2e.a off // ACPI end - device pnp 2e.b on # HWM + device pnp 2e.b on // HWM io 0x60 = 0xa10 end - device pnp 2e.c off # PECI, SST + device pnp 2e.c off // PECI, SST end - end #superio/winbond/w83627dhg - #chip superio/smsc/fdc37n972 - # seems this chip is not used? - #end - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # ACI 0x4382 - device pci 14.6 on end # MCI 0x438e + end //superio/winbond/w83627dhg + //chip superio/smsc/fdc37n972 + // seems this chip is not used? + //end + end //LPC + device pci 14.4 on end // PCI 0x4384 + device pci 14.5 on end // ACI 0x4382 + device pci 14.6 on end // MCI 0x438e register "hda_viddid" = "0x10ec0888" - end #southbridge/amd/sb600 - end # device pci 18.0 + end //southbridge/amd/sb600 + end // device pci 18.0
device pci 18.0 on end device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end - end #northbridge/amd/amdk8 - end #pci_domain -end #northbridge/amd/amdk8/root_complex + end //northbridge/amd/amdk8 + end //pci_domain +end //northbridge/amd/amdk8/root_complex
diff --git a/src/mainboard/lanner/em8510/devicetree.cb b/src/mainboard/lanner/em8510/devicetree.cb index 5784a16..7060e58 100644 --- a/src/mainboard/lanner/em8510/devicetree.cb +++ b/src/mainboard/lanner/em8510/devicetree.cb @@ -2,51 +2,51 @@ chip northbridge/intel/i855 device pci_domain 0 on device pci 0.0 on end chip southbridge/intel/i82801dx -# pci 11.0 on end -# pci 11.1 on end -# pci 11.2 on end -# pci 11.3 on end -# pci 11.4 on end -# pci 11.5 on end -# pci 11.6 on end -# pci 12.0 on end +// pci 11.0 on end +// pci 11.1 on end +// pci 11.2 on end +// pci 11.3 on end +// pci 11.4 on end +// pci 11.5 on end +// pci 11.6 on end +// pci 12.0 on end register "enable_usb" = "0" register "enable_native_ide" = "0" device pci 1f.0 on - chip superio/winbond/w83627thg # link 1 - device pnp 2e.0 on # Floppy + chip superio/winbond/w83627thg // link 1 + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Parallel Port + device pnp 2e.1 on // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # Com2 + device pnp 2e.3 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.7 off end # GAME_MIDI_GIPO1 - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.7 off end // GAME_MIDI_GIPO1 + device pnp 2e.8 off end // GPIO2 + device pnp 2e.9 off end // GPIO3 + device pnp 2e.a off end // ACPI + device pnp 2e.b on // HW Monitor io 0x60 = 0x290 end register "com1" = "{1}" - # register "com1" = "{1, 0, 0x3f8, 4}" - # register "lpt" = "{1}" + // register "com1" = "{1, 0, 0x3f8, 4}" + // register "lpt" = "{1}" end end end diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 2817255..3426a54 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -1,24 +1,26 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2009 coresystems GmbH -## Copyright (C) 2011 Sven Schnelle svens@stackframe.org -## -## This program is free software; you can redistribute it and/or -## modify it under the terms of the GNU General Public License as -## published by the Free Software Foundation; version 2 of -## the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -## MA 02110-1301 USA -## +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle svens@stackframe.org + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <config.h>
chip northbridge/intel/i945
@@ -29,13 +31,13 @@ chip northbridge/intel/i945 end
device pci_domain 0 on - device pci 00.0 on # Host bridge + device pci 00.0 on /* Host bridge */ subsystemid 0x17aa 0x2017 end - device pci 02.0 on # VGA controller + device pci 02.0 on /* VGA controller */ subsystemid 0x17aa 0x201a end - device pci 02.1 on # display controller + device pci 02.1 on /* display controller */ subsystemid 0x17aa 0x201a end chip southbridge/intel/i82801gx @@ -48,10 +50,13 @@ chip northbridge/intel/i945 register "pirqg_routing" = "0x0b" register "pirqh_routing" = "0x0b"
- # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) + /* test */ + /* multiline + test */ + // GPI routing + // 0 No effect (default) + // 1 SMI/* (if corresponding ALT_GPI_SMI_EN bit is also set) */ + // 2 SCI (if corresponding GPIO_EN bit is also set) register "gpi13_routing" = "2" register "gpi12_routing" = "2" register "gpi8_routing" = "2" @@ -60,34 +65,34 @@ chip northbridge/intel/i945
register "gpe0_en" = "0x11000006"
- device pci 1b.0 on # Audio Cnotroller + device pci 1b.0 on /* Audio Cnotroller */ subsystemid 0x17aa 0x2010 end - device pci 1c.0 on end # Ethernet - device pci 1c.1 on end # Atheros WLAN - device pci 1d.0 on # USB UHCI + device pci 1c.0 on end /* Ethernet */ + device pci 1c.1 on end /* Atheros WLAN */ + device pci 1d.0 on /* USB UHCI */ subsystemid 0x17aa 0x200a end - device pci 1d.1 on # USB UHCI + device pci 1d.1 on /* USB UHCI */ subsystemid 0x17aa 0x200a end - device pci 1d.2 on # USB UHCI + device pci 1d.2 on /* USB UHCI */ subsystemid 0x17aa 0x200a end - device pci 1d.3 on # USB UHCI + device pci 1d.3 on /* USB UHCI */ subsystemid 0x17aa 0x200a end - device pci 1d.7 on # USB2 EHCI + device pci 1d.7 on /* USB2 EHCI */ subsystemid 0x17aa 0x200b end - device pci 1f.0 on # PCI-LPC bridge + device pci 1f.0 on /* PCI-LPC bridge */ subsystemid 0x17aa 0x2009 chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy + device pnp ff.1 on /* dummy */ end end chip ec/acpi - device pnp ff.2 on # dummy + device pnp ff.2 on /* dummy */ io 0x60 = 0x62 io 0x62 = 0x66 io 0x64 = 0x1600 @@ -95,57 +100,57 @@ chip northbridge/intel/i945 end end chip superio/nsc/pc87382 - device pnp 164e.2 on # IR + device pnp 164e.2 on /* IR */ io 0x60 = 0x2f8 end
- device pnp 164e.3 off # Serial Port + device pnp 164e.3 off /* Serial Port */ io 0x60 = 0x3f8 end
- device pnp 164e.7 on # GPIO + device pnp 164e.7 on /* GPIO */ io 0x60 = 0x1680 end
- device pnp 164e.19 on # DLPC + device pnp 164e.19 on /* DLPC */ io 0x60 = 0x164c end end
chip superio/nsc/pc87392 - device pnp 2e.0 off #FDC + device pnp 2e.0 off /*FDC */ end
- device pnp 2e.1 on # Parallel Port + device pnp 2e.1 on /* Parallel Port */ io 0x60 = 0x3bc irq 0x70 = 7 end
- device pnp 2e.2 off # Serial Port / IR + device pnp 2e.2 off /* Serial Port / IR */ io 0x60 = 0x2f8 irq 0x70 = 4 end
- device pnp 2e.3 on # Serial Port + device pnp 2e.3 on /* Serial Port */ io 0x60 = 0x3f8 irq 0x70 = 4 end
- device pnp 2e.7 on # GPIO + device pnp 2e.7 on /* GPIO */ io 0x60 = 0x1620 end
- device pnp 2e.a off # WDT + device pnp 2e.a off /* WDT */ end end end - device pci 1f.1 off # IDE + device pci 1f.1 off /* IDE */ subsystemid 0x17aa 0x200c end - device pci 1f.2 on # SATA + device pci 1f.2 on /* SATA */ subsystemid 0x17aa 0x200d end - device pci 1f.3 on # SMBUS + device pci 1f.3 on /* SMBUS */ subsystemid 0x17aa 0x200f end end diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index e2b4a40..2819ca9 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -313,11 +313,6 @@ void main(unsigned long bist) /* Set up the console */ uart_init();
-#if CONFIG_USBDEBUG - i82801gx_enable_usbdebug(1); - early_usbdebug_init(); -#endif - console_init();
/* Halt if there was a built in self test failure */ @@ -417,4 +412,10 @@ void main(unsigned long bist) #endif /* Set legacy Brightness control to full brightness */ pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, 0xff); + +#if CONFIG_USBDEBUG + i82801gx_enable_usbdebug(1); + early_usbdebug_init(); +#endif + } diff --git a/src/mainboard/lippert/frontrunner/devicetree.cb b/src/mainboard/lippert/frontrunner/devicetree.cb index 9c18076..3302844 100644 --- a/src/mainboard/lippert/frontrunner/devicetree.cb +++ b/src/mainboard/lippert/frontrunner/devicetree.cb @@ -5,16 +5,16 @@ chip northbridge/amd/gx2 end end
- #register "irqmap" = "0xaa5b" + //register "irqmap" = "0xaa5b" device pci_domain 0 on device pci 0.0 on end chip southbridge/amd/cs5535 register "setupflash" = "0" device pci 12.0 on - device pci 12.1 off end # SMI - device pci 12.2 on end # IDE - device pci 12.3 off end # Audio - device pci 12.4 off end # VGA + device pci 12.1 off end // SMI + device pci 12.2 on end // IDE + device pci 12.3 off end // Audio + device pci 12.4 off end // VGA end end end diff --git a/src/mainboard/lippert/hurricane-lx/devicetree.cb b/src/mainboard/lippert/hurricane-lx/devicetree.cb index 17c0b8b..d61af1b 100644 --- a/src/mainboard/lippert/hurricane-lx/devicetree.cb +++ b/src/mainboard/lippert/hurricane-lx/devicetree.cb @@ -1,87 +1,87 @@ chip northbridge/amd/lx device pci_domain 0 on - device pci 1.0 on end # Northbridge - device pci 1.1 on end # Graphics - device pci 1.2 on end # AES + device pci 1.0 on end // Northbridge + device pci 1.1 on end // Graphics + device pci 1.2 on end // AES chip southbridge/amd/cs5536 - # IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK - # SIRQ Mode = Active(Quiet) mode. Save power.... - # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse, - # UARTs, etc IRQs. OK - register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010 - register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above + // IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK + // SIRQ Mode = Active(Quiet) mode. Save power.... + // Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse, + // UARTs, etc IRQs. OK + register "lpc_serirq_enable" = "0x000012DA" // 00010010 11011010 + register "lpc_serirq_polarity" = "0x0000ED25" // inverse of above register "lpc_serirq_mode" = "1" register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "0" # 0:host, 1:device - register "enable_USBP4_overcurrent" = "0" # 0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "enable_ide_nand_flash" = "0" // 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" // 0:host, 1:device + register "enable_USBP4_overcurrent" = "0" // 0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) register "com1_enable" = "0" register "com1_address" = "0x3E8" register "com1_irq" = "6" register "com2_enable" = "0" register "com2_address" = "0x2E8" register "com2_irq" = "6" - register "unwanted_vpci[0]" = "0" # End of list has a zero - device pci 8.0 on end # Slot4 - device pci 9.0 on end # Slot3 - device pci a.0 on end # Slot2 - device pci b.0 on end # Slot1 - device pci c.0 on end # IT8888 - device pci d.0 on end # Mini-PCI - device pci e.0 on end # Ethernet - device pci f.0 on # ISA Bridge + register "unwanted_vpci[0]" = "0" // End of list has a zero + device pci 8.0 on end // Slot4 + device pci 9.0 on end // Slot3 + device pci a.0 on end // Slot2 + device pci b.0 on end // Slot1 + device pci c.0 on end // IT8888 + device pci d.0 on end // Mini-PCI + device pci e.0 on end // Ethernet + device pci f.0 on // ISA Bridge chip superio/ite/it8712f - device pnp 2e.0 on # Floppy + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Com1 + device pnp 2e.1 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 on # Com2 + device pnp 2e.2 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 on # Parallel port + device pnp 2e.3 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.4 on # EC - io 0x60 = 0x290 # EC - io 0x62 = 0x298 # PME + device pnp 2e.4 on // EC + io 0x60 = 0x290 // EC + io 0x62 = 0x298 // PME irq 0x70 = 9 end - device pnp 2e.5 on # PS/2 keyboard + device pnp 2e.5 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.6 on # PS/2 mouse + device pnp 2e.6 on // PS/2 mouse irq 0x70 = 12 end - device pnp 2e.7 on # GPIO - io 0x62 = 0x1220 # Simple I/O - io 0x64 = 0x1228 # SPI + device pnp 2e.7 on // GPIO + io 0x62 = 0x1220 // Simple I/O + io 0x64 = 0x1228 // SPI end - device pnp 2e.8 off # MIDI + device pnp 2e.8 off // MIDI io 0x60 = 0x300 irq 0x70 = 9 end - device pnp 2e.9 off # Game port + device pnp 2e.9 off // Game port io 0x60 = 0x220 end - device pnp 2e.a off end # CIR + device pnp 2e.a off end // CIR end end - device pci f.2 on end # IDE - device pci f.3 on end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI + device pci f.2 on end // IDE + device pci f.3 on end // Audio + device pci f.4 on end // OHCI + device pci f.5 on end // EHCI end end - # APIC cluster is late CPU init. + // APIC cluster is late CPU init. device lapic_cluster 0 on chip cpu/amd/model_lx device lapic 0 on end diff --git a/src/mainboard/lippert/literunner-lx/devicetree.cb b/src/mainboard/lippert/literunner-lx/devicetree.cb index 44d6010..95d661f 100644 --- a/src/mainboard/lippert/literunner-lx/devicetree.cb +++ b/src/mainboard/lippert/literunner-lx/devicetree.cb @@ -1,84 +1,84 @@ chip northbridge/amd/lx device pci_domain 0 on - device pci 1.0 on end # Northbridge - device pci 1.1 on end # Graphics - device pci 1.2 on end # AES + device pci 1.0 on end // Northbridge + device pci 1.1 on end // Graphics + device pci 1.2 on end // AES chip southbridge/amd/cs5536 - # IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK - # SIRQ Mode = Active(Quiet) mode. Save power.... - # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse, - # UARTs, etc IRQs. OK - register "lpc_serirq_enable" = "0x0000129A" # 00010010 10011010 - register "lpc_serirq_polarity" = "0x0000ED65" # inverse of above + // IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK + // SIRQ Mode = Active(Quiet) mode. Save power.... + // Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse, + // UARTs, etc IRQs. OK + register "lpc_serirq_enable" = "0x0000129A" // 00010010 10011010 + register "lpc_serirq_polarity" = "0x0000ED65" // inverse of above register "lpc_serirq_mode" = "1" register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "0" # 0:host, 1:device - register "enable_USBP4_overcurrent" = "0" # 0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "enable_ide_nand_flash" = "0" // 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" // 0:host, 1:device + register "enable_USBP4_overcurrent" = "0" // 0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) register "com1_enable" = "1" register "com1_address" = "0x3E8" register "com1_irq" = "6" register "com2_enable" = "0" register "com2_address" = "0x2E8" register "com2_irq" = "6" - register "unwanted_vpci[0]" = "0" # End of list has a zero - device pci 8.0 on end # Ethernet 2 - device pci c.0 on end # IT8888 - device pci d.0 on end # Mini-PCI - device pci e.0 on end # Ethernet 1 - device pci f.0 on # ISA Bridge + register "unwanted_vpci[0]" = "0" // End of list has a zero + device pci 8.0 on end // Ethernet 2 + device pci c.0 on end // IT8888 + device pci d.0 on end // Mini-PCI + device pci e.0 on end // Ethernet 1 + device pci f.0 on // ISA Bridge chip superio/ite/it8712f - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Com1 + device pnp 2e.1 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 on # Com2 + device pnp 2e.2 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 on # Parallel port + device pnp 2e.3 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.4 on # EC - io 0x60 = 0x290 # EC - io 0x62 = 0x298 # PME + device pnp 2e.4 on // EC + io 0x60 = 0x290 // EC + io 0x62 = 0x298 // PME irq 0x70 = 9 end - device pnp 2e.5 on # PS/2 keyboard + device pnp 2e.5 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.6 on # PS/2 mouse + device pnp 2e.6 on // PS/2 mouse irq 0x70 = 12 end - device pnp 2e.7 on # GPIO - io 0x62 = 0x1220 # Simple I/O - io 0x64 = 0x1228 # SPI + device pnp 2e.7 on // GPIO + io 0x62 = 0x1220 // Simple I/O + io 0x64 = 0x1228 // SPI end - device pnp 2e.8 off # MIDI + device pnp 2e.8 off // MIDI io 0x60 = 0x300 irq 0x70 = 9 end - device pnp 2e.9 off # Game port + device pnp 2e.9 off // Game port io 0x60 = 0x220 end - device pnp 2e.a off end # CIR + device pnp 2e.a off end // CIR end end - device pci f.2 on end # IDE - device pci f.3 on end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI + device pci f.2 on end // IDE + device pci f.3 on end // Audio + device pci f.4 on end // OHCI + device pci f.5 on end // EHCI end end - # APIC cluster is late CPU init. + // APIC cluster is late CPU init. device lapic_cluster 0 on chip cpu/amd/model_lx device lapic 0 on end diff --git a/src/mainboard/lippert/roadrunner-lx/devicetree.cb b/src/mainboard/lippert/roadrunner-lx/devicetree.cb index eae8479..e506013 100644 --- a/src/mainboard/lippert/roadrunner-lx/devicetree.cb +++ b/src/mainboard/lippert/roadrunner-lx/devicetree.cb @@ -1,86 +1,86 @@ chip northbridge/amd/lx device pci_domain 0 on - device pci 1.0 on end # Northbridge - device pci 1.1 on end # Graphics - device pci 1.2 on end # AES - chip southbridge/amd/cs5536 # Southbridge - # IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK - # SIRQ Mode = Active(Quiet) mode. Save power... - # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse, - # UARTs, etc IRQs. OK - register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010 - register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above + device pci 1.0 on end // Northbridge + device pci 1.1 on end // Graphics + device pci 1.2 on end // AES + chip southbridge/amd/cs5536 // Southbridge + // IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK + // SIRQ Mode = Active(Quiet) mode. Save power... + // Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse, + // UARTs, etc IRQs. OK + register "lpc_serirq_enable" = "0x000012DA" // 00010010 11011010 + register "lpc_serirq_polarity" = "0x0000ED25" // inverse of above register "lpc_serirq_mode" = "1" register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "0" # 0: host, 1:device - register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "enable_ide_nand_flash" = "0" // 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" // 0: host, 1:device + register "enable_USBP4_overcurrent" = "0" //0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) register "com1_enable" = "0" register "com1_address" = "0x3E8" register "com1_irq" = "6" register "com2_enable" = "0" register "com2_address" = "0x2E8" register "com2_irq" = "6" - register "unwanted_vpci[0]" = "0" # End of list has a zero - device pci 8.0 on end # Slot4 - device pci 9.0 on end # Slot3 - device pci a.0 on end # Slot2 - device pci b.0 on end # Slot1 - device pci c.0 on end # IT8888 - device pci e.0 on end # Ethernet - device pci f.0 on # ISA bridge + register "unwanted_vpci[0]" = "0" // End of list has a zero + device pci 8.0 on end // Slot4 + device pci 9.0 on end // Slot3 + device pci a.0 on end // Slot2 + device pci b.0 on end // Slot1 + device pci c.0 on end // IT8888 + device pci e.0 on end // Ethernet + device pci f.0 on // ISA bridge chip superio/ite/it8712f - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Com1 + device pnp 2e.1 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 on # Com2 + device pnp 2e.2 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 on # Parallel port + device pnp 2e.3 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.4 on # EC - io 0x60 = 0x290 # EC - io 0x62 = 0x298 # PME + device pnp 2e.4 on // EC + io 0x60 = 0x290 // EC + io 0x62 = 0x298 // PME irq 0x70 = 9 end - device pnp 2e.5 on # PS/2 keyboard + device pnp 2e.5 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.6 on # PS/2 mouse + device pnp 2e.6 on // PS/2 mouse irq 0x70 = 12 end - device pnp 2e.7 on # GPIO - io 0x62 = 0x1220 # Simple I/O - # io 0x64 = 0x1228 # SPI + device pnp 2e.7 on // GPIO + io 0x62 = 0x1220 // Simple I/O + // io 0x64 = 0x1228 # SPI end - device pnp 2e.8 off # MIDI + device pnp 2e.8 off // MIDI io 0x60 = 0x300 irq 0x70 = 9 end - device pnp 2e.9 off # Game port + device pnp 2e.9 off // Game port io 0x60 = 0x220 end - device pnp 2e.a off end # CIR + device pnp 2e.a off end // CIR end end - device pci f.2 on end # IDE controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI + device pci f.2 on end // IDE controller + device pci f.3 on end // Audio + device pci f.4 on end // OHCI + device pci f.5 on end // EHCI end end - # APIC cluster is late CPU init. + // APIC cluster is late CPU init. device lapic_cluster 0 on chip cpu/amd/model_lx device lapic 0 on end diff --git a/src/mainboard/lippert/spacerunner-lx/devicetree.cb b/src/mainboard/lippert/spacerunner-lx/devicetree.cb index 1fd2c54..35394c5 100644 --- a/src/mainboard/lippert/spacerunner-lx/devicetree.cb +++ b/src/mainboard/lippert/spacerunner-lx/devicetree.cb @@ -1,87 +1,87 @@ chip northbridge/amd/lx device pci_domain 0 on - device pci 1.0 on end # Northbridge - device pci 1.1 on end # Graphics - device pci 1.2 on end # AES + device pci 1.0 on end // Northbridge + device pci 1.1 on end // Graphics + device pci 1.2 on end // AES chip southbridge/amd/cs5536 - # IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK - # SIRQ Mode = Active(Quiet) mode. Save power.... - # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse, - # UARTs, etc IRQs. OK - register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010 - register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above + // IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK + // SIRQ Mode = Active(Quiet) mode. Save power.... + // Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse, + // UARTs, etc IRQs. OK + register "lpc_serirq_enable" = "0x000012DA" // 00010010 11011010 + register "lpc_serirq_polarity" = "0x0000ED25" // inverse of above register "lpc_serirq_mode" = "1" register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "0" # 0:host, 1:device - register "enable_USBP4_overcurrent" = "0" # 0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "enable_ide_nand_flash" = "0" // 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" // 0:host, 1:device + register "enable_USBP4_overcurrent" = "0" // 0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) register "com1_enable" = "0" register "com1_address" = "0x3E8" register "com1_irq" = "6" register "com2_enable" = "0" register "com2_address" = "0x2E8" register "com2_irq" = "6" - register "unwanted_vpci[0]" = "0x80007B00" # Audio: 1<<31 + Device 0x0F<<11 + Function 3<<8 - register "unwanted_vpci[1]" = "0" # End of list has a zero - device pci 8.0 on end # Slot4 - device pci 9.0 on end # Slot3 - device pci a.0 on end # Slot2 - device pci b.0 on end # Slot1 - device pci c.0 on end # IT8888 - device pci e.0 on end # Ethernet - device pci f.0 on # ISA Bridge + register "unwanted_vpci[0]" = "0x80007B00" // Audio: 1<<31 + Device 0x0F<<11 + Function 3<<8 + register "unwanted_vpci[1]" = "0" // End of list has a zero + device pci 8.0 on end // Slot4 + device pci 9.0 on end // Slot3 + device pci a.0 on end // Slot2 + device pci b.0 on end // Slot1 + device pci c.0 on end // IT8888 + device pci e.0 on end // Ethernet + device pci f.0 on // ISA Bridge chip superio/ite/it8712f - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Com1 + device pnp 2e.1 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 on # Com2 + device pnp 2e.2 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 on # Parallel port + device pnp 2e.3 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.4 on # EC - io 0x60 = 0x290 # EC - io 0x62 = 0x298 # PME + device pnp 2e.4 on // EC + io 0x60 = 0x290 // EC + io 0x62 = 0x298 // PME irq 0x70 = 9 end - device pnp 2e.5 on # PS/2 keyboard + device pnp 2e.5 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.6 on # PS/2 mouse + device pnp 2e.6 on // PS/2 mouse irq 0x70 = 12 end - device pnp 2e.7 on # GPIO - io 0x62 = 0x1220 # Simple I/O - io 0x64 = 0x1228 # SPI + device pnp 2e.7 on // GPIO + io 0x62 = 0x1220 // Simple I/O + io 0x64 = 0x1228 // SPI end - device pnp 2e.8 off # MIDI + device pnp 2e.8 off // MIDI io 0x60 = 0x300 irq 0x70 = 9 end - device pnp 2e.9 off # Game port + device pnp 2e.9 off // Game port io 0x60 = 0x220 end - device pnp 2e.a off end # CIR + device pnp 2e.a off end // CIR end end - device pci f.2 on end # IDE - device pci f.3 off end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI + device pci f.2 on end // IDE + device pci f.3 off end // Audio + device pci f.4 on end // OHCI + device pci f.5 on end // EHCI end end - # APIC cluster is late CPU init. + // APIC cluster is late CPU init. device lapic_cluster 0 on chip cpu/amd/model_lx device lapic 0 on end diff --git a/src/mainboard/mitac/6513wu/devicetree.cb b/src/mainboard/mitac/6513wu/devicetree.cb index df2d2ce..e933307 100644 --- a/src/mainboard/mitac/6513wu/devicetree.cb +++ b/src/mainboard/mitac/6513wu/devicetree.cb @@ -1,33 +1,33 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Michael Gold mgold@ncf.ca -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +// +// This file is part of the coreboot project. +// +// Copyright (C) 2009 Michael Gold mgold@ncf.ca +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +//
-chip northbridge/intel/i82810 # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device lapic 0 on end # APIC +chip northbridge/intel/i82810 // Northbridge + device lapic_cluster 0 on // APIC cluster + chip cpu/intel/socket_PGA370 // CPU + device lapic 0 on end // APIC end end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Graphics Memory Controller Hub (GMCH) device pci 1.0 on end - chip southbridge/intel/i82801ax # Southbridge + chip southbridge/intel/i82801ax // Southbridge register "pirqa_routing" = "0x03" register "pirqb_routing" = "0x05" register "pirqc_routing" = "0x09" @@ -36,49 +36,49 @@ chip northbridge/intel/i82810 # Northbridge register "ide0_enable" = "1" register "ide1_enable" = "1"
- device pci 1e.0 on # PCI bridge - device pci 5.0 on end # Audio controller (ESS ES1988) + device pci 1e.0 on // PCI bridge + device pci 5.0 on end // Audio controller (ESS ES1988) end - device pci 1f.0 on # ISA bridge - chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47U332) - device pnp 4e.0 on # Floppy + device pci 1f.0 on // ISA bridge + chip superio/smsc/smscsuperio // Super I/O (SMSC LPC47U332) + device pnp 4e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 4e.3 on # Parallel port + device pnp 4e.3 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 end - device pnp 4e.4 on # COM1 + device pnp 4e.4 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 4e.5 on # MIDI port (MPU-401) + device pnp 4e.5 on // MIDI port (MPU-401) io 0x60 = 0x330 irq 0x70 = 10 end - device pnp 4e.7 on # PS/2 keyboard / mouse - io 0x60 = 0x60 # XXX: not relocatable - io 0x62 = 0x64 # XXX: not relocatable - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt + device pnp 4e.7 on // PS/2 keyboard / mouse + io 0x60 = 0x60 // XXX: not relocatable + io 0x62 = 0x64 // XXX: not relocatable + irq 0x70 = 1 // PS/2 keyboard interrupt + irq 0x72 = 12 // PS/2 mouse interrupt end - device pnp 4e.9 on # Game port + device pnp 4e.9 on // Game port io 0x60 = 0x201 end - device pnp 4e.a on # Runtime registers + device pnp 4e.a on // Runtime registers io 0x60 = 0x400 end - device pnp 4e.b off end # SMBus + device pnp 4e.b off end // SMBus end end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMbus - device pci 1f.5 off end # Audio controller - device pci 1f.6 off end # Modem + device pci 1f.1 on end // IDE + device pci 1f.2 on end // USB + device pci 1f.3 on end // SMbus + device pci 1f.5 off end // Audio controller + device pci 1f.6 off end // Modem end end end diff --git a/src/mainboard/msi/ms6119/devicetree.cb b/src/mainboard/msi/ms6119/devicetree.cb index d5be59f..b7f5acc 100644 --- a/src/mainboard/msi/ms6119/devicetree.cb +++ b/src/mainboard/msi/ms6119/devicetree.cb @@ -1,56 +1,56 @@ -chip northbridge/intel/i440bx # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/slot_1 # CPU - device lapic 0 on end # APIC +chip northbridge/intel/i440bx // Northbridge + device lapic_cluster 0 on // APIC cluster + chip cpu/intel/slot_1 // CPU + device lapic 0 on end // APIC end end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 7.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O - device pnp 3f0.0 on # Floppy + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + device pci 1.0 on end // PCI/AGP bridge + chip southbridge/intel/i82371eb // Southbridge + device pci 7.0 on // ISA bridge + chip superio/winbond/w83977tf // Super I/O + device pnp 3f0.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 3f0.1 on # Parallel port + device pnp 3f0.1 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 end - device pnp 3f0.2 on # COM1 + device pnp 3f0.2 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 3f0.3 on # COM2 / IR + device pnp 3f0.3 on // COM2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 3f0.5 on # PS/2 keyboard + device pnp 3f0.5 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt + irq 0x70 = 1 // PS/2 keyboard interrupt + irq 0x72 = 12 // PS/2 mouse interrupt end - device pnp 3f0.7 on # GPIO 1 + device pnp 3f0.7 on // GPIO 1 end - device pnp 3f0.8 on # GPIO 2 + device pnp 3f0.8 on // GPIO 2 end - device pnp 3f0.9 on # GPIO 3 + device pnp 3f0.9 on // GPIO 3 end - device pnp 3f0.a on # ACPI + device pnp 3f0.a on // ACPI end end end - device pci 7.1 on end # IDE - device pci 7.2 on end # USB - device pci 7.3 on end # ACPI + device pci 7.1 on end // IDE + device pci 7.2 on end // USB + device pci 7.3 on end // ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. + // Enable UDMA/33 for higher speed if your IDE device(s) support it. register "ide0_drive0_udma33_enable" = "0" register "ide0_drive1_udma33_enable" = "0" register "ide1_drive0_udma33_enable" = "0" diff --git a/src/mainboard/msi/ms6147/devicetree.cb b/src/mainboard/msi/ms6147/devicetree.cb index 0500a7f..36d4bec 100644 --- a/src/mainboard/msi/ms6147/devicetree.cb +++ b/src/mainboard/msi/ms6147/devicetree.cb @@ -1,56 +1,56 @@ -chip northbridge/intel/i440bx # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/slot_1 # CPU - device lapic 0 on end # APIC +chip northbridge/intel/i440bx // Northbridge + device lapic_cluster 0 on // APIC cluster + chip cpu/intel/slot_1 // CPU + device lapic 0 on end // APIC end end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 7.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O - device pnp 3f0.0 on # Floppy + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + device pci 1.0 on end // PCI/AGP bridge + chip southbridge/intel/i82371eb // Southbridge + device pci 7.0 on // ISA bridge + chip superio/winbond/w83977tf // Super I/O + device pnp 3f0.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 3f0.1 on # Parallel port + device pnp 3f0.1 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 end - device pnp 3f0.2 on # COM1 + device pnp 3f0.2 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 3f0.3 on # COM2 / IR + device pnp 3f0.3 on // COM2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 3f0.5 on # PS/2 keyboard + device pnp 3f0.5 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt + irq 0x70 = 1 // PS/2 keyboard interrupt + irq 0x72 = 12 // PS/2 mouse interrupt end - device pnp 3f0.7 on # GPIO 1 + device pnp 3f0.7 on // GPIO 1 end - device pnp 3f0.8 on # GPIO 2 + device pnp 3f0.8 on // GPIO 2 end - device pnp 3f0.9 off # GPIO 3 + device pnp 3f0.9 off // GPIO 3 end - device pnp 3f0.a on # ACPI + device pnp 3f0.a on // ACPI end end end - device pci 7.1 on end # IDE - device pci 7.2 on end # USB - device pci 7.3 on end # ACPI + device pci 7.1 on end // IDE + device pci 7.2 on end // USB + device pci 7.3 on end // ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. + // Enable UDMA/33 for higher speed if your IDE device(s) support it. register "ide0_drive0_udma33_enable" = "1" register "ide0_drive1_udma33_enable" = "1" register "ide1_drive0_udma33_enable" = "1" diff --git a/src/mainboard/msi/ms6156/devicetree.cb b/src/mainboard/msi/ms6156/devicetree.cb index da3ba6f..c5badcc 100644 --- a/src/mainboard/msi/ms6156/devicetree.cb +++ b/src/mainboard/msi/ms6156/devicetree.cb @@ -1,77 +1,77 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann uwe@hermann-uwe.de -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +// +// This file is part of the coreboot project. +// +// Copyright (C) 2009 Uwe Hermann uwe@hermann-uwe.de +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +//
-chip northbridge/intel/i440bx # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/slot_1 # CPU - device lapic 0 on end # APIC +chip northbridge/intel/i440bx // Northbridge + device lapic_cluster 0 on // APIC cluster + chip cpu/intel/slot_1 // CPU + device lapic 0 on end // APIC end end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 7.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O - device pnp 3f0.0 on # Floppy + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + device pci 1.0 on end // PCI/AGP bridge + chip southbridge/intel/i82371eb // Southbridge + device pci 7.0 on // ISA bridge + chip superio/winbond/w83977tf // Super I/O + device pnp 3f0.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 3f0.1 on # Parallel port + device pnp 3f0.1 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 end - device pnp 3f0.2 on # COM1 + device pnp 3f0.2 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 3f0.3 on # COM2 / IR + device pnp 3f0.3 on // COM2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 3f0.5 on # PS/2 keyboard + device pnp 3f0.5 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt + irq 0x70 = 1 // PS/2 keyboard interrupt + irq 0x72 = 12 // PS/2 mouse interrupt end - device pnp 3f0.7 off # GPIO 1 + device pnp 3f0.7 off // GPIO 1 end - device pnp 3f0.8 off # GPIO 2 + device pnp 3f0.8 off // GPIO 2 end - device pnp 3f0.9 off # GPIO 3 + device pnp 3f0.9 off // GPIO 3 end - device pnp 3f0.a off # ACPI + device pnp 3f0.a off // ACPI end end end - device pci 7.1 on end # IDE - device pci 7.2 on end # USB - device pci 7.3 on end # ACPI - device pci 14.0 on end # Onboard audio (Ensoniq ES1371) + device pci 7.1 on end // IDE + device pci 7.2 on end // USB + device pci 7.3 on end // ACPI + device pci 14.0 on end // Onboard audio (Ensoniq ES1371) register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. + // Enable UDMA/33 for higher speed if your IDE device(s) support it. register "ide0_drive0_udma33_enable" = "1" register "ide0_drive1_udma33_enable" = "1" register "ide1_drive0_udma33_enable" = "1" diff --git a/src/mainboard/msi/ms6178/devicetree.cb b/src/mainboard/msi/ms6178/devicetree.cb index 569aee5..670a83d 100644 --- a/src/mainboard/msi/ms6178/devicetree.cb +++ b/src/mainboard/msi/ms6178/devicetree.cb @@ -1,83 +1,83 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann uwe@hermann-uwe.de -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +// +// This file is part of the coreboot project. +// +// Copyright (C) 2007 Uwe Hermann uwe@hermann-uwe.de +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +//
-chip northbridge/intel/i82810 # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device lapic 0 on end # APIC +chip northbridge/intel/i82810 // Northbridge + device lapic_cluster 0 on // APIC cluster + chip cpu/intel/socket_PGA370 // CPU + device lapic 0 on end // APIC end end device pci_domain 0 on - device pci 0.0 on end # Host bridge - device pci 1.0 on end # Onboard VGA - chip southbridge/intel/i82801ax # Southbridge + device pci 0.0 on end // Host bridge + device pci 1.0 on end // Onboard VGA + chip southbridge/intel/i82801ax // Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1"
- device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA/LPC bridge - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 on # Floppy + device pci 1e.0 on end // PCI bridge + device pci 1f.0 on // ISA/LPC bridge + chip superio/winbond/w83627hf // Super I/O + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Parallel port + device pnp 2e.1 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # Com2 (only header on board) + device pnp 2e.3 on // Com2 (only header on board) io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # PS/2 keyboard/mouse + device pnp 2e.5 on // PS/2 keyboard/mouse io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # Keyboard interrupt - irq 0x72 = 12 # Mouse interrupt + irq 0x70 = 1 // Keyboard interrupt + irq 0x72 = 12 // Mouse interrupt end - device pnp 2e.6 off end # Consumer IR (TODO) - device pnp 2e.7 on # Game port / MIDI / GPIO 1 + device pnp 2e.6 off end // Consumer IR (TODO) + device pnp 2e.7 on // Game port / MIDI / GPIO 1 io 0x60 = 0x201 io 0x62 = 0x330 irq 0x70 = 9 end - device pnp 2e.8 on end # GPIO 2 - device pnp 2e.9 on end # GPIO 3 - device pnp 2e.a on end # ACPI - device pnp 2e.b on # Hardware monitor + device pnp 2e.8 on end // GPIO 2 + device pnp 2e.9 on end // GPIO 3 + device pnp 2e.a on end // ACPI + device pnp 2e.b on // Hardware monitor io 0x60 = 0x290 irq 0x70 = 5 end end end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMBus - device pci 1f.5 on end # AC'97 audio - device pci 1f.6 on end # AC'97 modem + device pci 1f.1 on end // IDE + device pci 1f.2 on end // USB + device pci 1f.3 on end // SMBus + device pci 1f.5 on end // AC'97 audio + device pci 1f.6 on end // AC'97 modem end end end diff --git a/src/mainboard/msi/ms7135/devicetree.cb b/src/mainboard/msi/ms7135/devicetree.cb index 54e5d5e..cfe3542 100644 --- a/src/mainboard/msi/ms7135/devicetree.cb +++ b/src/mainboard/msi/ms7135/devicetree.cb @@ -1,66 +1,66 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device lapic_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_754 # CPU socket - device lapic 0 on end # Local APIC of the CPU +chip northbridge/amd/amdk8/root_complex // Root complex + device lapic_cluster 0 on // (L)APIC cluster + chip cpu/amd/socket_754 // CPU socket + device lapic 0 on end // Local APIC of the CPU end end
- device pci_domain 0 on # PCI domain + device pci_domain 0 on // PCI domain subsystemid 0x1462 0x7135 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627thg # Super I/O - device pnp 4e.0 on # Floppy + chip northbridge/amd/amdk8 // Northbridge / RAM controller + device pci 18.0 on // Link 0 == LDT 0 + chip southbridge/nvidia/ck804 // Southbridge + device pci 0.0 on end // HT + device pci 1.0 on // LPC + chip superio/winbond/w83627thg // Super I/O + device pnp 4e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 4e.1 on # Parallel port + device pnp 4e.1 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 end - device pnp 4e.2 on # Com1 + device pnp 4e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 4e.3 on # Com2 + device pnp 4e.3 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 4e.5 on # PS/2 keyboard & mouse + device pnp 4e.5 on // PS/2 keyboard & mouse io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 4e.7 off end # Game port, MIDI, GPIO 1 & 5 - device pnp 4e.8 off end # GPIO 2 - device pnp 4e.9 off end # GPIO 3, GPIO 4 - device pnp 4e.a off end # ACPI - device pnp 4e.b on # Hardware monitor + device pnp 4e.7 off end // Game port, MIDI, GPIO 1 & 5 + device pnp 4e.8 off end // GPIO 2 + device pnp 4e.9 off end // GPIO 3, GPIO 4 + device pnp 4e.a off end // ACPI + device pnp 4e.b on // Hardware monitor io 0x60 = 0x290 irq 0x70 = 5 end end end - device pci 1.1 on end # SMbus - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # Onboard audio (ACI) - device pci 4.1 off end # Onboard modem (MCI), N/A - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on end # PCI - device pci a.0 on end # NIC - device pci b.0 off end # PCI E 3 (N/A) - device pci c.0 off end # PCI E 2 (N/A) - device pci d.0 on end # PCI E 1 - device pci e.0 on end # PCI E 0 + device pci 1.1 on end // SMbus + device pci 2.0 on end // USB 1.1 + device pci 2.1 on end // USB 2 + device pci 4.0 on end // Onboard audio (ACI) + device pci 4.1 off end // Onboard modem (MCI), N/A + device pci 6.0 on end // IDE + device pci 7.0 on end // SATA 1 + device pci 8.0 on end // SATA 0 + device pci 9.0 on end // PCI + device pci a.0 on end // NIC + device pci b.0 off end // PCI E 3 (N/A) + device pci c.0 off end // PCI E 2 (N/A) + device pci d.0 on end // PCI E 1 + device pci e.0 on end // PCI E 0 register "ide0_enable" = "1" register "ide1_enable" = "1" register "sata0_enable" = "1" diff --git a/src/mainboard/msi/ms7260/devicetree.cb b/src/mainboard/msi/ms7260/devicetree.cb index 47d5381..853c3e1 100644 --- a/src/mainboard/msi/ms7260/devicetree.cb +++ b/src/mainboard/msi/ms7260/devicetree.cb @@ -1,156 +1,156 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device lapic_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_AM2 # CPU socket - device lapic 0 on end # Local APIC of the CPU +chip northbridge/amd/amdk8/root_complex // Root complex + device lapic_cluster 0 on // (L)APIC cluster + chip cpu/amd/socket_AM2 // CPU socket + device lapic 0 on end // Local APIC of the CPU end end - device pci_domain 0 on # PCI domain + device pci_domain 0 on // PCI domain subsystemid 0x1462 0x7260 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627ehg # Super I/O - device pnp 4e.0 on # Floppy + chip northbridge/amd/amdk8 // Northbridge / RAM controller + device pci 18.0 on // Link 0 == LDT 0 + chip southbridge/nvidia/mcp55 // Southbridge + device pci 0.0 on end // HT + device pci 1.0 on // LPC + chip superio/winbond/w83627ehg // Super I/O + device pnp 4e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 4e.1 on # Parallel port + device pnp 4e.1 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 4e.2 on # Com1 + device pnp 4e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 4e.3 on # Com2 / IrDA + device pnp 4e.3 on // Com2 / IrDA io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 4e.5 on # PS/2 keyboard & mouse + device pnp 4e.5 on // PS/2 keyboard & mouse io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard IRQ - irq 0x72 = 12 # PS/2 mouse IRQ + irq 0x70 = 1 // PS/2 keyboard IRQ + irq 0x72 = 12 // PS/2 mouse IRQ end - device pnp 4e.106 off # Serial flash interface (SFI) - # io 0x62 = 0x100 + device pnp 4e.106 off // Serial flash interface (SFI) + // io 0x62 = 0x100 end - device pnp 4e.007 off # GPIO 1 + device pnp 4e.007 off // GPIO 1 end - device pnp 4e.107 off # Game port - # io 0x60 = 0x220 # Datasheet: 0x201 + device pnp 4e.107 off // Game port + // io 0x60 = 0x220 # Datasheet: 0x201 end - device pnp 4e.207 off # MIDI - # io 0x62 = 0x300 # Datasheet: 0x330 - # irq 0x70 = 9 + device pnp 4e.207 off // MIDI + // io 0x62 = 0x300 # Datasheet: 0x330 + // irq 0x70 = 9 end - device pnp 4e.307 off # GPIO 6 + device pnp 4e.307 off // GPIO 6 end - device pnp 4e.8 off # WDTO#, PLED + device pnp 4e.8 off // WDTO#, PLED end - device pnp 4e.009 off # GPIO 2 + device pnp 4e.009 off // GPIO 2 end - device pnp 4e.109 off # GPIO 3 + device pnp 4e.109 off // GPIO 3 end - device pnp 4e.209 off # GPIO 4 + device pnp 4e.209 off // GPIO 4 end - device pnp 4e.309 off # GPIO 5 + device pnp 4e.309 off // GPIO 5 end - device pnp 4e.a off # ACPI + device pnp 4e.a off // ACPI end - device pnp 4e.b on # Hardware monitor + device pnp 4e.b on // Hardware monitor io 0x60 = 0xa10 - # TODO: IRQ? + // TODO: IRQ? end end end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 + device pci 1.1 on // SM 0 + chip drivers/generic/generic // DIMM 0-0-0 device i2c 50 on end end - chip drivers/generic/generic # DIMM 0-0-1 + chip drivers/generic/generic // DIMM 0-0-1 device i2c 51 on end end - chip drivers/generic/generic # DIMM 0-1-0 + chip drivers/generic/generic // DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 + chip drivers/generic/generic // DIMM 0-1-1 device i2c 53 on end end end - # TODO: Check if the stuff below is correct / needed. - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM + // TODO: Check if the stuff below is correct / needed. + device pci 1.1 on // SM 1 + // PCI device SMBus address will + // depend on addon PCI device, do + // we need to scan_smbus_bus? + // chip drivers/generic/generic # PCIXA slot 1 + // device i2c 50 on end + // end + // chip drivers/generic/generic # PCIXB slot 1 + // device i2c 51 on end + // end + // chip drivers/generic/generic # PCIXB slot 2 + // device i2c 52 on end + // end + // chip drivers/generic/generic # PCI slot 1 + // device i2c 53 on end + // end + // chip drivers/generic/generic # Master MCP55 PCI-E + // device i2c 54 on end + // end + // chip drivers/generic/generic # Slave MCP55 PCI-E + // device i2c 55 on end + // end + chip drivers/generic/generic // MAC EEPROM device i2c 51 on end end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 off end # SATA 2 (N/A on this board) - device pci 6.0 on end # PCI - device pci 6.1 on end # AZA (HD Audio) - device pci 8.0 on end # NIC - device pci 9.0 off end # NIC (N/A on this board) - device pci a.0 off end # PCI E 5 (N/A on this board?) - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 + device pci 2.0 on end // USB 1.1 + device pci 2.1 on end // USB 2 + device pci 4.0 on end // IDE + device pci 5.0 on end // SATA 0 + device pci 5.1 on end // SATA 1 + device pci 5.2 off end // SATA 2 (N/A on this board) + device pci 6.0 on end // PCI + device pci 6.1 on end // AZA (HD Audio) + device pci 8.0 on end // NIC + device pci 9.0 off end // NIC (N/A on this board) + device pci a.0 off end // PCI E 5 (N/A on this board?) + device pci b.0 on end // PCI E 4 + device pci c.0 on end // PCI E 3 + device pci d.0 on end // PCI E 2 + device pci e.0 on end // PCI E 1 + device pci f.0 on end // PCI E 0 register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # TODO: Check the two lines below. - # 1: SMBus under 2e.8, 2: SM0 3: SM1 + // TODO: Check the two lines below. + // 1: SMBus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" end end - device pci 18.0 on end # Link 1 + device pci 18.0 on end // Link 1 device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end end - # TODO - # chip drivers/generic/debug - # device pnp 0.0 off end # chip name - # device pnp 0.1 on end # pci_regs_all - # device pnp 0.2 on end # mem - # device pnp 0.3 off end # cpuid - # device pnp 0.4 on end # smbus_regs_all - # device pnp 0.5 off end # dual core msr - # device pnp 0.6 off end # cache size - # device pnp 0.7 off end # tsc - # device pnp 0.8 off end # io - # device pnp 0.9 off end # io - # end + // TODO + // chip drivers/generic/debug + // device pnp 0.0 off end # chip name + // device pnp 0.1 on end # pci_regs_all + // device pnp 0.2 on end # mem + // device pnp 0.3 off end # cpuid + // device pnp 0.4 on end # smbus_regs_all + // device pnp 0.5 off end # dual core msr + // device pnp 0.6 off end # cache size + // device pnp 0.7 off end # tsc + // device pnp 0.8 off end # io + // device pnp 0.9 off end # io + // end end diff --git a/src/mainboard/msi/ms9185/devicetree.cb b/src/mainboard/msi/ms9185/devicetree.cb index 9576225..16db972 100644 --- a/src/mainboard/msi/ms9185/devicetree.cb +++ b/src/mainboard/msi/ms9185/devicetree.cb @@ -9,89 +9,89 @@ chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8 device pci 18.0 on end device pci 18.0 on end - device pci 18.0 on # northbridge - # devices on link 0 - chip southbridge/broadcom/bcm5780 # HT2000 - device pci 0.0 on end # PXB 1 0x0130 - device pci 1.0 on # PXB 2 0x0130 - device pci 4.0 on end # GB E 0x1668 vid = 0x14e4 - device pci 4.1 on end # GB E 0x1669 vid = 0x14e4 + device pci 18.0 on // northbridge + // devices on link 0 + chip southbridge/broadcom/bcm5780 // HT2000 + device pci 0.0 on end // PXB 1 0x0130 + device pci 1.0 on // PXB 2 0x0130 + device pci 4.0 on end // GB E 0x1668 vid = 0x14e4 + device pci 4.1 on end // GB E 0x1669 vid = 0x14e4 end - device pci 2.0 on end # PCI E 1 #0x0132 - device pci 3.0 on end # PCI E 2 - device pci 4.0 on end # PCI E 3 - device pci 5.0 on end # PCI E 4 + device pci 2.0 on end // PCI E 1 #0x0132 + device pci 3.0 on end // PCI E 2 + device pci 4.0 on end // PCI E 3 + device pci 5.0 on end // PCI E 4 end - chip southbridge/broadcom/bcm5785 # HT1000 - device pci 0.0 on # HT PXB 0x0036 - device pci d.0 on end # PPBX 0x0104 - device pci e.0 on end # SATA 0x024a - device pci e.1 on end # SATA 0x024a bx_a001 - device pci e.2 on end # SATA 0x024a bx_a001 - device pci e.3 on end # SATA 0x024a bx_a001 + chip southbridge/broadcom/bcm5785 // HT1000 + device pci 0.0 on // HT PXB 0x0036 + device pci d.0 on end // PPBX 0x0104 + device pci e.0 on end // SATA 0x024a + device pci e.1 on end // SATA 0x024a bx_a001 + device pci e.2 on end // SATA 0x024a bx_a001 + device pci e.3 on end // SATA 0x024a bx_a001 end - device pci 1.0 on # Legacy pci main 0x0205 + device pci 1.0 on // Legacy pci main 0x0205 end - device pci 1.1 on end # IDE 0x0214 - device pci 1.2 on # LPC 0x0234 + device pci 1.1 on end // IDE 0x0214 + device pci 1.2 on // LPC 0x0234 chip superio/nsc/pc87417 - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 off # Com 2 + device pnp 2e.2 off // Com 2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 on # Com 1 + device pnp 2e.3 on // Com 1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.4 off end # SWC - device pnp 2e.5 off end # Mouse - device pnp 2e.6 on # Keyboard + device pnp 2e.4 off end // SWC + device pnp 2e.5 off end // Mouse + device pnp 2e.6 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.7 off end # GPIO - device pnp 2e.f off end # XBUS - device pnp 2e.10 on #RTC + device pnp 2e.7 off end // GPIO + device pnp 2e.f off end // XBUS + device pnp 2e.10 on //RTC io 0x60 = 0x70 io 0x62 = 0x72 end end end - device pci 1.3 on end # WDTimer 0x0238 - device pci 1.4 on end # XIOAPIC0 0x0235 - device pci 1.5 on end # XIOAPIC1 - device pci 1.6 on end # XIOAPIC2 - device pci 2.0 on end # USB 0x0223 - device pci 2.1 on end # USB - device pci 2.2 on end # USB - device pci 3.0 on end # it is in bcm5785_0 bus + device pci 1.3 on end // WDTimer 0x0238 + device pci 1.4 on end // XIOAPIC0 0x0235 + device pci 1.5 on end // XIOAPIC1 + device pci 1.6 on end // XIOAPIC2 + device pci 2.0 on end // USB 0x0223 + device pci 2.1 on end // USB + device pci 2.2 on end // USB + device pci 3.0 on end // it is in bcm5785_0 bus end - end # device pci 18.0 + end // device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end - end # amdk8 - end #pci_domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# end + end // amdk8 + end //pci_domain +// chip drivers/generic/debug +// device pnp 0.0 off end # chip name +// device pnp 0.1 on end # pci_regs_all +// device pnp 0.2 off end # mem +// device pnp 0.3 off end # cpuid +// device pnp 0.4 off end # smbus_regs_all +// device pnp 0.5 off end # dual core msr +// device pnp 0.6 off end # cache size +// device pnp 0.7 off end # tsc +// end
end
diff --git a/src/mainboard/msi/ms9282/devicetree.cb b/src/mainboard/msi/ms9282/devicetree.cb index b52e7ed..4758f47 100644 --- a/src/mainboard/msi/ms9282/devicetree.cb +++ b/src/mainboard/msi/ms9282/devicetree.cb @@ -1,190 +1,190 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device lapic_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F # CPU socket - device lapic 0 on end # Local APIC of the CPU +chip northbridge/amd/amdk8/root_complex // Root complex + device lapic_cluster 0 on // (L)APIC cluster + chip cpu/amd/socket_F // CPU socket + device lapic 0 on end // Local APIC of the CPU end end - device pci_domain 0 on # PCI domain + device pci_domain 0 on // PCI domain subsystemid 0x1462 0x9282 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627ehg # Super I/O - device pnp 2e.0 on # Floppy + chip northbridge/amd/amdk8 // Northbridge / RAM controller + device pci 18.0 on // Link 0 == LDT 0 + chip southbridge/nvidia/mcp55 // Southbridge + device pci 0.0 on end // HT + device pci 1.0 on // LPC + chip superio/winbond/w83627ehg // Super I/O + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel port + device pnp 2e.1 off // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.3 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # PS/2 keyboard & mouse + device pnp 2e.5 on // PS/2 keyboard & mouse io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.106 off # Serial flash interface (SFI) + device pnp 2e.106 off // Serial flash interface (SFI) io 0x60 = 0x100 end - device pnp 2e.007 off # GPIO 1 + device pnp 2e.007 off // GPIO 1 end - device pnp 2e.107 off # Game port + device pnp 2e.107 off // Game port io 0x60 = 0x220 end - device pnp 2e.207 off # MIDI + device pnp 2e.207 off // MIDI io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.307 off # GPIO 6 + device pnp 2e.307 off // GPIO 6 end - device pnp 2e.8 off end # WDTO#, PLED - device pnp 2e.009 off # GPIO 2 + device pnp 2e.8 off end // WDTO#, PLED + device pnp 2e.009 off // GPIO 2 end - device pnp 2e.109 off # GPIO 3 + device pnp 2e.109 off // GPIO 3 end - device pnp 2e.209 off # GPIO 4 + device pnp 2e.209 off // GPIO 4 end - device pnp 2e.309 off # GPIO 5 + device pnp 2e.309 off // GPIO 5 end - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor + device pnp 2e.a off end // ACPI + device pnp 2e.b on // Hardware monitor io 0x60 = 0x290 irq 0x70 = 5 end end end - device pci 1.1 on # SM 0 - chip drivers/i2c/i2cmux2 # PCA9554 SMBus mux - device i2c 70 on # 0 pca9554 1 - chip drivers/generic/generic # DIMM 0-0-0 + device pci 1.1 on // SM 0 + chip drivers/i2c/i2cmux2 // PCA9554 SMBus mux + device i2c 70 on // 0 pca9554 1 + chip drivers/generic/generic // DIMM 0-0-0 device i2c 50 on end end - chip drivers/generic/generic # DIMM 0-0-1 + chip drivers/generic/generic // DIMM 0-0-1 device i2c 51 on end end - chip drivers/generic/generic # DIMM 0-1-0 + chip drivers/generic/generic // DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 + chip drivers/generic/generic // DIMM 0-1-1 device i2c 53 on end end - chip drivers/generic/generic # DIMM 0-0-0 + chip drivers/generic/generic // DIMM 0-0-0 device i2c 54 on end end - chip drivers/generic/generic # DIMM 0-0-1 + chip drivers/generic/generic // DIMM 0-0-1 device i2c 55 on end end - chip drivers/generic/generic # DIMM 0-1-0 + chip drivers/generic/generic // DIMM 0-1-0 device i2c 56 on end end - chip drivers/generic/generic # DIMM 0-1-1 + chip drivers/generic/generic // DIMM 0-1-1 device i2c 57 on end end end - device i2c 70 on # 0 pca9554 2 - chip drivers/generic/generic # DIMM 0-0-0 + device i2c 70 on // 0 pca9554 2 + chip drivers/generic/generic // DIMM 0-0-0 device i2c 50 on end end - chip drivers/generic/generic # DIMM 0-0-1 + chip drivers/generic/generic // DIMM 0-0-1 device i2c 51 on end end - chip drivers/generic/generic # DIMM 0-1-0 + chip drivers/generic/generic // DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 + chip drivers/generic/generic // DIMM 0-1-1 device i2c 53 on end end - chip drivers/generic/generic # DIMM 0-0-0 + chip drivers/generic/generic // DIMM 0-0-0 device i2c 54 on end end - chip drivers/generic/generic # DIMM 0-0-1 + chip drivers/generic/generic // DIMM 0-0-1 device i2c 55 on end end - chip drivers/generic/generic # DIMM 0-1-0 + chip drivers/generic/generic // DIMM 0-1-0 device i2c 56 on end end - chip drivers/generic/generic # DIMM 0-1-1 + chip drivers/generic/generic // DIMM 0-1-1 device i2c 57 on end end end end end - device pci 1.1 on # SM 1 - chip drivers/i2c/i2cmux2 # pca9554 SMBus mux - device i2c 72 on # PCA9554 channel 1 - chip drivers/i2c/adm1027 # HWM ADT7476 1 + device pci 1.1 on // SM 1 + chip drivers/i2c/i2cmux2 // pca9554 SMBus mux + device i2c 72 on // PCA9554 channel 1 + chip drivers/i2c/adm1027 // HWM ADT7476 1 device i2c 2e on end end end - device i2c 72 on # PCA9545 channel 2 - chip drivers/i2c/adm1027 # HWM ADT7463 + device i2c 72 on // PCA9545 channel 2 + chip drivers/i2c/adm1027 // HWM ADT7463 device i2c 2e on end end end - device i2c 72 on end # PCA9545 channel 3 - device i2c 72 on # PCA9545 channel 4 - chip drivers/i2c/adm1027 # HWM ADT7476 2 + device i2c 72 on end // PCA9545 channel 3 + device i2c 72 on // PCA9545 channel 4 + chip drivers/i2c/adm1027 // HWM ADT7476 2 device i2c 2e on end end end end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # P2P + device pci 2.0 on end // USB 1.1 + device pci 2.1 on end // USB 2 + device pci 4.0 on end // IDE + device pci 5.0 on end // SATA 0 + device pci 5.1 on end // SATA 1 + device pci 5.2 on end // SATA 2 + device pci 6.0 on // P2P device pci 4.0 on end end - device pci 7.0 on end # reserve - device pci 8.0 on end # MAC0 - device pci 9.0 on end # MAC1 + device pci 7.0 on end // reserve + device pci 8.0 on end // MAC0 + device pci 9.0 on end // MAC1 device pci a.0 on device pci 0.0 on - device pci 4.0 on end # PCI-E LAN1 - device pci 4.1 on end # PCI-E LAN2 + device pci 4.0 on end // PCI-E LAN1 + device pci 4.1 on end // PCI-E LAN2 end - end # 0x376 - device pci b.0 on end # PCI E 0x374 + end // 0x376 + device pci b.0 on end // PCI E 0x374 device pci c.0 on end - device pci d.0 on # SAS + device pci d.0 on // SAS device pci 0.0 on end - end # PCI E 1 0x378 - device pci e.0 on end # PCI E 0 0x375 - device pci f.0 on end # PCI E 0x377, PCI-E slot + end // PCI E 1 0x378 + device pci e.0 on end // PCI E 0 0x375 + device pci f.0 on end // PCI E 0x377, PCI-E slot register "ide0_enable" = "1" register "ide1_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" end end - device pci 18.0 on end # Link 1 + device pci 18.0 on end // Link 1 device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end - # device pnp 0.1 off end - # device pnp 0.2 off end - # device pnp 0.3 off end - # device pnp 0.4 off end - # device pnp 0.5 on end - # end + // chip drivers/generic/debug + // device pnp 0.0 off end + // device pnp 0.1 off end + // device pnp 0.2 off end + // device pnp 0.3 off end + // device pnp 0.4 off end + // device pnp 0.5 on end + // end end diff --git a/src/mainboard/msi/ms9652_fam10/devicetree.cb b/src/mainboard/msi/ms9652_fam10/devicetree.cb index 0e9a3ff..9573e7d 100644 --- a/src/mainboard/msi/ms9652_fam10/devicetree.cb +++ b/src/mainboard/msi/ms9652_fam10/devicetree.cb @@ -1,181 +1,181 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## Written by Yinghai Lu yinghailu@amd.com for AMD. -## Copyright (C) 2010 Raptor Engineering -## Written by Timothy Pearson tpearson@raptorengineeringinc.com for Raptor Engineering. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +// +// This file is part of the coreboot project. +// +// Copyright (C) 2007 AMD +// Written by Yinghai Lu yinghailu@amd.com for AMD. +// Copyright (C) 2010 Raptor Engineering +// Written by Timothy Pearson tpearson@raptorengineeringinc.com for Raptor Engineering. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +//
-chip northbridge/amd/amdfam10/root_complex # Root complex - device lapic_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F_1207 # CPU socket - device lapic 0 on end # Local APIC of the CPU +chip northbridge/amd/amdfam10/root_complex // Root complex + device lapic_cluster 0 on // (L)APIC cluster + chip cpu/amd/socket_F_1207 // CPU socket + device lapic 0 on end // Local APIC of the CPU end end - device pci_domain 0 on # PCI domain + device pci_domain 0 on // PCI domain subsystemid 0x1462 0x9652 inherit - chip northbridge/amd/amdfam10 # Northbridge / RAM controller - device pci 18.0 on # Link 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627ehg # Super I/O - device pnp 2e.0 on # Floppy + chip northbridge/amd/amdfam10 // Northbridge / RAM controller + device pci 18.0 on // Link 0 + chip southbridge/nvidia/mcp55 // Southbridge + device pci 0.0 on end // HT + device pci 1.0 on // LPC + chip superio/winbond/w83627ehg // Super I/O + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel port + device pnp 2e.1 off // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # Com2 + device pnp 2e.3 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # PS/2 keyboard & mouse + device pnp 2e.5 on // PS/2 keyboard & mouse io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.106 off # Serial flash interface (SFI) + device pnp 2e.106 off // Serial flash interface (SFI) io 0x60 = 0x100 end - device pnp 2e.007 off # GPIO 1 + device pnp 2e.007 off // GPIO 1 end - device pnp 2e.107 on # Game port + device pnp 2e.107 on // Game port io 0x60 = 0x220 end - device pnp 2e.207 on # MIDI + device pnp 2e.207 on // MIDI io 0x62 = 0x330 irq 0x70 = 0xa end - device pnp 2e.307 off # GPIO 6 + device pnp 2e.307 off // GPIO 6 end - device pnp 2e.8 off # WDTO#, PLED + device pnp 2e.8 off // WDTO#, PLED end - device pnp 2e.009 off # GPIO 2 + device pnp 2e.009 off // GPIO 2 end - device pnp 2e.109 off # GPIO 3 + device pnp 2e.109 off // GPIO 3 end - device pnp 2e.209 off # GPIO 4 + device pnp 2e.209 off // GPIO 4 end - device pnp 2e.309 off # GPIO 5 + device pnp 2e.309 off // GPIO 5 end - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor + device pnp 2e.a off end // ACPI + device pnp 2e.b on // Hardware monitor io 0x60 = 0x290 irq 0x70 = 5 end end end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 + device pci 1.1 on // SM 0 + chip drivers/generic/generic // DIMM 0-0-0 device i2c 50 on end end - chip drivers/generic/generic # DIMM 0-0-1 + chip drivers/generic/generic // DIMM 0-0-1 device i2c 51 on end end - chip drivers/generic/generic # DIMM 0-1-0 + chip drivers/generic/generic // DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 + chip drivers/generic/generic // DIMM 0-1-1 device i2c 53 on end end - chip drivers/generic/generic # DIMM 1-0-0 + chip drivers/generic/generic // DIMM 1-0-0 device i2c 54 on end end - chip drivers/generic/generic # DIMM 1-0-1 + chip drivers/generic/generic // DIMM 1-0-1 device i2c 55 on end end - chip drivers/generic/generic # DIMM 1-1-0 + chip drivers/generic/generic // DIMM 1-1-0 device i2c 56 on end end - chip drivers/generic/generic # DIMM 1-1-1 + chip drivers/generic/generic // DIMM 1-1-1 device i2c 57 on end end end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - # chip drivers/generic/generic # MAC EEPROM - # device i2c 51 on end - # end + device pci 1.1 on // SM 1 + // PCI device SMBus address will + // depend on addon PCI device, do + // we need to scan_smbus_bus? + // chip drivers/generic/generic # PCIXA slot 1 + // device i2c 50 on end + // end + // chip drivers/generic/generic # PCIXB slot 1 + // device i2c 51 on end + // end + // chip drivers/generic/generic # PCIXB slot 2 + // device i2c 52 on end + // end + // chip drivers/generic/generic # PCI slot 1 + // device i2c 53 on end + // end + // chip drivers/generic/generic # Master MCP55 PCI-E + // device i2c 54 on end + // end + // chip drivers/generic/generic # Slave MCP55 PCI-E + // device i2c 55 on end + // end + // chip drivers/generic/generic # MAC EEPROM + // device i2c 51 on end + // end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC + device pci 2.0 on end // USB 1.1 + device pci 2.1 on end // USB 2 + device pci 4.0 on end // IDE + device pci 5.0 on end // SATA 0 + device pci 5.1 on end // SATA 1 + device pci 5.2 on end // SATA 2 + device pci 6.1 on end // AZA + device pci 8.0 on end // NIC + device pci 9.0 on end // NIC register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 + // 1: SMBus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" end end - device pci 18.0 on end # HT 1.0 - device pci 18.0 on end # HT 2.0 + device pci 18.0 on end // HT 1.0 + device pci 18.0 on end // HT 2.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end # chip name - # device pnp 0.1 on end # pci_regs_all - # device pnp 0.2 on end # mem - # device pnp 0.3 off end # cpuid - # device pnp 0.4 on end # smbus_regs_all - # device pnp 0.5 off end # dual core msr - # device pnp 0.6 off end # cache size - # device pnp 0.7 off end # tsc - # device pnp 0.8 off end # io - # device pnp 0.9 off end # io - # end + // chip drivers/generic/debug + // device pnp 0.0 off end # chip name + // device pnp 0.1 on end # pci_regs_all + // device pnp 0.2 on end # mem + // device pnp 0.3 off end # cpuid + // device pnp 0.4 on end # smbus_regs_all + // device pnp 0.5 off end # dual core msr + // device pnp 0.6 off end # cache size + // device pnp 0.7 off end # tsc + // device pnp 0.8 off end # io + // device pnp 0.9 off end # io + // end end diff --git a/src/mainboard/nec/powermate2000/devicetree.cb b/src/mainboard/nec/powermate2000/devicetree.cb index 37a15e1..cf6efa1 100644 --- a/src/mainboard/nec/powermate2000/devicetree.cb +++ b/src/mainboard/nec/powermate2000/devicetree.cb @@ -1,53 +1,53 @@ -chip northbridge/intel/i82810 # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device lapic 0 on end # APIC +chip northbridge/intel/i82810 // Northbridge + device lapic_cluster 0 on // APIC cluster + chip cpu/intel/socket_PGA370 // CPU + device lapic 0 on end // APIC end end device pci_domain 0 on - device pci 0.0 on end # Host bridge - device pci 1.0 off end # Onboard video - chip southbridge/intel/i82801ax # Southbridge + device pci 0.0 on end // Host bridge + device pci 1.0 off end // Onboard video + chip southbridge/intel/i82801ax // Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1"
- device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA/LPC bridge - chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47B27x) - device pnp 2e.0 on # Floppy + device pci 1e.0 on end // PCI bridge + device pci 1f.0 on // ISA/LPC bridge + chip superio/smsc/smscsuperio // Super I/O (SMSC LPC47B27x) + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.3 on # Parallel port + device pnp 2e.3 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 end - device pnp 2e.4 on # Com1 + device pnp 2e.4 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.5 off end # Com2 (N/A) - device pnp 2e.7 on # PS/2 keyboard + device pnp 2e.5 off end // Com2 (N/A) + device pnp 2e.7 on // PS/2 keyboard irq 0x70 = 1 irq 0x72 = 0 end - device pnp 2e.9 off end # Game port (N/A) - device pnp 2e.a on # Power-management events (PME) + device pnp 2e.9 off end // Game port (N/A) + device pnp 2e.a on // Power-management events (PME) io 0x60 = 0x800 end - device pnp 2e.b on # MIDI port + device pnp 2e.b on // MIDI port io 0x60 = 0x330 irq 0x70 = 5 end end end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMBus - device pci 1f.5 on end # AC'97 audio - device pci 1f.6 off end # AC'97 modem (N/A) + device pci 1f.1 on end // IDE + device pci 1f.2 on end // USB + device pci 1f.3 on end // SMBus + device pci 1f.5 on end // AC'97 audio + device pci 1f.6 off end // AC'97 modem (N/A) end end end diff --git a/src/mainboard/newisys/khepri/devicetree.cb b/src/mainboard/newisys/khepri/devicetree.cb index 9cdbc9c..23cfb3d 100644 --- a/src/mainboard/newisys/khepri/devicetree.cb +++ b/src/mainboard/newisys/khepri/devicetree.cb @@ -8,8 +8,8 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on subsystemid 0x17c2 0x0010 inherit chip northbridge/amd/amdk8 - device pci 18.0 on end # LDT 0 - device pci 18.0 on # LDT 1 + device pci 18.0 on end // LDT 0 + device pci 18.0 on // LDT 1 chip southbridge/amd/amd8131 device pci 0.0 on end device pci 0.1 on end @@ -25,41 +25,41 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.0 on chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # Com2 + device pnp 2e.3 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # CIR + device pnp 2e.6 off // CIR io 0x60 = 0x100 end - device pnp 2e.7 off # GAME_MIDI_GIPO1 + device pnp 2e.7 off // GAME_MIDI_GIPO1 io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.8 off end // GPIO2 + device pnp 2e.9 off end // GPIO3 + device pnp 2e.a off end // ACPI + device pnp 2e.b on // HW Monitor io 0x60 = 0x290 irq 0x70 = 5 end @@ -71,8 +71,8 @@ chip northbridge/amd/amdk8/root_complex device pci 1.5 on end device pci 1.6 on end end - end # LDT1 - device pci 18.0 on end # LDT2 + end // LDT1 + device pci 18.0 on end // LDT2 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end diff --git a/src/mainboard/nokia/ip530/devicetree.cb b/src/mainboard/nokia/ip530/devicetree.cb index 3cfbc8f..74dc9df 100644 --- a/src/mainboard/nokia/ip530/devicetree.cb +++ b/src/mainboard/nokia/ip530/devicetree.cb @@ -1,103 +1,103 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Marc Bertens mbertens@xs4all.nl -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +// +// This file is part of the coreboot project. +// +// Copyright (C) 2010 Marc Bertens mbertens@xs4all.nl +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +//
-chip northbridge/intel/i440bx # Northbridge - device lapic_cluster 0 on # (L)APIC cluster - chip cpu/intel/socket_PGA370 # CPU socket - device lapic 0 on end # Local APIC of the CPU +chip northbridge/intel/i440bx // Northbridge + device lapic_cluster 0 on // (L)APIC cluster + chip cpu/intel/socket_PGA370 // CPU socket + device lapic 0 on end // Local APIC of the CPU end end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 7.0 on # ISA bridge - chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37B787) - device pnp 3f0.0 off end # Floppy (No connector) - device pnp 3f0.3 off end # Parallel port (No connector) - device pnp 3f0.4 on # COM1 + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + device pci 1.0 on end // PCI/AGP bridge + chip southbridge/intel/i82371eb // Southbridge + device pci 7.0 on // ISA bridge + chip superio/smsc/smscsuperio // Super I/O (SMSC FDC37B787) + device pnp 3f0.0 off end // Floppy (No connector) + device pnp 3f0.3 off end // Parallel port (No connector) + device pnp 3f0.4 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 3f0.5 on # COM2 / IR + device pnp 3f0.5 on // COM2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 3f0.6 on # RTC + device pnp 3f0.6 on // RTC irq 0x63 = 0x72 end - device pnp 3f0.7 off # PS/2 keyboard / mouse (No connector) + device pnp 3f0.7 off // PS/2 keyboard / mouse (No connector) end - device pnp 3f0.8 on # AUX I/O - irq 0x24 = 0x84 # OSC + device pnp 3f0.8 on // AUX I/O + irq 0x24 = 0x84 // OSC
- irq 0xB2 = 0x0C # Soft power status 1 - irq 0xB3 = 0x05 # Soft power status 2 - irq 0xC0 = 0x03 # IRQ MUX control + irq 0xB2 = 0x0C // Soft power status 1 + irq 0xB3 = 0x05 // Soft power status 2 + irq 0xC0 = 0x03 // IRQ MUX control
- irq 0xC8 = 0x10 # GP50 = (I/O) output = Flashrom enable - irq 0xCA = 0x09 # GP52 = IRQ8 (output) - irq 0xCB = 0x01 # GP53 = nROMCS (output) - irq 0xCC = 0x11 # GP54 = (I/O) input - irq 0xF9 = 0x00 # read/write GP5x lines (0x1C) + irq 0xC8 = 0x10 // GP50 = (I/O) output = Flashrom enable + irq 0xCA = 0x09 // GP52 = IRQ8 (output) + irq 0xCB = 0x01 // GP53 = nROMCS (output) + irq 0xCC = 0x11 // GP54 = (I/O) input + irq 0xF9 = 0x00 // read/write GP5x lines (0x1C)
- irq 0xD0 = 0x08 # GP60 = IRQ1 - irq 0xD1 = 0x08 # GP61 = IRQ3 - irq 0xD2 = 0x08 # GP62 = IRQ4 - irq 0xD3 = 0x11 # GP63 = (I/O) input = JP901 on board - irq 0xD4 = 0x11 # GP64 = (I/O) input - irq 0xD5 = 0x11 # GP65 = (I/O) input - irq 0xD6 = 0x08 # GP66 = IRQ8 - irq 0xD7 = 0x11 # GP67 = (I/O) input - irq 0xFA = 0x00 # read/write GP6x lines (0x88) + irq 0xD0 = 0x08 // GP60 = IRQ1 + irq 0xD1 = 0x08 // GP61 = IRQ3 + irq 0xD2 = 0x08 // GP62 = IRQ4 + irq 0xD3 = 0x11 // GP63 = (I/O) input = JP901 on board + irq 0xD4 = 0x11 // GP64 = (I/O) input + irq 0xD5 = 0x11 // GP65 = (I/O) input + irq 0xD6 = 0x08 // GP66 = IRQ8 + irq 0xD7 = 0x11 // GP67 = (I/O) input + irq 0xFA = 0x00 // read/write GP6x lines (0x88)
- irq 0xE0 = 0x00 # GP10 (I/O) = output - irq 0xE1 = 0x01 # GP11 (I/O) = input - irq 0xE2 = 0x08 # GP12 = P17 - irq 0xE3 = 0x00 # GP13 (I/O) = output = LED fault on front, active low - irq 0xE4 = 0x00 # GP14 (I/O) = output - irq 0xE5 = 0x00 # GP15 (I/O) = output - irq 0xE6 = 0x01 # GP16 (I/O) = input = JP900 on board, low on short, high on open - irq 0xE7 = 0x00 # GP17 (I/O) = output = LED alert on front, active low - irq 0xF6 = 0xFF # read/write GP1x lines (0xCA) + irq 0xE0 = 0x00 // GP10 (I/O) = output + irq 0xE1 = 0x01 // GP11 (I/O) = input + irq 0xE2 = 0x08 // GP12 = P17 + irq 0xE3 = 0x00 // GP13 (I/O) = output = LED fault on front, active low + irq 0xE4 = 0x00 // GP14 (I/O) = output + irq 0xE5 = 0x00 // GP15 (I/O) = output + irq 0xE6 = 0x01 // GP16 (I/O) = input = JP900 on board, low on short, high on open + irq 0xE7 = 0x00 // GP17 (I/O) = output = LED alert on front, active low + irq 0xF6 = 0xFF // read/write GP1x lines (0xCA)
- irq 0xEF = 0x00 # GP_INT2 disable - irq 0xF0 = 0x00 # GP_INT1 disable - irq 0xF1 = 0x00 # WDT_UNITS - irq 0xF2 = 0x00 # WDT_VAL - irq 0xF3 = 0x00 # WDT_CFG - irq 0xF4 = 0x20 # WDT_CTRL (stop-cnt) + irq 0xEF = 0x00 // GP_INT2 disable + irq 0xF0 = 0x00 // GP_INT1 disable + irq 0xF1 = 0x00 // WDT_UNITS + irq 0xF2 = 0x00 // WDT_VAL + irq 0xF3 = 0x00 // WDT_CFG + irq 0xF4 = 0x20 // WDT_CTRL (stop-cnt) end - device pnp 3f0.a off # ACPI (No support yet) - # irq 0x60 = 0x0C - # irq 0x61 = 0x80 + device pnp 3f0.a off // ACPI (No support yet) + // irq 0x60 = 0x0C + // irq 0x61 = 0x80 end end end - device pci 7.1 on end # IDE - device pci 7.2 off end # USB (No connector) - device pci 7.3 off end # ACPI (No support yet) + device pci 7.1 on end // IDE + device pci 7.2 off end // USB (No connector) + device pci 7.3 off end // ACPI (No support yet) register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" - # Disable UDMA/33 for lower speed if your IDE device(s) don't support it. + // Disable UDMA/33 for lower speed if your IDE device(s) don't support it. register "ide0_drive0_udma33_enable" = "1" register "ide0_drive1_udma33_enable" = "1" register "ide1_drive0_udma33_enable" = "1" diff --git a/src/mainboard/nvidia/l1_2pvv/devicetree.cb b/src/mainboard/nvidia/l1_2pvv/devicetree.cb index 9a80710..5c30212 100644 --- a/src/mainboard/nvidia/l1_2pvv/devicetree.cb +++ b/src/mainboard/nvidia/l1_2pvv/devicetree.cb @@ -1,173 +1,173 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device lapic_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F # CPU socket - device lapic 0 on end # Local APIC of the CPU +chip northbridge/amd/amdk8/root_complex // Root complex + device lapic_cluster 0 on // (L)APIC cluster + chip cpu/amd/socket_F // CPU socket + device lapic 0 on end // Local APIC of the CPU end end - device pci_domain 0 on # PCI domain + device pci_domain 0 on // PCI domain subsystemid 0x1022 0x2b80 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627ehg # Super I/O - device pnp 2e.0 off # Floppy + chip northbridge/amd/amdk8 // Northbridge / RAM controller + device pci 18.0 on // Link 0 == LDT 0 + chip southbridge/nvidia/mcp55 // Southbridge + device pci 0.0 on end // HT + device pci 1.0 on // LPC + chip superio/winbond/w83627ehg // Super I/O + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel port + device pnp 2e.1 off // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.3 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # PS/2 keyboard & mouse + device pnp 2e.5 on // PS/2 keyboard & mouse io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.106 off # Serial flash interface (SFI) + device pnp 2e.106 off // Serial flash interface (SFI) io 0x60 = 0x100 end - device pnp 2e.007 off # GPIO 1 + device pnp 2e.007 off // GPIO 1 end - device pnp 2e.107 off # Game port + device pnp 2e.107 off // Game port io 0x60 = 0x220 end - device pnp 2e.207 off # MIDI + device pnp 2e.207 off // MIDI io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.307 off # GPIO 6 + device pnp 2e.307 off // GPIO 6 end - device pnp 2e.8 off # WDTO#, PLED + device pnp 2e.8 off // WDTO#, PLED end - device pnp 2e.009 off # GPIO 2 + device pnp 2e.009 off // GPIO 2 end - device pnp 2e.109 off # GPIO 3 + device pnp 2e.109 off // GPIO 3 end - device pnp 2e.209 off # GPIO 4 + device pnp 2e.209 off // GPIO 4 end - device pnp 2e.309 off # GPIO 5 + device pnp 2e.309 off // GPIO 5 end - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor + device pnp 2e.a off end // ACPI + device pnp 2e.b on // Hardware monitor io 0x60 = 0x290 irq 0x70 = 5 end end end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 + device pci 1.1 on // SM 0 + chip drivers/generic/generic // DIMM 0-0-0 device i2c 50 on end end - chip drivers/generic/generic # DIMM 0-0-1 + chip drivers/generic/generic // DIMM 0-0-1 device i2c 51 on end end - chip drivers/generic/generic # DIMM 0-1-0 + chip drivers/generic/generic // DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 + chip drivers/generic/generic // DIMM 0-1-1 device i2c 53 on end end - chip drivers/generic/generic # DIMM 1-0-0 + chip drivers/generic/generic // DIMM 1-0-0 device i2c 54 on end end - chip drivers/generic/generic # DIMM 1-0-1 + chip drivers/generic/generic // DIMM 1-0-1 device i2c 55 on end end - chip drivers/generic/generic # DIMM 1-1-0 + chip drivers/generic/generic // DIMM 1-1-0 device i2c 56 on end end - chip drivers/generic/generic # DIMM 1-1-1 + chip drivers/generic/generic // DIMM 1-1-1 device i2c 57 on end end end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM + device pci 1.1 on // SM 1 + // PCI device SMBus address will + // depend on addon PCI device, do + // we need to scan_smbus_bus? + // chip drivers/generic/generic # PCIXA slot 1 + // device i2c 50 on end + // end + // chip drivers/generic/generic # PCIXB slot 1 + // device i2c 51 on end + // end + // chip drivers/generic/generic # PCIXB slot 2 + // device i2c 52 on end + // end + // chip drivers/generic/generic # PCI slot 1 + // device i2c 53 on end + // end + // chip drivers/generic/generic # Master MCP55 PCI-E + // device i2c 54 on end + // end + // chip drivers/generic/generic # Slave MCP55 PCI-E + // device i2c 55 on end + // end + chip drivers/generic/generic // MAC EEPROM device i2c 51 on end end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on end # PCI - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 off end # PCI E 1 - device pci f.0 on end # PCI E 0 + device pci 2.0 on end // USB 1.1 + device pci 2.1 on end // USB 2 + device pci 4.0 on end // IDE + device pci 5.0 on end // SATA 0 + device pci 5.1 on end // SATA 1 + device pci 5.2 on end // SATA 2 + device pci 6.0 on end // PCI + device pci 6.1 on end // AZA + device pci 8.0 on end // NIC + device pci 9.0 on end // NIC + device pci a.0 on end // PCI E 5 + device pci b.0 off end // PCI E 4 + device pci c.0 off end // PCI E 3 + device pci d.0 on end // PCI E 2 + device pci e.0 off end // PCI E 1 + device pci f.0 on end // PCI E 0 register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 + // 1: SMBus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" end end - device pci 18.0 on end # Link 1 - device pci 18.0 on # Link 2 == LDT 2 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on end # LPC - device pci 1.1 on end # SM 0 - device pci 2.0 off end # USB 1.1 - device pci 2.1 off end # USB 2 - device pci 4.0 off end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 off end # PCI - device pci 6.1 off end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 + device pci 18.0 on end // Link 1 + device pci 18.0 on // Link 2 == LDT 2 + chip southbridge/nvidia/mcp55 // Southbridge + device pci 0.0 on end // HT + device pci 1.0 on end // LPC + device pci 1.1 on end // SM 0 + device pci 2.0 off end // USB 1.1 + device pci 2.1 off end // USB 2 + device pci 4.0 off end // IDE + device pci 5.0 on end // SATA 0 + device pci 5.1 on end // SATA 1 + device pci 5.2 on end // SATA 2 + device pci 6.0 off end // PCI + device pci 6.1 off end // AZA + device pci 8.0 on end // NIC + device pci 9.0 on end // NIC + device pci a.0 on end // PCI E 5 + device pci b.0 off end // PCI E 4 + device pci c.0 off end // PCI E 3 + device pci d.0 on end // PCI E 2 + device pci e.0 on end // PCI E 1 + device pci f.0 on end // PCI E 0 register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 + // 1: SMBus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" end @@ -177,16 +177,16 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 18.3 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end # chip name - # device pnp 0.1 on end # pci_regs_all - # device pnp 0.2 on end # mem - # device pnp 0.3 off end # cpuid - # device pnp 0.4 on end # smbus_regs_all - # device pnp 0.5 off end # dual core msr - # device pnp 0.6 off end # cache size - # device pnp 0.7 off end # tsc - # device pnp 0.8 off end # io - # device pnp 0.9 off end # io - # end + // chip drivers/generic/debug + // device pnp 0.0 off end # chip name + // device pnp 0.1 on end # pci_regs_all + // device pnp 0.2 on end # mem + // device pnp 0.3 off end # cpuid + // device pnp 0.4 on end # smbus_regs_all + // device pnp 0.5 off end # dual core msr + // device pnp 0.6 off end # cache size + // device pnp 0.7 off end # tsc + // device pnp 0.8 off end # io + // device pnp 0.9 off end # io + // end end diff --git a/src/mainboard/pcengines/alix1c/devicetree.cb b/src/mainboard/pcengines/alix1c/devicetree.cb index 4af91ca..90c568c 100644 --- a/src/mainboard/pcengines/alix1c/devicetree.cb +++ b/src/mainboard/pcengines/alix1c/devicetree.cb @@ -3,79 +3,79 @@ chip northbridge/amd/lx device pci 1.0 on end device pci 1.1 on end chip southbridge/amd/cs5536 - # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK - # SIRQ Mode = Active(Quiet) mode. Save power.... - # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK - # How to get these? Boot linux and do this: - # rdmsr 0x51400025 + // IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + // SIRQ Mode = Active(Quiet) mode. Save power.... + // Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK + // How to get these? Boot linux and do this: + // rdmsr 0x51400025 register "lpc_serirq_enable" = "0x0000105a" - # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits + // rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits register "lpc_serirq_polarity" = "0x0000EFA5" - # mode is high 10 bits (determined from code) + // mode is high 10 bits (determined from code) register "lpc_serirq_mode" = "1" - # Don't yet know how to find this. + // Don't yet know how to find this. register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "0" #0: host, 1:device - register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "enable_ide_nand_flash" = "0" // 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" //0: host, 1:device + register "enable_USBP4_overcurrent" = "0" //0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) register "com1_enable" = "0" register "com1_address" = "0x3F8" register "com1_irq" = "4" register "com2_enable" = "0" register "com2_address" = "0x2F8" register "com2_irq" = "3" - register "unwanted_vpci[0]" = "0" # End of list has a zero - device pci f.0 on # ISA Bridge + register "unwanted_vpci[0]" = "0" // End of list has a zero + device pci f.0 on // ISA Bridge chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Parallel Port + device pnp 2e.1 on // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # Com2 + device pnp 2e.3 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # CIR + device pnp 2e.6 off // CIR io 0x60 = 0x100 end - device pnp 2e.7 off # GAME_MIDI_GIPO1 + device pnp 2e.7 off // GAME_MIDI_GIPO1 io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 on end # GPIO2 - device pnp 2e.9 on end # GPIO3 - device pnp 2e.a on end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.8 on end // GPIO2 + device pnp 2e.9 on end // GPIO3 + device pnp 2e.a on end // ACPI + device pnp 2e.b on // HW Monitor io 0x60 = 0x290 irq 0x70 = 5 end end end - device pci f.1 on end # Flash controller - device pci f.2 on end # IDE controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI + device pci f.1 on end // Flash controller + device pci f.2 on end // IDE controller + device pci f.3 on end // Audio + device pci f.4 on end // OHCI + device pci f.5 on end // EHCI end end
- # APIC cluster is late CPU init. + // APIC cluster is late CPU init. device lapic_cluster 0 on chip cpu/amd/model_lx device lapic 0 on end diff --git a/src/mainboard/pcengines/alix2d/devicetree.cb b/src/mainboard/pcengines/alix2d/devicetree.cb index edcbc06..c28b4e2 100644 --- a/src/mainboard/pcengines/alix2d/devicetree.cb +++ b/src/mainboard/pcengines/alix2d/devicetree.cb @@ -3,39 +3,39 @@ chip northbridge/amd/lx device pci 1.0 on end device pci 1.1 on end chip southbridge/amd/cs5536 - # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK - # SIRQ Mode = Active(Quiet) mode. Save power.... - # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK - # How to get these? Boot linux and do this: - # rdmsr 0x51400025 + // IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + // SIRQ Mode = Active(Quiet) mode. Save power.... + // Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK + // How to get these? Boot linux and do this: + // rdmsr 0x51400025 register "lpc_serirq_enable" = "0x00001002" - # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits + // rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits register "lpc_serirq_polarity" = "0x0000EFFD" - # mode is high 10 bits (determined from code) + // mode is high 10 bits (determined from code) register "lpc_serirq_mode" = "1" - # Don't yet know how to find this. + // Don't yet know how to find this. register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "0" #0: host, 1:device - register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "enable_ide_nand_flash" = "0" // 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" //0: host, 1:device + register "enable_USBP4_overcurrent" = "0" //0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) register "com1_enable" = "1" register "com1_address" = "0x3F8" register "com1_irq" = "4" - register "com2_enable" = "1" # Wired on Alix.2D13 only + register "com2_enable" = "1" // Wired on Alix.2D13 only register "com2_address" = "0x2F8" register "com2_irq" = "3" - register "unwanted_vpci[0]" = "0x80000900" # Disable VGA controller (not wired) - register "unwanted_vpci[1]" = "0x80007B00" # Disable AC97 controller (not wired) - register "unwanted_vpci[2]" = "0" # End of list has a zero - device pci f.0 on end # ISA Bridge - device pci f.1 on end # Flash controller - device pci f.2 on end # IDE controller - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI + register "unwanted_vpci[0]" = "0x80000900" // Disable VGA controller (not wired) + register "unwanted_vpci[1]" = "0x80007B00" // Disable AC97 controller (not wired) + register "unwanted_vpci[2]" = "0" // End of list has a zero + device pci f.0 on end // ISA Bridge + device pci f.1 on end // Flash controller + device pci f.2 on end // IDE controller + device pci f.4 on end // OHCI + device pci f.5 on end // EHCI end end
- # APIC cluster is late CPU init. + // APIC cluster is late CPU init. device lapic_cluster 0 on chip cpu/amd/model_lx device lapic 0 on end diff --git a/src/mainboard/rca/rm4100/devicetree.cb b/src/mainboard/rca/rm4100/devicetree.cb index 5c22eaa..bf56ecc 100644 --- a/src/mainboard/rca/rm4100/devicetree.cb +++ b/src/mainboard/rca/rm4100/devicetree.cb @@ -1,13 +1,13 @@ -chip northbridge/intel/i82830 # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/socket_mFCBGA479 # Mobile Celeron Micro-FCBGA Socket 479 - device lapic 0 on end # APIC +chip northbridge/intel/i82830 // Northbridge + device lapic_cluster 0 on // APIC cluster + chip cpu/intel/socket_mFCBGA479 // Mobile Celeron Micro-FCBGA Socket 479 + device lapic 0 on end // APIC end end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 2.0 on end # VGA (Intel 82830 CGC) - chip southbridge/intel/i82801dx # Southbridge + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + device pci 2.0 on end // VGA (Intel 82830 CGC) + chip southbridge/intel/i82801dx // Southbridge register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x06" register "pirqc_routing" = "0x07" @@ -20,48 +20,48 @@ chip northbridge/intel/i82830 # Northbridge register "ide0_enable" = "1" register "ide1_enable" = "1"
- device pci 1d.0 on end # USB UHCI Controller #1 - device pci 1d.1 on end # USB UHCI Controller #2 - device pci 1d.2 on end # USB UHCI Controller #3 - device pci 1d.7 on end # USB2 EHCI Controller - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA/LPC bridge - chip superio/smsc/smscsuperio # Super I/O - device pnp 2e.0 off # Floppy + device pci 1d.0 on end // USB UHCI Controller #1 + device pci 1d.1 on end // USB UHCI Controller #2 + device pci 1d.2 on end // USB UHCI Controller #3 + device pci 1d.7 on end // USB2 EHCI Controller + device pci 1e.0 on end // PCI bridge + device pci 1f.0 on // ISA/LPC bridge + chip superio/smsc/smscsuperio // Super I/O + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.3 on # Parallel port + device pnp 2e.3 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 4 end - device pnp 2e.4 on # Com1 + device pnp 2e.4 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.5 on # Com2 / IR + device pnp 2e.5 on // Com2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.7 on # PS/2 keyboard/mouse + device pnp 2e.7 on // PS/2 keyboard/mouse io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # Keyboard interrupt - irq 0x72 = 12 # Mouse interrupt + irq 0x70 = 1 // Keyboard interrupt + irq 0x72 = 12 // Mouse interrupt end - device pnp 2e.9 off end # Game port - device pnp 2e.a on # PME + device pnp 2e.9 off end // Game port + device pnp 2e.a on // PME io 0x60 = 0x800 end - device pnp 2e.b off end # MPU-401 + device pnp 2e.b off end // MPU-401 end end - device pci 1f.1 on end # IDE - device pci 1f.3 on end # SMBus - device pci 1f.5 on end # AC'97 audio - device pci 1f.6 on end # AC'97 modem + device pci 1f.1 on end // IDE + device pci 1f.3 on end // SMBus + device pci 1f.5 on end // AC'97 audio + device pci 1f.6 on end // AC'97 modem end end end diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 1bd0d14..fd3d922 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -1,23 +1,23 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2009 coresystems GmbH -## -## This program is free software; you can redistribute it and/or -## modify it under the terms of the GNU General Public License as -## published by the Free Software Foundation; version 2 of -## the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -## MA 02110-1301 USA -## +// +// This file is part of the coreboot project. +// +// Copyright (C) 2007-2009 coresystems GmbH +// +// This program is free software; you can redistribute it and/or +// modify it under the terms of the GNU General Public License as +// published by the Free Software Foundation; version 2 of +// the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +// MA 02110-1301 USA +//
chip northbridge/intel/i945
@@ -29,11 +29,11 @@ chip northbridge/intel/i945
device pci_domain 0 on subsystemid 0x4352 0x6886 inherit - device pci 00.0 on end # host bridge - # auto detection: - #device pci 01.0 off end # i945 PCIe root port - #device pci 02.0 on end # vga controller - #device pci 02.1 on end # display controller + device pci 00.0 on end // host bridge + // auto detection: + //device pci 01.0 off end # i945 PCIe root port + //device pci 02.0 on end # vga controller + //device pci 02.1 on end # display controller
chip southbridge/intel/i82801gx register "pirqa_routing" = "0x0b" @@ -45,10 +45,10 @@ chip northbridge/intel/i945 register "pirqg_routing" = "0x0b" register "pirqh_routing" = "0x0b"
- # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) + // GPI routing + // 0 No effect (default) + // 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + // 2 SCI (if corresponding GPIO_EN bit is also set) register "gpi13_routing" = "2" register "gpi8_routing" = "1" register "gpi7_routing" = "2" @@ -59,62 +59,62 @@ chip northbridge/intel/i945 register "ide_enable_secondary" = "0x0" register "sata_ahci" = "0x0"
- device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe - device pci 1c.1 on end # PCIe - device pci 1c.2 on end # PCIe - #device pci 1c.3 off end # PCIe port 4 - #device pci 1c.4 off end # PCIe port 5 - #device pci 1c.5 off end # PCIe port 6 - device pci 1d.0 on end # USB UHCI - device pci 1d.1 on end # USB UHCI - device pci 1d.2 on end # USB UHCI - device pci 1d.3 on end # USB UHCI - device pci 1d.7 on end # USB2 EHCI + device pci 1b.0 on end // High Definition Audio + device pci 1c.0 on end // PCIe + device pci 1c.1 on end // PCIe + device pci 1c.2 on end // PCIe + //device pci 1c.3 off end # PCIe port 4 + //device pci 1c.4 off end # PCIe port 5 + //device pci 1c.5 off end # PCIe port 6 + device pci 1d.0 on end // USB UHCI + device pci 1d.1 on end // USB UHCI + device pci 1d.2 on end // USB UHCI + device pci 1d.3 on end // USB UHCI + device pci 1d.7 on end // USB2 EHCI device pci 1e.0 on chip southbridge/ti/pci7420 register "smartcard_enabled" = "0x0" device pci 3.0 on end device pci 3.1 on end device pci 3.2 on end - device pci 3.3 off end # smartcard + device pci 3.3 off end // smartcard end - end # PCI bridge - #device pci 1e.2 off end # AC'97 Audio - #device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge + end // PCI bridge + //device pci 1e.2 off end # AC'97 Audio + //device pci 1e.3 off end # AC'97 Modem + device pci 1f.0 on // LPC bridge chip superio/smsc/lpc47n227 - device pnp 2e.1 on # Parallel port + device pnp 2e.1 on // Parallel port io 0x60 = 0x378 irq 0x70 = 5 end - device pnp 2e.2 on # COM1 + device pnp 2e.2 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # COM2 + device pnp 2e.3 on // COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 off # Keyboard+Mouse - # io 0x60 = 0x60 - # io 0x62 = 0x64 - # irq 0x70 = 1 - # irq 0x72 = 12 + device pnp 2e.5 off // Keyboard+Mouse + // io 0x60 = 0x60 + // io 0x62 = 0x64 + // irq 0x70 = 1 + // irq 0x72 = 12 end end chip superio/renesas/m3885x - device pnp ff.1 on # dummy address + device pnp ff.1 on // dummy address end end chip ec/acpi end
end - #device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - #device pci 1f.4 off end # Realtek ID Codec + //device pci 1f.1 off end # IDE + device pci 1f.2 on end // SATA + device pci 1f.3 on end // SMBus + //device pci 1f.4 off end # Realtek ID Codec end end end diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb b/src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb index 03451e2..3b4cac0 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb +++ b/src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb @@ -1,69 +1,69 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann uwe@hermann-uwe.de -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +// +// This file is part of the coreboot project. +// +// Copyright (C) 2009 Uwe Hermann uwe@hermann-uwe.de +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +//
-chip northbridge/intel/i440bx # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/slot_1 # CPU - device lapic 0 on end # APIC +chip northbridge/intel/i440bx // Northbridge + device lapic_cluster 0 on // APIC cluster + chip cpu/intel/slot_1 // CPU + device lapic 0 on end // APIC end end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 7.0 on # ISA bridge - chip superio/ite/it8671f # Super I/O - device pnp 370.0 on # Floppy + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + device pci 1.0 on end // PCI/AGP bridge + chip southbridge/intel/i82371eb // Southbridge + device pci 7.0 on // ISA bridge + chip superio/ite/it8671f // Super I/O + device pnp 370.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 370.1 on # COM1 + device pnp 370.1 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 370.2 on # COM2 + device pnp 370.2 on // COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 370.3 on # Parallel port + device pnp 370.3 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 370.5 on # PS/2 keyboard + device pnp 370.5 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 370.6 on # PS/2 mouse + device pnp 370.6 on // PS/2 mouse irq 0x70 = 12 end end end - device pci 7.1 on end # IDE - device pci 7.2 on end # USB - device pci 7.3 on end # ACPI + device pci 7.1 on end // IDE + device pci 7.2 on end // USB + device pci 7.3 on end // ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. + // Enable UDMA/33 for higher speed if your IDE device(s) support it. register "ide0_drive0_udma33_enable" = "0" register "ide0_drive1_udma33_enable" = "0" register "ide1_drive0_udma33_enable" = "0" diff --git a/src/mainboard/sunw/ultra40/devicetree.cb b/src/mainboard/sunw/ultra40/devicetree.cb index f355200..1976462 100644 --- a/src/mainboard/sunw/ultra40/devicetree.cb +++ b/src/mainboard/sunw/ultra40/devicetree.cb @@ -1,36 +1,36 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device lapic_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_940 # CPU socket - device lapic 0 on end # Local APIC of the CPU +chip northbridge/amd/amdk8/root_complex // Root complex + device lapic_cluster 0 on // (L)APIC cluster + chip cpu/amd/socket_940 // CPU socket + device lapic 0 on end // Local APIC of the CPU end end - device pci_domain 0 on # PCI domain + device pci_domain 0 on // PCI domain subsystemid 0x108e 0x0040 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller + chip northbridge/amd/amdk8 // Northbridge / RAM controller device pci 18.0 on end - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/smsc/lpc47m10x # Super I/O - device pnp 2e.0 off # Floppy + device pci 18.0 on // Link 0 == LDT 0 + chip southbridge/nvidia/ck804 // Southbridge + device pci 0.0 on end // HT + device pci 1.0 on // LPC + chip superio/smsc/lpc47m10x // Super I/O + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.3 off # Parallel port + device pnp 2e.3 off // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.4 on # Com1 + device pnp 2e.4 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.5 off # Com2 + device pnp 2e.5 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.7 off # PS/2 keyboard + device pnp 2e.7 off // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 @@ -38,106 +38,106 @@ chip northbridge/amd/amdk8/root_complex # Root complex end end end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 + device pci 1.1 on // SM 0 + chip drivers/generic/generic // DIMM 0-0-0 device i2c 50 on end end - chip drivers/generic/generic # DIMM 0-0-1 + chip drivers/generic/generic // DIMM 0-0-1 device i2c 51 on end end - chip drivers/generic/generic # DIMM 0-1-0 + chip drivers/generic/generic // DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 + chip drivers/generic/generic // DIMM 0-1-1 device i2c 53 on end end - chip drivers/generic/generic # DIMM 1-0-0 + chip drivers/generic/generic // DIMM 1-0-0 device i2c 54 on end end - chip drivers/generic/generic # DIMM 1-0-1 + chip drivers/generic/generic // DIMM 1-0-1 device i2c 55 on end end - chip drivers/generic/generic # DIMM 1-1-0 + chip drivers/generic/generic // DIMM 1-1-0 device i2c 56 on end end - chip drivers/generic/generic # DIMM 1-1-1 + chip drivers/generic/generic // DIMM 1-1-1 device i2c 57 on end end end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master CK804 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave CK804 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM + device pci 1.1 on // SM 1 + // PCI device SMBus address will + // depend on addon PCI device, do + // we need to scan_smbus_bus? + // chip drivers/generic/generic # PCIXA slot 1 + // device i2c 50 on end + // end + // chip drivers/generic/generic # PCIXB slot 1 + // device i2c 51 on end + // end + // chip drivers/generic/generic # PCIXB slot 2 + // device i2c 52 on end + // end + // chip drivers/generic/generic # PCI slot 1 + // device i2c 53 on end + // end + // chip drivers/generic/generic # Master CK804 PCI-E + // device i2c 54 on end + // end + // chip drivers/generic/generic # Slave CK804 PCI-E + // device i2c 55 on end + // end + chip drivers/generic/generic // MAC EEPROM device i2c 51 on end end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # ACI - device pci 4.1 off end # MCI - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on end # PCI - device pci a.0 on end # NIC - device pci b.0 off end # PCI E 3 - device pci c.0 off end # PCI E 2 - device pci d.0 off end # PCI E 1 - device pci e.0 on end # PCI E 0 + device pci 2.0 on end // USB 1.1 + device pci 2.1 on end // USB 2 + device pci 4.0 on end // ACI + device pci 4.1 off end // MCI + device pci 6.0 on end // IDE + device pci 7.0 on end // SATA 1 + device pci 8.0 on end // SATA 0 + device pci 9.0 on end // PCI + device pci a.0 on end // NIC + device pci b.0 off end // PCI E 3 + device pci c.0 off end // PCI E 2 + device pci d.0 off end // PCI E 1 + device pci e.0 on end // PCI E 0 register "ide0_enable" = "1" register "ide1_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 + // 1: SMBus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" end end - device pci 18.0 on end # Link 2 + device pci 18.0 on end // Link 2 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 19.0 on end # Link 0 - device pci 19.0 on # Link 1 == LDT 1 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on end # LPC - device pci 1.1 off end # SM - device pci 2.0 off end # USB 1.1 - device pci 2.1 off end # USB 2 - device pci 4.0 off end # ACI - device pci 4.1 off end # MCI - device pci 6.0 off end # IDE - device pci 7.0 off end # SATA 1 - device pci 8.0 off end # SATA 0 - device pci 9.0 off end # PCI - device pci a.0 on end # NIC - device pci b.0 off end # PCI E 3 - device pci c.0 off end # PCI E 2 - device pci d.0 off end # PCI E 1 - device pci e.0 on end # PCI E 0 - # 1: SMBus under 2e.8, 2: SM0 3: SM1 + chip northbridge/amd/amdk8 // Northbridge / RAM controller + device pci 19.0 on end // Link 0 + device pci 19.0 on // Link 1 == LDT 1 + chip southbridge/nvidia/ck804 // Southbridge + device pci 0.0 on end // HT + device pci 1.0 on end // LPC + device pci 1.1 off end // SM + device pci 2.0 off end // USB 1.1 + device pci 2.1 off end // USB 2 + device pci 4.0 off end // ACI + device pci 4.1 off end // MCI + device pci 6.0 off end // IDE + device pci 7.0 off end // SATA 1 + device pci 8.0 off end // SATA 0 + device pci 9.0 off end // PCI + device pci a.0 on end // NIC + device pci b.0 off end // PCI E 3 + device pci c.0 off end // PCI E 2 + device pci d.0 off end // PCI E 1 + device pci e.0 on end // PCI E 0 + // 1: SMBus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" end diff --git a/src/mainboard/supermicro/h8dme/devicetree.cb b/src/mainboard/supermicro/h8dme/devicetree.cb index 73a43e8..f0179e9 100644 --- a/src/mainboard/supermicro/h8dme/devicetree.cb +++ b/src/mainboard/supermicro/h8dme/devicetree.cb @@ -1,119 +1,119 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device lapic_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F # CPU socket - device lapic 0 on end # Local APIC of the CPU +chip northbridge/amd/amdk8/root_complex // Root complex + device lapic_cluster 0 on // (L)APIC cluster + chip cpu/amd/socket_F // CPU socket + device lapic 0 on end // Local APIC of the CPU end end - device pci_domain 0 on # PCI domain + device pci_domain 0 on // PCI domain subsystemid 0x15d9 0x1511 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller + chip northbridge/amd/amdk8 // Northbridge / RAM controller device pci 18.0 on end device pci 18.0 on end - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy + device pci 18.0 on // Link 0 == LDT 0 + chip southbridge/nvidia/mcp55 // Southbridge + device pci 0.0 on end // HT + device pci 1.0 on // LPC + chip superio/winbond/w83627hf // Super I/O + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel port + device pnp 2e.1 off // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.3 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # PS/2 keyboard + device pnp 2e.5 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # SFI + device pnp 2e.6 off // SFI io 0x62 = 0x100 end - device pnp 2e.7 off # GPIO, game port, MIDI + device pnp 2e.7 off // GPIO, game port, MIDI io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor + device pnp 2e.8 off end // WDTO PLED + device pnp 2e.9 off end // GPIO SUSLED + device pnp 2e.a off end // ACPI + device pnp 2e.b on // Hardware monitor io 0x60 = 0x290 irq 0x70 = 5 end end end - device pci 1.1 on # SM 0 + device pci 1.1 on // SM 0 chip drivers/i2c/i2cmux2 device i2c 48 off end device i2c 49 off end end end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM + device pci 1.1 on // SM 1 + // PCI device SMBus address will + // depend on addon PCI device, do + // we need to scan_smbus_bus? + // chip drivers/generic/generic # PCIXA slot 1 + // device i2c 50 on end + // end + // chip drivers/generic/generic # PCIXB slot 1 + // device i2c 51 on end + // end + // chip drivers/generic/generic # PCIXB slot 2 + // device i2c 52 on end + // end + // chip drivers/generic/generic # PCI slot 1 + // device i2c 53 on end + // end + // chip drivers/generic/generic # Master MCP55 PCI-E + // device i2c 54 on end + // end + // chip drivers/generic/generic # Slave MCP55 PCI-E + // device i2c 55 on end + // end + chip drivers/generic/generic // MAC EEPROM device i2c 51 on end end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # PCI + device pci 2.0 on end // USB 1.1 + device pci 2.1 on end // USB 2 + device pci 4.0 on end // IDE + device pci 5.0 on end // SATA 0 + device pci 5.1 on end // SATA 1 + device pci 5.2 on end // SATA 2 + device pci 6.0 on // PCI device pci 6.0 on end end - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on # PCI E 5 - device pci 0.0 on end # NEC PCI-X - device pci 0.1 on # NEC PCI-X - device pci 4.0 on end # SCSI - device pci 4.1 on end # SCSI + device pci 6.1 on end // AZA + device pci 8.0 on end // NIC + device pci 9.0 on end // NIC + device pci a.0 on // PCI E 5 + device pci 0.0 on end // NEC PCI-X + device pci 0.1 on // NEC PCI-X + device pci 4.0 on end // SCSI + device pci 4.1 on end // SCSI end end - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 + device pci b.0 on end // PCI E 4 + device pci c.0 on end // PCI E 3 + device pci d.0 on end // PCI E 2 + device pci e.0 on end // PCI E 1 + device pci f.0 on end // PCI E 0 register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 + // 1: SMBus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" end @@ -123,16 +123,16 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 18.3 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end # chip name - # device pnp 0.1 on end # pci_regs_all - # device pnp 0.2 off end # mem - # device pnp 0.3 off end # cpuid - # device pnp 0.4 on end # smbus_regs_all - # device pnp 0.5 off end # dual core msr - # device pnp 0.6 off end # cache size - # device pnp 0.7 off end # tsc - # device pnp 0.8 off end # io - # device pnp 0.9 on end # io - # end + // chip drivers/generic/debug + // device pnp 0.0 off end # chip name + // device pnp 0.1 on end # pci_regs_all + // device pnp 0.2 off end # mem + // device pnp 0.3 off end # cpuid + // device pnp 0.4 on end # smbus_regs_all + // device pnp 0.5 off end # dual core msr + // device pnp 0.6 off end # cache size + // device pnp 0.7 off end # tsc + // device pnp 0.8 off end # io + // device pnp 0.9 on end # io + // end end diff --git a/src/mainboard/supermicro/h8dmr/devicetree.cb b/src/mainboard/supermicro/h8dmr/devicetree.cb index 6c96ac0..d8d88fc 100644 --- a/src/mainboard/supermicro/h8dmr/devicetree.cb +++ b/src/mainboard/supermicro/h8dmr/devicetree.cb @@ -1,139 +1,139 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device lapic_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F # CPU socket - device lapic 0 on end # Local APIC of the CPU +chip northbridge/amd/amdk8/root_complex // Root complex + device lapic_cluster 0 on // (L)APIC cluster + chip cpu/amd/socket_F // CPU socket + device lapic 0 on end // Local APIC of the CPU end end - device pci_domain 0 on # PCI domain + device pci_domain 0 on // PCI domain subsystemid 0x15d9 0x1511 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller + chip northbridge/amd/amdk8 // Northbridge / RAM controller device pci 18.0 on end device pci 18.0 on end - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy + device pci 18.0 on // Link 0 == LDT 0 + chip southbridge/nvidia/mcp55 // Southbridge + device pci 0.0 on end // HT + device pci 1.0 on // LPC + chip superio/winbond/w83627hf // Super I/O + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel port + device pnp 2e.1 off // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.3 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # PS/2 keyboard + device pnp 2e.5 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # SFI + device pnp 2e.6 off // SFI io 0x62 = 0x100 end - device pnp 2e.7 off # GPIO, game port, MIDI + device pnp 2e.7 off // GPIO, game port, MIDI io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor + device pnp 2e.8 off end // WDTO PLED + device pnp 2e.9 off end // GPIO SUSLED + device pnp 2e.a off end // ACPI + device pnp 2e.b on // Hardware monitor io 0x60 = 0x290 irq 0x70 = 5 end end end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 + device pci 1.1 on // SM 0 + chip drivers/generic/generic // DIMM 0-0-0 device i2c 50 on end end - chip drivers/generic/generic # DIMM 0-0-1 + chip drivers/generic/generic // DIMM 0-0-1 device i2c 51 on end end - chip drivers/generic/generic # DIMM 0-1-0 + chip drivers/generic/generic // DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 + chip drivers/generic/generic // DIMM 0-1-1 device i2c 53 on end end - chip drivers/generic/generic # DIMM 1-0-0 + chip drivers/generic/generic // DIMM 1-0-0 device i2c 54 on end end - chip drivers/generic/generic # DIMM 1-0-1 + chip drivers/generic/generic // DIMM 1-0-1 device i2c 55 on end end - chip drivers/generic/generic # DIMM 1-1-0 + chip drivers/generic/generic // DIMM 1-1-0 device i2c 56 on end end - chip drivers/generic/generic # DIMM 1-1-1 + chip drivers/generic/generic // DIMM 1-1-1 device i2c 57 on end end end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM + device pci 1.1 on // SM 1 + // PCI device SMBus address will + // depend on addon PCI device, do + // we need to scan_smbus_bus? + // chip drivers/generic/generic # PCIXA slot 1 + // device i2c 50 on end + // end + // chip drivers/generic/generic # PCIXB slot 1 + // device i2c 51 on end + // end + // chip drivers/generic/generic # PCIXB slot 2 + // device i2c 52 on end + // end + // chip drivers/generic/generic # PCI slot 1 + // device i2c 53 on end + // end + // chip drivers/generic/generic # Master MCP55 PCI-E + // device i2c 54 on end + // end + // chip drivers/generic/generic # Slave MCP55 PCI-E + // device i2c 55 on end + // end + chip drivers/generic/generic // MAC EEPROM device i2c 51 on end end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # PCI + device pci 2.0 on end // USB 1.1 + device pci 2.1 on end // USB 2 + device pci 4.0 on end // IDE + device pci 5.0 on end // SATA 0 + device pci 5.1 on end // SATA 1 + device pci 5.2 on end // SATA 2 + device pci 6.0 on // PCI device pci 6.0 on end end - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on # PCI E 5 - device pci 0.0 on end # NEC PCI-X - device pci 0.1 on # NEC PCI-X - device pci 4.0 on end # SCSI - device pci 4.1 on end # SCSI + device pci 6.1 on end // AZA + device pci 8.0 on end // NIC + device pci 9.0 on end // NIC + device pci a.0 on // PCI E 5 + device pci 0.0 on end // NEC PCI-X + device pci 0.1 on // NEC PCI-X + device pci 4.0 on end // SCSI + device pci 4.1 on end // SCSI end end - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 + device pci b.0 on end // PCI E 4 + device pci c.0 on end // PCI E 3 + device pci d.0 on end // PCI E 2 + device pci e.0 on end // PCI E 1 + device pci f.0 on end // PCI E 0 register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 + // 1: SMBus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" end @@ -143,16 +143,16 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 18.3 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end # chip name - # device pnp 0.1 on end # pci_regs_all - # device pnp 0.2 off end # mem - # device pnp 0.3 off end # cpuid - # device pnp 0.4 on end # smbus_regs_all - # device pnp 0.5 off end # dual core msr - # device pnp 0.6 off end # cache size - # device pnp 0.7 off end # tsc - # device pnp 0.8 off end # io - # device pnp 0.9 on end # io - # end + // chip drivers/generic/debug + // device pnp 0.0 off end # chip name + // device pnp 0.1 on end # pci_regs_all + // device pnp 0.2 off end # mem + // device pnp 0.3 off end # cpuid + // device pnp 0.4 on end # smbus_regs_all + // device pnp 0.5 off end # dual core msr + // device pnp 0.6 off end # cache size + // device pnp 0.7 off end # tsc + // device pnp 0.8 off end # io + // device pnp 0.9 on end # io + // end end diff --git a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb index 6c4443f..3abe776 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb @@ -1,139 +1,139 @@ -chip northbridge/amd/amdfam10/root_complex # Root complex - device lapic_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F_1207 # CPU socket - device lapic 0 on end # Local APIC of the CPU +chip northbridge/amd/amdfam10/root_complex // Root complex + device lapic_cluster 0 on // (L)APIC cluster + chip cpu/amd/socket_F_1207 // CPU socket + device lapic 0 on end // Local APIC of the CPU end end - device pci_domain 0 on # PCI domain + device pci_domain 0 on // PCI domain subsystemid 0x15d9 0x1511 inherit - chip northbridge/amd/amdfam10 # Northbridge / RAM controller + chip northbridge/amd/amdfam10 // Northbridge / RAM controller device pci 18.0 on end device pci 18.0 on end - device pci 18.0 on # SB on link 2.0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy + device pci 18.0 on // SB on link 2.0 + chip southbridge/nvidia/mcp55 // Southbridge + device pci 0.0 on end // HT + device pci 1.0 on // LPC + chip superio/winbond/w83627hf // Super I/O + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel port + device pnp 2e.1 off // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # Com2 + device pnp 2e.3 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # PS/2 keyboard + device pnp 2e.5 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # SFI + device pnp 2e.6 off // SFI io 0x62 = 0x100 end - device pnp 2e.7 off # GPIO, game port, MIDI + device pnp 2e.7 off // GPIO, game port, MIDI io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor + device pnp 2e.8 off end // WDTO PLED + device pnp 2e.9 off end // GPIO SUSLED + device pnp 2e.a off end // ACPI + device pnp 2e.b on // Hardware monitor io 0x60 = 0x290 irq 0x70 = 5 end end end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 + device pci 1.1 on // SM 0 + chip drivers/generic/generic // DIMM 0-0-0 device i2c 50 on end end - chip drivers/generic/generic # DIMM 0-0-1 + chip drivers/generic/generic // DIMM 0-0-1 device i2c 51 on end end - chip drivers/generic/generic # DIMM 0-1-0 + chip drivers/generic/generic // DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 + chip drivers/generic/generic // DIMM 0-1-1 device i2c 53 on end end - chip drivers/generic/generic # DIMM 1-0-0 + chip drivers/generic/generic // DIMM 1-0-0 device i2c 54 on end end - chip drivers/generic/generic # DIMM 1-0-1 + chip drivers/generic/generic // DIMM 1-0-1 device i2c 55 on end end - chip drivers/generic/generic # DIMM 1-1-0 + chip drivers/generic/generic // DIMM 1-1-0 device i2c 56 on end end - chip drivers/generic/generic # DIMM 1-1-1 + chip drivers/generic/generic // DIMM 1-1-1 device i2c 57 on end end end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM + device pci 1.1 on // SM 1 + // PCI device SMBus address will + // depend on addon PCI device, do + // we need to scan_smbus_bus? + // chip drivers/generic/generic # PCIXA slot 1 + // device i2c 50 on end + // end + // chip drivers/generic/generic # PCIXB slot 1 + // device i2c 51 on end + // end + // chip drivers/generic/generic # PCIXB slot 2 + // device i2c 52 on end + // end + // chip drivers/generic/generic # PCI slot 1 + // device i2c 53 on end + // end + // chip drivers/generic/generic # Master MCP55 PCI-E + // device i2c 54 on end + // end + // chip drivers/generic/generic # Slave MCP55 PCI-E + // device i2c 55 on end + // end + chip drivers/generic/generic // MAC EEPROM device i2c 51 on end end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # PCI + device pci 2.0 on end // USB 1.1 + device pci 2.1 on end // USB 2 + device pci 4.0 on end // IDE + device pci 5.0 on end // SATA 0 + device pci 5.1 on end // SATA 1 + device pci 5.2 on end // SATA 2 + device pci 6.0 on // PCI device pci 6.0 on end end - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on # PCI E 5 - device pci 0.0 on end # NEC PCI-X - device pci 0.1 on # NEC PCI-X - device pci 4.0 on end # SCSI - device pci 4.1 on end # SCSI + device pci 6.1 on end // AZA + device pci 8.0 on end // NIC + device pci 9.0 on end // NIC + device pci a.0 on // PCI E 5 + device pci 0.0 on end // NEC PCI-X + device pci 0.1 on // NEC PCI-X + device pci 4.0 on end // SCSI + device pci 4.1 on end // SCSI end end - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 + device pci b.0 on end // PCI E 4 + device pci c.0 on end // PCI E 3 + device pci d.0 on end // PCI E 2 + device pci e.0 on end // PCI E 1 + device pci f.0 on end // PCI E 0 register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 + // 1: SMBus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" end @@ -149,16 +149,16 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device pci 19.4 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end # chip name - # device pnp 0.1 on end # pci_regs_all - # device pnp 0.2 off end # mem - # device pnp 0.3 off end # cpuid - # device pnp 0.4 on end # smbus_regs_all - # device pnp 0.5 off end # dual core msr - # device pnp 0.6 off end # cache size - # device pnp 0.7 off end # tsc - # device pnp 0.8 off end # io - # device pnp 0.9 on end # io - # end + // chip drivers/generic/debug + // device pnp 0.0 off end # chip name + // device pnp 0.1 on end # pci_regs_all + // device pnp 0.2 off end # mem + // device pnp 0.3 off end # cpuid + // device pnp 0.4 on end # smbus_regs_all + // device pnp 0.5 off end # dual core msr + // device pnp 0.6 off end # cache size + // device pnp 0.7 off end # tsc + // device pnp 0.8 off end # io + // device pnp 0.9 on end # io + // end end diff --git a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb index 56ba7b5..40e6291 100644 --- a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb @@ -1,90 +1,90 @@ -chip northbridge/amd/amdfam10/root_complex # Root complex - device lapic_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F_1207 # CPU socket - device lapic 0 on end # Local APIC of the CPU +chip northbridge/amd/amdfam10/root_complex // Root complex + device lapic_cluster 0 on // (L)APIC cluster + chip cpu/amd/socket_F_1207 // CPU socket + device lapic 0 on end // Local APIC of the CPU end end - device pci_domain 0 on # PCI domain + device pci_domain 0 on // PCI domain subsystemid 0x15d9 0x1511 inherit - chip northbridge/amd/amdfam10 # Northbridge / RAM controller + chip northbridge/amd/amdfam10 // Northbridge / RAM controller device pci 18.0 on end device pci 18.0 on end - device pci 18.0 on # SB on link 2 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy + device pci 18.0 on // SB on link 2 + chip southbridge/nvidia/mcp55 // Southbridge + device pci 0.0 on end // HT + device pci 1.0 on // LPC + chip superio/winbond/w83627hf // Super I/O + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel port + device pnp 2e.1 off // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.3 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # PS/2 keyboard + device pnp 2e.5 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # SFI + device pnp 2e.6 off // SFI io 0x62 = 0x100 end - device pnp 2e.7 off # GPIO, game port, MIDI + device pnp 2e.7 off // GPIO, game port, MIDI io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor + device pnp 2e.8 off end // WDTO PLED + device pnp 2e.9 off end // GPIO SUSLED + device pnp 2e.a off end // ACPI + device pnp 2e.b on // Hardware monitor io 0x60 = 0x290 irq 0x70 = 5 end end end device pci 1.1 on end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - chip drivers/generic/generic # MAC EEPROM + device pci 1.1 on // SM 1 + // PCI device SMBus address will + // depend on addon PCI device, do + // we need to scan_smbus_bus? + chip drivers/generic/generic // MAC EEPROM device i2c 51 on end end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.1 off end # AZA + device pci 2.0 on end // USB 1.1 + device pci 2.1 on end // USB 2 + device pci 4.0 on end // IDE + device pci 5.0 on end // SATA 0 + device pci 5.1 on end // SATA 1 + device pci 5.2 on end // SATA 2 + device pci 6.1 off end // AZA device pci 7.0 on device pci 1.0 on end end device pci 8.0 off end device pci 9.0 off end - device pci a.0 on end # PCI E 5 - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 + device pci a.0 on end // PCI E 5 + device pci b.0 on end // PCI E 4 + device pci c.0 on end // PCI E 3 + device pci d.0 on end // PCI E 2 + device pci e.0 on end // PCI E 1 + device pci f.0 on end // PCI E 0 register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 + // 1: SMBus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" end @@ -112,16 +112,16 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device pci 19.4 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end # chip name - # device pnp 0.1 on end # pci_regs_all - # device pnp 0.2 off end # mem - # device pnp 0.3 off end # cpuid - # device pnp 0.4 on end # smbus_regs_all - # device pnp 0.5 off end # dual core msr - # device pnp 0.6 off end # cache size - # device pnp 0.7 off end # tsc - # device pnp 0.8 off end # io - # device pnp 0.9 on end # io - # end + // chip drivers/generic/debug + // device pnp 0.0 off end # chip name + // device pnp 0.1 on end # pci_regs_all + // device pnp 0.2 off end # mem + // device pnp 0.3 off end # cpuid + // device pnp 0.4 on end # smbus_regs_all + // device pnp 0.5 off end # dual core msr + // device pnp 0.6 off end # cache size + // device pnp 0.7 off end # tsc + // device pnp 0.8 off end # io + // device pnp 0.9 on end # io + // end end diff --git a/src/mainboard/supermicro/x6dai_g/devicetree.cb b/src/mainboard/supermicro/x6dai_g/devicetree.cb index e6201a8..aea518e 100644 --- a/src/mainboard/supermicro/x6dai_g/devicetree.cb +++ b/src/mainboard/supermicro/x6dai_g/devicetree.cb @@ -1,7 +1,7 @@ -chip northbridge/intel/e7525 # mch +chip northbridge/intel/e7525 // mch device pci_domain 0 on subsystemid 0x15d9 0x6780 inherit - chip southbridge/intel/esb6300 # esb6300 + chip southbridge/intel/esb6300 // esb6300 register "pirq_a_d" = "0x0b0a0a05" register "pirq_e_h" = "0x0a0b0c80"
@@ -54,10 +54,10 @@ chip northbridge/intel/e7525 # mch device pci 08.0 on end end device lapic_cluster 0 on - chip cpu/intel/socket_mPGA604 # cpu0 + chip cpu/intel/socket_mPGA604 // cpu0 device lapic 0 on end end - chip cpu/intel/socket_mPGA604 # cpu1 + chip cpu/intel/socket_mPGA604 // cpu1 device lapic 6 on end end end diff --git a/src/mainboard/supermicro/x6dhe_g/devicetree.cb b/src/mainboard/supermicro/x6dhe_g/devicetree.cb index 08c0751..7590f53 100644 --- a/src/mainboard/supermicro/x6dhe_g/devicetree.cb +++ b/src/mainboard/supermicro/x6dhe_g/devicetree.cb @@ -1,5 +1,5 @@ -chip northbridge/intel/e7520 # MCH - chip drivers/generic/debug # DEBUGGING +chip northbridge/intel/e7520 // MCH + chip drivers/generic/debug // DEBUGGING device pnp 00.0 on end device pnp 00.1 off end device pnp 00.2 off end @@ -7,25 +7,25 @@ chip northbridge/intel/e7520 # MCH end device pci_domain 0 on subsystemid 0x15d9 0x6080 inherit - chip southbridge/intel/esb6300 # ESB6300 + chip southbridge/intel/esb6300 // ESB6300 register "pirq_a_d" = "0x0b070a05" register "pirq_e_h" = "0x0a808080"
device pci 1c.0 on chip drivers/generic/generic - device pci 01.0 on end # onboard gige1 - device pci 02.0 on end # onboard gige2 + device pci 01.0 on end // onboard gige1 + device pci 02.0 on end // onboard gige2 end end
- # USB ports + // USB ports device pci 1d.0 on end device pci 1d.1 on end - device pci 1d.4 on end # Southbridge Watchdog timer - device pci 1d.5 on end # Southbridge I/O apic1 + device pci 1d.4 on end // Southbridge Watchdog timer + device pci 1d.5 on end // Southbridge I/O apic1 device pci 1d.7 on end
- # VGA / PCI 32-bit + // VGA / PCI 32-bit device pci 1e.0 on chip drivers/generic/generic device pci 01.0 on end @@ -33,7 +33,7 @@ chip northbridge/intel/e7520 # MCH end
- device pci 1f.0 on # ISA bridge + device pci 1f.0 on // ISA bridge chip superio/winbond/w83627hf device pnp 2e.0 off end device pnp 2e.2 on @@ -55,32 +55,32 @@ chip northbridge/intel/e7520 # MCH end device pci 1f.1 on end device pci 1f.2 off end - device pci 1f.3 on end # SMBus + device pci 1f.3 on end // SMBus device pci 1f.5 off end device pci 1f.6 off end end
- device pci 00.0 on end # Northbridge - device pci 00.1 on end # Northbridge Error reporting + device pci 00.0 on end // Northbridge + device pci 00.1 on end // Northbridge Error reporting device pci 01.0 on end device pci 02.0 on - chip southbridge/intel/pxhd # PXHD 6700 - device pci 00.0 on end # bridge - device pci 00.1 on end # I/O apic - device pci 00.2 on end # bridge - device pci 00.3 on end # I/O apic + chip southbridge/intel/pxhd // PXHD 6700 + device pci 00.0 on end // bridge + device pci 00.1 on end // I/O apic + device pci 00.2 on end // bridge + device pci 00.3 on end // I/O apic end end -# device register "intrline" = "0x00070105" +// device register "intrline" = "0x00070105" device pci 04.0 on end device pci 06.0 on end end
device lapic_cluster 0 on - chip cpu/intel/socket_mPGA604 # CPU 0 + chip cpu/intel/socket_mPGA604 // CPU 0 device lapic 0 on end end - chip cpu/intel/socket_mPGA604 # CPU 1 + chip cpu/intel/socket_mPGA604 // CPU 1 device lapic 6 on end end end diff --git a/src/mainboard/supermicro/x6dhe_g2/devicetree.cb b/src/mainboard/supermicro/x6dhe_g2/devicetree.cb index ecfe0a0..f27e7e3 100644 --- a/src/mainboard/supermicro/x6dhe_g2/devicetree.cb +++ b/src/mainboard/supermicro/x6dhe_g2/devicetree.cb @@ -1,5 +1,5 @@ -chip northbridge/intel/e7520 # MCH - chip drivers/generic/debug # DEBUGGING +chip northbridge/intel/e7520 // MCH + chip drivers/generic/debug // DEBUGGING device pnp 00.0 off end device pnp 00.1 off end device pnp 00.2 off end @@ -7,25 +7,25 @@ chip northbridge/intel/e7520 # MCH end device pci_domain 0 on subsystemid 0x15d9 0x6080 inherit - chip southbridge/intel/i82801ex # ICH5R + chip southbridge/intel/i82801ex // ICH5R register "pirq_a_d" = "0x0b070a05" register "pirq_e_h" = "0x0a808080"
device pci 1c.0 on chip drivers/generic/generic - device pci 01.0 on end # onboard gige1 - device pci 02.0 on end # onboard gige2 + device pci 01.0 on end // onboard gige1 + device pci 02.0 on end // onboard gige2 end end
- # USB ports + // USB ports device pci 1d.0 on end device pci 1d.1 on end - device pci 1d.4 on end # Southbridge Watchdog timer - device pci 1d.5 on end # Southbridge I/O apic1 + device pci 1d.4 on end // Southbridge Watchdog timer + device pci 1d.5 on end // Southbridge I/O apic1 device pci 1d.7 on end
- # VGA / PCI 32-bit + // VGA / PCI 32-bit device pci 1e.0 on chip drivers/generic/generic device pci 01.0 on end @@ -33,7 +33,7 @@ chip northbridge/intel/e7520 # MCH end
- device pci 1f.0 on # ISA bridge + device pci 1f.0 on // ISA bridge chip superio/nsc/pc87427 device pnp 2e.0 off end device pnp 2e.2 on @@ -55,32 +55,32 @@ chip northbridge/intel/e7520 # MCH end device pci 1f.1 on end device pci 1f.2 on end - device pci 1f.3 on end # SMBus + device pci 1f.3 on end // SMBus device pci 1f.5 off end device pci 1f.6 off end end
- device pci 00.0 on end # Northbridge - device pci 00.1 on end # Northbridge Error reporting + device pci 00.0 on end // Northbridge + device pci 00.1 on end // Northbridge Error reporting device pci 01.0 on end device pci 02.0 on - chip southbridge/intel/pxhd # PXHD 6700 - device pci 00.0 on end # bridge - device pci 00.1 on end # I/O apic - device pci 00.2 on end # bridge - device pci 00.3 on end # I/O apic + chip southbridge/intel/pxhd // PXHD 6700 + device pci 00.0 on end // bridge + device pci 00.1 on end // I/O apic + device pci 00.2 on end // bridge + device pci 00.3 on end // I/O apic end end -# device register "intrline" = "0x00070105" +// device register "intrline" = "0x00070105" device pci 04.0 on end device pci 06.0 on end end
device lapic_cluster 0 on - chip cpu/intel/socket_mPGA604 # CPU 0 + chip cpu/intel/socket_mPGA604 // CPU 0 device lapic 0 on end end - chip cpu/intel/socket_mPGA604 # CPU 1 + chip cpu/intel/socket_mPGA604 // CPU 1 device lapic 6 on end end end diff --git a/src/mainboard/supermicro/x6dhr_ig/devicetree.cb b/src/mainboard/supermicro/x6dhr_ig/devicetree.cb index 6ada3b1..57a815d 100644 --- a/src/mainboard/supermicro/x6dhr_ig/devicetree.cb +++ b/src/mainboard/supermicro/x6dhr_ig/devicetree.cb @@ -1,18 +1,18 @@ -chip northbridge/intel/e7520 # mch +chip northbridge/intel/e7520 // mch device pci_domain 0 on subsystemid 0x15d9 0x5580 inherit - chip southbridge/intel/i82801ex # i82801er - # USB ports + chip southbridge/intel/i82801ex // i82801er + // USB ports device pci 1d.0 on end device pci 1d.1 on end device pci 1d.2 on end device pci 1d.3 on end device pci 1d.7 on end
- # -> VGA + // -> VGA device pci 1e.0 on end
- # -> IDE + // -> IDE device pci 1f.0 on chip superio/winbond/w83627hf device pnp 2e.0 off end @@ -45,12 +45,12 @@ chip northbridge/intel/e7520 # mch device pci 01.0 on end device pci 02.0 on end device pci 03.0 on - chip southbridge/intel/pxhd # pxhd1 - # Bus bridges and ioapics usually bus 2 + chip southbridge/intel/pxhd // pxhd1 + // Bus bridges and ioapics usually bus 2 device pci 0.0 on end device pci 0.1 on end device pci 0.2 on - # On board gig e1000 + // On board gig e1000 chip drivers/generic/generic device pci 02.0 on end device pci 02.1 on end @@ -60,23 +60,23 @@ chip northbridge/intel/e7520 # mch end end device pci 04.0 on - chip southbridge/intel/pxhd # pxhd2 - # Bus bridges and ioapics usually bus 5 + chip southbridge/intel/pxhd // pxhd2 + // Bus bridges and ioapics usually bus 5 device pci 0.0 on end - # Slot 6 is usually 6:2.0 + // Slot 6 is usually 6:2.0 device pci 0.1 on end device pci 0.2 on end - # Slot 7 is usually 7:2.0 + // Slot 7 is usually 7:2.0 device pci 0.3 on end end end device pci 06.0 on end end device lapic_cluster 0 on - chip cpu/intel/socket_mPGA604 # cpu 0 + chip cpu/intel/socket_mPGA604 // cpu 0 device lapic 0 on end end - chip cpu/intel/socket_mPGA604 # cpu 1 + chip cpu/intel/socket_mPGA604 // cpu 1 device lapic 6 on end end end diff --git a/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb b/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb index 3d9b644..32b0768 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb +++ b/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb @@ -1,18 +1,18 @@ -chip northbridge/intel/e7520 # mch +chip northbridge/intel/e7520 // mch device pci_domain 0 on subsystemid 0x15d9 0x5580 inherit - chip southbridge/intel/i82801ex # i82801er - # USB ports + chip southbridge/intel/i82801ex // i82801er + // USB ports device pci 1d.0 on end device pci 1d.1 on end device pci 1d.2 on end device pci 1d.3 on end device pci 1d.7 on end
- # -> Bridge + // -> Bridge device pci 1e.0 on end
- # -> ISA + // -> ISA device pci 1f.0 on chip superio/winbond/w83627hf device pnp 2e.0 off end @@ -33,9 +33,9 @@ chip northbridge/intel/e7520 # mch device pnp 2e.b off end end end - # -> IDE + // -> IDE device pci 1f.1 on end - # -> SATA + // -> SATA device pci 1f.2 on end device pci 1f.3 on end
@@ -46,10 +46,10 @@ chip northbridge/intel/e7520 # mch device pci 00.1 on end device pci 01.0 on end device pci 02.0 on - chip southbridge/intel/pxhd # pxhd1 - # Bus bridges and ioapics usually bus 1 + chip southbridge/intel/pxhd // pxhd1 + // Bus bridges and ioapics usually bus 1 device pci 0.0 on - # On board gig e1000 + // On board gig e1000 chip drivers/generic/generic device pci 03.0 on end device pci 03.1 on end @@ -64,10 +64,10 @@ chip northbridge/intel/e7520 # mch device pci 06.0 on end end device lapic_cluster 0 on - chip cpu/intel/socket_mPGA604 # cpu 0 + chip cpu/intel/socket_mPGA604 // cpu 0 device lapic 0 on end end - chip cpu/intel/socket_mPGA604 # cpu 1 + chip cpu/intel/socket_mPGA604 // cpu 1 device lapic 6 on end end end diff --git a/src/mainboard/technexion/tim5690/devicetree.cb b/src/mainboard/technexion/tim5690/devicetree.cb index 148a4ab..bb9c481 100644 --- a/src/mainboard/technexion/tim5690/devicetree.cb +++ b/src/mainboard/technexion/tim5690/devicetree.cb @@ -1,13 +1,13 @@ -#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) -#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, -# 1: the system allows a PCIE link to be established on Dev2 or Dev3. -#Define gfx_dual_slot, 0: single slot, 1: dual slot -#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable -#Define gfx_tmds, 0: didn't support TMDS, 1: support -#Define gfx_compliance, 0: didn't support compliance, 1: support -#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration -#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 +//Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +//Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) +//Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, +// 1: the system allows a PCIE link to be established on Dev2 or Dev3. +//Define gfx_dual_slot, 0: single slot, 1: dual slot +//Define gfx_lane_reversal, 0: disable lane reversal, 1: enable +//Define gfx_tmds, 0: didn't support TMDS, 1: support +//Define gfx_compliance, 0: didn't support compliance, 1: support +//Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration +//Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex device lapic_cluster 0 on chip cpu/amd/socket_S1G1 @@ -17,19 +17,19 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on subsystemid 0x1022 0x3050 inherit chip northbridge/amd/amdk8 - device pci 18.0 on # southbridge + device pci 18.0 on // southbridge chip southbridge/amd/rs690 - device pci 0.0 on end # HT 0x7910 - device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - device pci 5.0 on end # Internal Graphics 0x791F + device pci 0.0 on end // HT 0x7910 + device pci 1.0 on // Internal Graphics P2P bridge 0x7912 + device pci 5.0 on end // Internal Graphics 0x791F end - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 - device pci 3.0 off end # PCIE P2P bridge 0x791b - device pci 4.0 on end # PCIE P2P bridge 0x7914 - device pci 5.0 on end # PCIE P2P bridge 0x7915 - device pci 6.0 on end # PCIE P2P bridge 0x7916 - device pci 7.0 on end # PCIE P2P bridge 0x7917 - device pci 8.0 off end # NB/SB Link P2P bridge + device pci 2.0 on end // PCIE P2P bridge (external graphics) 0x7913 + device pci 3.0 off end // PCIE P2P bridge 0x791b + device pci 4.0 on end // PCIE P2P bridge 0x7914 + device pci 5.0 on end // PCIE P2P bridge 0x7915 + device pci 6.0 on end // PCIE P2P bridge 0x7916 + device pci 7.0 on end // PCIE P2P bridge 0x7917 + device pci 8.0 off end // NB/SB Link P2P bridge register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" @@ -40,74 +40,74 @@ chip northbridge/amd/amdk8/root_complex register "gfx_reconfiguration" = "0" register "gfx_link_width" = "0" end - chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus - device pci 12.0 on end # SATA 0x4380 - device pci 13.0 on end # USB 0x4387 - device pci 13.1 on end # USB 0x4388 - device pci 13.2 on end # USB 0x4389 - device pci 13.3 on end # USB 0x438a - device pci 13.4 on end # USB 0x438b - device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 - chip drivers/generic/generic #dimm 0-0-0 + chip southbridge/amd/sb600 // it is under NB/SB Link, but on the same pri bus + device pci 12.0 on end // SATA 0x4380 + device pci 13.0 on end // USB 0x4387 + device pci 13.1 on end // USB 0x4388 + device pci 13.2 on end // USB 0x4389 + device pci 13.3 on end // USB 0x438a + device pci 13.4 on end // USB 0x438b + device pci 13.5 on end // USB 2 0x4386 + device pci 14.0 on // SM 0x4385 + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - end # SM - device pci 14.1 on end # IDE 0x438c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x438d + end // SM + device pci 14.1 on end // IDE 0x438c + device pci 14.2 on end // HDA 0x4383 + device pci 14.3 on // LPC 0x438d chip superio/ite/it8712f - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Com1 + device pnp 2e.1 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 on # Com2 + device pnp 2e.2 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 on # Parallel Port + device pnp 2e.3 on // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard + device pnp 2e.4 off end // EC + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.6 on # Mouse + device pnp 2e.6 on // Mouse irq 0x70 = 12 end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + device pnp 2e.7 off // GPIO, must be closed for unresolved reason. end - device pnp 2e.8 off # MIDI + device pnp 2e.8 off // MIDI io 0x60 = 0x300 irq 0x70 = 9 end - device pnp 2e.9 off # GAME + device pnp 2e.9 off // GAME io 0x60 = 0x220 end - device pnp 2e.a off end # CIR - end #superio/ite/it8712f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # ACI 0x4382 - device pci 14.6 on end # MCI 0x438e + device pnp 2e.a off end // CIR + end //superio/ite/it8712f + end //LPC + device pci 14.4 on end // PCI 0x4384 + device pci 14.5 on end // ACI 0x4382 + device pci 14.6 on end // MCI 0x438e register "hda_viddid" = "0x10ec0882" - end #southbridge/amd/sb600 - end # device pci 18.0 + end //southbridge/amd/sb600 + end // device pci 18.0
device pci 18.0 on end device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end - end #northbridge/amd/amdk8 - end #pci_domain -end #northbridge/amd/amdk8/root_complex + end //northbridge/amd/amdk8 + end //pci_domain +end //northbridge/amd/amdk8/root_complex
diff --git a/src/mainboard/technexion/tim8690/devicetree.cb b/src/mainboard/technexion/tim8690/devicetree.cb index e1f8936..0e30741 100644 --- a/src/mainboard/technexion/tim8690/devicetree.cb +++ b/src/mainboard/technexion/tim8690/devicetree.cb @@ -1,13 +1,13 @@ -#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) -#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, -# 1: the system allows a PCIE link to be established on Dev2 or Dev3. -#Define gfx_dual_slot, 0: single slot, 1: dual slot -#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable -#Define gfx_tmds, 0: didn't support TMDS, 1: support -#Define gfx_compliance, 0: didn't support compliance, 1: support -#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration -#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 +//Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +//Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) +//Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, +// 1: the system allows a PCIE link to be established on Dev2 or Dev3. +//Define gfx_dual_slot, 0: single slot, 1: dual slot +//Define gfx_lane_reversal, 0: disable lane reversal, 1: enable +//Define gfx_tmds, 0: didn't support TMDS, 1: support +//Define gfx_compliance, 0: didn't support compliance, 1: support +//Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration +//Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex device lapic_cluster 0 on chip cpu/amd/socket_S1G1 @@ -17,19 +17,19 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on subsystemid 0x1022 0x3050 inherit chip northbridge/amd/amdk8 - device pci 18.0 on # southbridge + device pci 18.0 on // southbridge chip southbridge/amd/rs690 - device pci 0.0 on end # HT 0x7910 - device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - device pci 5.0 on end # Internal Graphics 0x791F + device pci 0.0 on end // HT 0x7910 + device pci 1.0 on // Internal Graphics P2P bridge 0x7912 + device pci 5.0 on end // Internal Graphics 0x791F end - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 - device pci 3.0 off end # PCIE P2P bridge 0x791b - device pci 4.0 on end # PCIE P2P bridge 0x7914 - device pci 5.0 on end # PCIE P2P bridge 0x7915 - device pci 6.0 on end # PCIE P2P bridge 0x7916 - device pci 7.0 on end # PCIE P2P bridge 0x7917 - device pci 8.0 off end # NB/SB Link P2P bridge + device pci 2.0 on end // PCIE P2P bridge (external graphics) 0x7913 + device pci 3.0 off end // PCIE P2P bridge 0x791b + device pci 4.0 on end // PCIE P2P bridge 0x7914 + device pci 5.0 on end // PCIE P2P bridge 0x7915 + device pci 6.0 on end // PCIE P2P bridge 0x7916 + device pci 7.0 on end // PCIE P2P bridge 0x7917 + device pci 8.0 off end // NB/SB Link P2P bridge register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" @@ -40,77 +40,77 @@ chip northbridge/amd/amdk8/root_complex register "gfx_reconfiguration" = "1" register "gfx_link_width" = "0" end - chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus - device pci 12.0 on end # SATA 0x4380 - device pci 13.0 on end # USB 0x4387 - device pci 13.1 on end # USB 0x4388 - device pci 13.2 on end # USB 0x4389 - device pci 13.3 on end # USB 0x438a - device pci 13.4 on end # USB 0x438b - device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 - chip drivers/generic/generic #dimm 0-0-0 + chip southbridge/amd/sb600 // it is under NB/SB Link, but on the same pri bus + device pci 12.0 on end // SATA 0x4380 + device pci 13.0 on end // USB 0x4387 + device pci 13.1 on end // USB 0x4388 + device pci 13.2 on end // USB 0x4389 + device pci 13.3 on end // USB 0x438a + device pci 13.4 on end // USB 0x438b + device pci 13.5 on end // USB 2 0x4386 + device pci 14.0 on // SM 0x4385 + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 + chip drivers/generic/generic //dimm 0-0-1 device i2c 51 on end end - end # SM - device pci 14.1 on end # IDE 0x438c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x438d + end // SM + device pci 14.1 on end // IDE 0x438c + device pci 14.2 on end // HDA 0x4383 + device pci 14.3 on // LPC 0x438d chip superio/ite/it8712f - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Com1 + device pnp 2e.1 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 off # Com2 + device pnp 2e.2 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 off # Parallel Port + device pnp 2e.3 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard + device pnp 2e.4 off end // EC + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.6 on # Mouse + device pnp 2e.6 on // Mouse irq 0x70 = 12 end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + device pnp 2e.7 off // GPIO, must be closed for unresolved reason. end - device pnp 2e.8 off # MIDI + device pnp 2e.8 off // MIDI io 0x60 = 0x300 irq 0x70 = 9 end - device pnp 2e.9 off # GAME + device pnp 2e.9 off // GAME io 0x60 = 0x220 end - device pnp 2e.a off end # CIR - end #superio/ite/it8712f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # ACI 0x4382 - device pci 14.6 on end # MCI 0x438e + device pnp 2e.a off end // CIR + end //superio/ite/it8712f + end //LPC + device pci 14.4 on end // PCI 0x4384 + device pci 14.5 on end // ACI 0x4382 + device pci 14.6 on end // MCI 0x438e register "hda_viddid" = "0x10ec0882" - end #southbridge/amd/sb600 - end # device pci 18.0 + end //southbridge/amd/sb600 + end // device pci 18.0
device pci 18.0 on end device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end - end #northbridge/amd/amdk8 - end #pci_domain -end #northbridge/amd/amdk8/root_complex + end //northbridge/amd/amdk8 + end //pci_domain +end //northbridge/amd/amdk8/root_complex
diff --git a/src/mainboard/technologic/ts5300/devicetree.cb b/src/mainboard/technologic/ts5300/devicetree.cb index a0f0579..12a59f2 100644 --- a/src/mainboard/technologic/ts5300/devicetree.cb +++ b/src/mainboard/technologic/ts5300/devicetree.cb @@ -2,8 +2,8 @@ chip cpu/amd/sc520 device pci_domain 0 on device pci 0.0 on end
-# register "com1" = "{1}" -# register "com1" = "{1, 0, 0x3f8, 4}" +// register "com1" = "{1}" +// register "com1" = "{1, 0, 0x3f8, 4}" end
end diff --git a/src/mainboard/televideo/tc7020/devicetree.cb b/src/mainboard/televideo/tc7020/devicetree.cb index bf89cf2..50bcbb5 100644 --- a/src/mainboard/televideo/tc7020/devicetree.cb +++ b/src/mainboard/televideo/tc7020/devicetree.cb @@ -1,57 +1,57 @@ -chip northbridge/amd/gx1 # Northbridge - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - chip southbridge/amd/cs5530 # Southbridge - device pci 12.0 on # ISA bridge - chip superio/nsc/pc97317 # Super I/O - device pnp 2e.0 on # PS/2 keyboard +chip northbridge/amd/gx1 // Northbridge + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + chip southbridge/amd/cs5530 // Southbridge + device pci 12.0 on // ISA bridge + chip superio/nsc/pc97317 // Super I/O + device pnp 2e.0 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.1 on # PS/2 mouse + device pnp 2e.1 on // PS/2 mouse irq 0x70 = 12 end - device pnp 2e.2 on # RTC, Advanced power control (APC) + device pnp 2e.2 on // RTC, Advanced power control (APC) io 0x60 = 0x70 irq 0x70 = 8 end - device pnp 2e.3 off # Floppy (N/A on this board) + device pnp 2e.3 off // Floppy (N/A on this board) io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.4 on # Parallel port + device pnp 2e.4 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.5 on # COM2 + device pnp 2e.5 on // COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.6 on # COM1 + device pnp 2e.6 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.7 on # GPIO + device pnp 2e.7 on // GPIO io 0x60 = 0xe0 end - device pnp 2e.8 on # Power management + device pnp 2e.8 on // Power management io 0x60 = 0xe8 end end end - device pci 12.1 off end # SMI - device pci 12.2 on end # IDE - device pci 12.3 on end # Audio - device pci 12.4 on end # VGA (onboard) - device pci 13.0 on end # USB - device pci 14.0 on end # MiniPCI slot - device pci 15.0 on end # Ethernet (onboard) + device pci 12.1 off end // SMI + device pci 12.2 on end // IDE + device pci 12.3 on end // Audio + device pci 12.4 on end // VGA (onboard) + device pci 13.0 on end // USB + device pci 14.0 on end // MiniPCI slot + device pci 15.0 on end // Ethernet (onboard) register "ide0_enable" = "1" - register "ide1_enable" = "0" # Not available/needed on this board + register "ide1_enable" = "0" // Not available/needed on this board end end - chip cpu/amd/model_gx1 # CPU + chip cpu/amd/model_gx1 // CPU end end diff --git a/src/mainboard/thomson/ip1000/devicetree.cb b/src/mainboard/thomson/ip1000/devicetree.cb index f7b11f1..4fa66c2 100644 --- a/src/mainboard/thomson/ip1000/devicetree.cb +++ b/src/mainboard/thomson/ip1000/devicetree.cb @@ -1,14 +1,14 @@ -chip northbridge/intel/i82830 # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/socket_mFCBGA479 # Low Voltage PIII Micro-FCBGA Socket 479 - device lapic 0 on end # APIC +chip northbridge/intel/i82830 // Northbridge + device lapic_cluster 0 on // APIC cluster + chip cpu/intel/socket_mFCBGA479 // Low Voltage PIII Micro-FCBGA Socket 479 + device lapic 0 on end // APIC end end
- device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 2.0 on end # VGA (Intel 82830 CGC) - chip southbridge/intel/i82801dx # Southbridge + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + device pci 2.0 on end // VGA (Intel 82830 CGC) + chip southbridge/intel/i82801dx // Southbridge register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x06" register "pirqc_routing" = "0x07" @@ -21,48 +21,48 @@ chip northbridge/intel/i82830 # Northbridge register "ide0_enable" = "1" register "ide1_enable" = "1"
- device pci 1d.0 on end # USB UHCI Controller #1 - device pci 1d.1 on end # USB UHCI Controller #2 - device pci 1d.2 on end # USB UHCI Controller #3 - device pci 1d.7 on end # USB2 EHCI Controller - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA/LPC bridge - chip superio/smsc/smscsuperio # Super I/O - device pnp 2e.0 off # Floppy + device pci 1d.0 on end // USB UHCI Controller #1 + device pci 1d.1 on end // USB UHCI Controller #2 + device pci 1d.2 on end // USB UHCI Controller #3 + device pci 1d.7 on end // USB2 EHCI Controller + device pci 1e.0 on end // PCI bridge + device pci 1f.0 on // ISA/LPC bridge + chip superio/smsc/smscsuperio // Super I/O + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.3 on # Parallel port + device pnp 2e.3 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 4 end - device pnp 2e.4 on # Com1 + device pnp 2e.4 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.5 on # Com2 / IR + device pnp 2e.5 on // Com2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.7 on # PS/2 keyboard/mouse + device pnp 2e.7 on // PS/2 keyboard/mouse io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 # Keyboard interrupt - irq 0x72 = 12 # Mouse interrupt + irq 0x70 = 1 // Keyboard interrupt + irq 0x72 = 12 // Mouse interrupt end - device pnp 2e.9 off end # Game port - device pnp 2e.a on # PME + device pnp 2e.9 off end // Game port + device pnp 2e.a on // PME io 0x60 = 0x800 end - device pnp 2e.b off end # MPU-401 + device pnp 2e.b off end // MPU-401 end end - device pci 1f.1 on end # IDE - device pci 1f.3 on end # SMBus - device pci 1f.5 on end # AC'97 audio - device pci 1f.6 off end # AC'97 modem + device pci 1f.1 on end // IDE + device pci 1f.3 on end // SMBus + device pci 1f.5 on end // AC'97 audio + device pci 1f.6 off end // AC'97 modem end end end diff --git a/src/mainboard/traverse/geos/devicetree.cb b/src/mainboard/traverse/geos/devicetree.cb index eab70c7..a215412 100644 --- a/src/mainboard/traverse/geos/devicetree.cb +++ b/src/mainboard/traverse/geos/devicetree.cb @@ -1,37 +1,37 @@ chip northbridge/amd/lx device pci_domain 0 on - device pci 1.0 on end # Northbridge - device pci 1.1 on end # Graphics + device pci 1.0 on end // Northbridge + device pci 1.1 on end // Graphics chip southbridge/amd/cs5536 - # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK - # SIRQ Mode = Active(Quiet) mode. Save power.... - # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK + // IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + // SIRQ Mode = Active(Quiet) mode. Save power.... + // Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK register "lpc_serirq_enable" = "0x00001002" register "lpc_serirq_polarity" = "0x0000EFFD" register "lpc_serirq_mode" = "1" register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "0" #0: host, 1:device - register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "enable_ide_nand_flash" = "0" // 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" //0: host, 1:device + register "enable_USBP4_overcurrent" = "0" //0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) register "com1_enable" = "1" register "com1_address" = "0x3F8" register "com1_irq" = "4" register "com2_enable" = "0" register "com2_address" = "0x2F8" register "com2_irq" = "3" - register "unwanted_vpci[0]" = "0" # End of list has a zero - device pci a.0 on end # Ethernet 0 - device pci b.0 on end # Ethernet 1 - device pci c.0 on end # Xilinx - device pci d.0 on end # Mini PCI - device pci f.0 on end # ISA Bridge - device pci f.2 on end # IDE Controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI + register "unwanted_vpci[0]" = "0" // End of list has a zero + device pci a.0 on end // Ethernet 0 + device pci b.0 on end // Ethernet 1 + device pci c.0 on end // Xilinx + device pci d.0 on end // Mini PCI + device pci f.0 on end // ISA Bridge + device pci f.2 on end // IDE Controller + device pci f.3 on end // Audio + device pci f.4 on end // OHCI + device pci f.5 on end // EHCI end end - # APIC cluster is late CPU init. + // APIC cluster is late CPU init. device lapic_cluster 0 on chip cpu/amd/model_lx device lapic 0 on end diff --git a/src/mainboard/tyan/s1846/devicetree.cb b/src/mainboard/tyan/s1846/devicetree.cb index d3df17c..73c3fe7 100644 --- a/src/mainboard/tyan/s1846/devicetree.cb +++ b/src/mainboard/tyan/s1846/devicetree.cb @@ -1,51 +1,51 @@ -chip northbridge/intel/i440bx # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/slot_1 # CPU - device lapic 0 on end # APIC +chip northbridge/intel/i440bx // Northbridge + device lapic_cluster 0 on // APIC cluster + chip cpu/intel/slot_1 // CPU + device lapic 0 on end // APIC end end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 7.0 on # ISA bridge - chip superio/nsc/pc87309 # Super I/O - device pnp 2e.0 on # Floppy + device pci_domain 0 on // PCI domain + device pci 0.0 on end // Host bridge + device pci 1.0 on end // PCI/AGP bridge + chip southbridge/intel/i82371eb // Southbridge + device pci 7.0 on // ISA bridge + chip superio/nsc/pc87309 // Super I/O + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Parallel port + device pnp 2e.1 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # COM2 / IR + device pnp 2e.2 on // COM2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 on # COM1 + device pnp 2e.3 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.4 on # Power management + device pnp 2e.4 on // Power management end - device pnp 2e.5 on # PS/2 mouse + device pnp 2e.5 on // PS/2 mouse irq 0x70 = 12 end - device pnp 2e.6 on # PS/2 keyboard + device pnp 2e.6 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end end end - device pci 7.1 on end # IDE - device pci 7.2 on end # USB - device pci 7.3 on end # ACPI + device pci 7.1 on end // IDE + device pci 7.2 on end // USB + device pci 7.3 on end // ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. + // Enable UDMA/33 for higher speed if your IDE device(s) support it. register "ide0_drive0_udma33_enable" = "0" register "ide0_drive1_udma33_enable" = "0" register "ide1_drive0_udma33_enable" = "0" diff --git a/src/mainboard/tyan/s2735/devicetree.cb b/src/mainboard/tyan/s2735/devicetree.cb index c0557f8..31afeef 100644 --- a/src/mainboard/tyan/s2735/devicetree.cb +++ b/src/mainboard/tyan/s2735/devicetree.cb @@ -7,7 +7,7 @@ chip northbridge/intel/e7501 chip southbridge/intel/i82870 device pci 1c.0 on end device pci 1d.0 on - device pci 1.0 on end # intel lan + device pci 1.0 on end // intel lan device pci 1.1 on end end device pci 1e.0 on end @@ -22,46 +22,46 @@ chip northbridge/intel/e7501 device pci 1d.3 on end device pci 1d.7 on end device pci 1e.0 on - device pci 1.0 on end # intel lan 10/100 - device pci 2.0 on end # ati + device pci 1.0 on end // intel lan 10/100 + device pci 2.0 on end // ati end device pci 1f.0 on chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # Com2 + device pnp 2e.3 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # CIR + device pnp 2e.6 off // CIR io 0x60 = 0x100 end - device pnp 2e.7 off # GAME_MIDI_GIPO1 + device pnp 2e.7 off // GAME_MIDI_GIPO1 io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.8 off end // GPIO2 + device pnp 2e.9 off end // GPIO3 + device pnp 2e.a off end // ACPI + device pnp 2e.b on // HW Monitor io 0x60 = 0x290 irq 0x70 = 5 end @@ -72,8 +72,8 @@ chip northbridge/intel/e7501 device pci 1f.3 on end device pci 1f.5 off end device pci 1f.6 off end - end # SB - end # PCI_DOMAIN + end // SB + end // PCI_DOMAIN device lapic_cluster 0 on chip cpu/intel/socket_mPGA604 device lapic 0 on end diff --git a/src/mainboard/tyan/s2850/devicetree.cb b/src/mainboard/tyan/s2850/devicetree.cb index 4e981ad..61c4e1e 100644 --- a/src/mainboard/tyan/s2850/devicetree.cb +++ b/src/mainboard/tyan/s2850/devicetree.cb @@ -7,56 +7,56 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on subsystemid 0x10f1 0x2850 inherit chip northbridge/amd/amdk8 - device pci 18.0 on # LDT0 - # devices on link 2, link 2 == LDT 2 + device pci 18.0 on // LDT0 + // devices on link 2, link 2 == LDT 2 chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge + // this "device pci 0.0" is the parent the next one + // PCI bridge device pci 0.0 on device pci 0.0 on end device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - #chip drivers/ati/ragexl + //chip drivers/ati/ragexl device pci b.0 on end end device pci 1.0 on chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.3 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # CIR + device pnp 2e.6 off // CIR io 0x60 = 0x100 end - device pnp 2e.7 off # GAME_MIDI_GIPO1 + device pnp 2e.7 off // GAME_MIDI_GIPO1 io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.8 off end // GPIO2 + device pnp 2e.9 off end // GPIO3 + device pnp 2e.a off end // ACPI + device pnp 2e.b on // HW Monitor io 0x60 = 0x290 irq 0x70 = 5 end @@ -65,16 +65,16 @@ chip northbridge/amd/amdk8/root_complex device pci 1.1 on end device pci 1.2 on end device pci 1.3 on - chip drivers/generic/generic #dimm 0-0-0 + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 + chip drivers/generic/generic //dimm 0-0-1 device i2c 51 on end end - chip drivers/generic/generic #dimm 0-1-0 + chip drivers/generic/generic //dimm 0-1-0 device i2c 52 on end end - chip drivers/generic/generic #dimm 0-1-1 + chip drivers/generic/generic //dimm 0-1-1 device i2c 53 on end end end @@ -83,7 +83,7 @@ chip northbridge/amd/amdk8/root_complex register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 + end // device pci 18.0 device pci 18.0 on end device pci 18.0 on end
diff --git a/src/mainboard/tyan/s2875/devicetree.cb b/src/mainboard/tyan/s2875/devicetree.cb index d3d6c6d..0962bae 100644 --- a/src/mainboard/tyan/s2875/devicetree.cb +++ b/src/mainboard/tyan/s2875/devicetree.cb @@ -7,16 +7,16 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on subsystemid 0x10f1 0x2875 inherit chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 + device pci 18.0 on // northbridge + // devices on link 0, link 0 == LDT 0 chip southbridge/amd/amd8151 - # the on/off keyword is mandatory + // the on/off keyword is mandatory device pci 0.0 on end device pci 1.0 on end end chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge + // this "device pci 0.0" is the parent the next one + // PCI bridge device pci 0.0 on device pci 0.0 on end device pci 0.1 on end @@ -26,41 +26,41 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.0 on chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.3 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # CIR + device pnp 2e.6 off // CIR io 0x60 = 0x100 end - device pnp 2e.7 off # GAME_MIDI_GIPO1 + device pnp 2e.7 off // GAME_MIDI_GIPO1 io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.8 off end // GPIO2 + device pnp 2e.9 off end // GPIO3 + device pnp 2e.a off end // ACPI + device pnp 2e.b on // HW Monitor io 0x60 = 0x290 irq 0x70 = 5 end @@ -74,7 +74,7 @@ chip northbridge/amd/amdk8/root_complex register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 + end // device pci 18.0
device pci 18.0 on end device pci 18.0 on end diff --git a/src/mainboard/tyan/s2880/devicetree.cb b/src/mainboard/tyan/s2880/devicetree.cb index b815fb5..550f7a8 100644 --- a/src/mainboard/tyan/s2880/devicetree.cb +++ b/src/mainboard/tyan/s2880/devicetree.cb @@ -7,71 +7,71 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on subsystemid 0x10f1 0x2880 inherit chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 + device pci 18.0 on // northbridge + // devices on link 0, link 0 == LDT 0 chip southbridge/amd/amd8131 - # the on/off keyword is mandatory + // the on/off keyword is mandatory device pci 0.0 on - device pci 9.0 on end #broadcom + device pci 9.0 on end //broadcom device pci 9.1 on end -# chip drivers/lsi/53c1030 -# device pci a.0 on end -# device pci a.1 on end -# register "fw_address" = "0xfff8c000" -# end +// chip drivers/lsi/53c1030 +// device pci a.0 on end +// device pci a.1 on end +// register "fw_address" = "0xfff8c000" +// end end device pci 0.1 on end device pci 1.0 on end device pci 1.1 on end end chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge + // this "device pci 0.0" is the parent the next one + // PCI bridge device pci 0.0 on device pci 0.0 on end device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - device pci 5.0 on end #some sata - device pci 6.0 on end #adti + device pci 5.0 on end //some sata + device pci 6.0 on end //adti end device pci 1.0 on chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.3 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # CIR + device pnp 2e.6 off // CIR io 0x60 = 0x100 end - device pnp 2e.7 off # GAME_MIDI_GIPO1 + device pnp 2e.7 off // GAME_MIDI_GIPO1 io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.8 off end // GPIO2 + device pnp 2e.9 off end // GPIO3 + device pnp 2e.a off end // ACPI + device pnp 2e.b on // HW Monitor io 0x60 = 0x290 irq 0x70 = 5 end @@ -85,7 +85,7 @@ chip northbridge/amd/amdk8/root_complex register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 + end // device pci 18.0
device pci 18.0 on end device pci 18.0 on end diff --git a/src/mainboard/tyan/s2881/devicetree.cb b/src/mainboard/tyan/s2881/devicetree.cb index 7e836ff..f87dabe 100644 --- a/src/mainboard/tyan/s2881/devicetree.cb +++ b/src/mainboard/tyan/s2881/devicetree.cb @@ -7,15 +7,15 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on subsystemid 0x10f1 0x2881 inherit chip northbridge/amd/amdk8 - device pci 18.0 on end # link 0 - device pci 18.0 on end # link 1 - device pci 18.0 on # link 2 + device pci 18.0 on end // link 0 + device pci 18.0 on end // link 1 + device pci 18.0 on // link 2 chip southbridge/amd/amd8131 - # the on/off keyword is mandatory + // the on/off keyword is mandatory device pci 0.0 on - device pci 9.0 on end # Broadcom 5704 + device pci 9.0 on end // Broadcom 5704 device pci 9.1 on end - device pci a.0 on end # Adaptic + device pci a.0 on end // Adaptic device pci a.1 on end end device pci 0.1 on end @@ -23,53 +23,53 @@ chip northbridge/amd/amdk8/root_complex device pci 1.1 on end end chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge + // this "device pci 0.0" is the parent the next one + // PCI bridge device pci 0.0 on device pci 0.0 on end device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - device pci 5.0 on end # SiI + device pci 5.0 on end // SiI device pci 6.0 on end end device pci 1.0 on chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.3 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # CIR + device pnp 2e.6 off // CIR io 0x60 = 0x100 end - device pnp 2e.7 off # GAME_MIDI_GIPO1 + device pnp 2e.7 off // GAME_MIDI_GIPO1 io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.8 off end // GPIO2 + device pnp 2e.9 off end // GPIO3 + device pnp 2e.a off end // ACPI + device pnp 2e.b on // HW Monitor io 0x60 = 0x290 irq 0x70 = 5 end @@ -78,49 +78,49 @@ chip northbridge/amd/amdk8/root_complex device pci 1.1 on end device pci 1.2 on end device pci 1.3 on - chip drivers/generic/generic #dimm 0-0-0 + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 + chip drivers/generic/generic //dimm 0-0-1 device i2c 51 on end end - chip drivers/generic/generic #dimm 0-1-0 + chip drivers/generic/generic //dimm 0-1-0 device i2c 52 on end end - chip drivers/generic/generic #dimm 0-1-1 + chip drivers/generic/generic //dimm 0-1-1 device i2c 53 on end end - chip drivers/generic/generic #dimm 1-0-0 + chip drivers/generic/generic //dimm 1-0-0 device i2c 54 on end end - chip drivers/generic/generic #dimm 1-0-1 + chip drivers/generic/generic //dimm 1-0-1 device i2c 55 on end end - chip drivers/generic/generic #dimm 1-1-0 + chip drivers/generic/generic //dimm 1-1-0 device i2c 56 on end end - chip drivers/generic/generic #dimm 1-1-1 + chip drivers/generic/generic //dimm 1-1-1 device i2c 57 on end end - chip drivers/i2c/adt7463 # CPU0/1 temp, CPU1 vid, SYS FAN 1/2/3 + chip drivers/i2c/adt7463 // CPU0/1 temp, CPU1 vid, SYS FAN 1/2/3 device i2c 2d on end end - chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 4,CPU0 vid, CPU0/1 FAN + chip drivers/generic/generic // Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 4,CPU0 vid, CPU0/1 FAN device i2c 2a on end end - chip drivers/generic/generic # Winbond HWM 0x92 + chip drivers/generic/generic // Winbond HWM 0x92 device i2c 49 on end end - chip drivers/generic/generic # Winbond HWM 0x94 + chip drivers/generic/generic // Winbond HWM 0x94 device i2c 4a on end end - end # acpi + end // acpi device pci 1.5 off end device pci 1.6 off end register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 + end // device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end diff --git a/src/mainboard/tyan/s2882/devicetree.cb b/src/mainboard/tyan/s2882/devicetree.cb index 4f10752..04fc56d 100644 --- a/src/mainboard/tyan/s2882/devicetree.cb +++ b/src/mainboard/tyan/s2882/devicetree.cb @@ -8,14 +8,14 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on subsystemid 0x10f1 0x2882 inherit chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 + device pci 18.0 on // northbridge + // devices on link 0, link 0 == LDT 0 chip southbridge/amd/amd8131 - # the on/off keyword is mandatory + // the on/off keyword is mandatory device pci 0.0 on - device pci 6.0 on end # adaptec + device pci 6.0 on end // adaptec device pci 6.1 on end - device pci 9.0 on end # broadcom 5704 + device pci 9.0 on end // broadcom 5704 device pci 9.1 on end end device pci 0.1 on end @@ -23,56 +23,56 @@ chip northbridge/amd/amdk8/root_complex device pci 1.1 on end end chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge + // this "device pci 0.0" is the parent the next one + // PCI bridge device pci 0.0 on device pci 0.0 on end device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end device pci 5.0 on end - # chip drivers/ati/ragexl + // chip drivers/ati/ragexl device pci 6.0 on end - # end - device pci 8.0 on end #intel 10/100 + // end + device pci 8.0 on end //intel 10/100 end device pci 1.0 on chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.3 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # CIR + device pnp 2e.6 off // CIR io 0x60 = 0x100 end - device pnp 2e.7 off # GAME_MIDI_GIPO1 + device pnp 2e.7 off // GAME_MIDI_GIPO1 io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.8 off end // GPIO2 + device pnp 2e.9 off end // GPIO3 + device pnp 2e.a off end // ACPI + device pnp 2e.b on // HW Monitor io 0x60 = 0x290 irq 0x70 = 5 end @@ -82,37 +82,37 @@ chip northbridge/amd/amdk8/root_complex device pci 1.2 on end device pci 1.3 on end device pci 1.3 on -# chip drivers/generic/generic #dimm 0-0-0 -# device i2c 50 on end -# end -# chip drivers/generic/generic #dimm 0-0-1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #dimm 0-1-0 -# device i2c 52 on end -# end -# chip drivers/generic/generic #dimm 0-1-1 -# device i2c 53 on end -# end -# chip drivers/generic/generic #dimm 1-0-0 -# device i2c 54 on end -# end -# chip drivers/generic/generic #dimm 1-0-1 -# device i2c 55 on end -# end -# chip drivers/generic/generic #dimm 1-1-0 -# device i2c 56 on end -# end -# chip drivers/generic/generic #dimm 1-1-1 -# device i2c 57 on end -# end - end # acpi +// chip drivers/generic/generic #dimm 0-0-0 +// device i2c 50 on end +// end +// chip drivers/generic/generic #dimm 0-0-1 +// device i2c 51 on end +// end +// chip drivers/generic/generic #dimm 0-1-0 +// device i2c 52 on end +// end +// chip drivers/generic/generic #dimm 0-1-1 +// device i2c 53 on end +// end +// chip drivers/generic/generic #dimm 1-0-0 +// device i2c 54 on end +// end +// chip drivers/generic/generic #dimm 1-0-1 +// device i2c 55 on end +// end +// chip drivers/generic/generic #dimm 1-1-0 +// device i2c 56 on end +// end +// chip drivers/generic/generic #dimm 1-1-1 +// device i2c 57 on end +// end + end // acpi device pci 1.5 off end device pci 1.6 off end register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 + end // device pci 18.0
device pci 18.0 on end device pci 18.0 on end @@ -120,7 +120,7 @@ chip northbridge/amd/amdk8/root_complex device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end - end # NB - end #pci_domain + end // NB + end //pci_domain end
diff --git a/src/mainboard/tyan/s2885/devicetree.cb b/src/mainboard/tyan/s2885/devicetree.cb index fbb9680..13a7622 100644 --- a/src/mainboard/tyan/s2885/devicetree.cb +++ b/src/mainboard/tyan/s2885/devicetree.cb @@ -7,72 +7,72 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on subsystemid 0x10f1 0x2885 inherit chip northbridge/amd/amdk8 - device pci 18.0 on # LDT0 + device pci 18.0 on // LDT0 chip southbridge/amd/amd8151 - # the on/off keyword is mandatory + // the on/off keyword is mandatory device pci 0.0 on end device pci 1.0 on end end end - device pci 18.0 on end # LDT1 - device pci 18.0 on # northbridge - # devices on link 2, link 2 == LDT 2 + device pci 18.0 on end // LDT1 + device pci 18.0 on // northbridge + // devices on link 2, link 2 == LDT 2 chip southbridge/amd/amd8131 - # the on/off keyword is mandatory + // the on/off keyword is mandatory device pci 0.0 on - device pci 9.0 on end # broadcom 5703 + device pci 9.0 on end // broadcom 5703 end device pci 0.1 on end device pci 1.0 on end device pci 1.1 on end end chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge + // this "device pci 0.0" is the parent the next one + // PCI bridge device pci 0.0 on device pci 0.0 on end device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - device pci b.0 on end # SiI 3114 + device pci b.0 on end // SiI 3114 end device pci 1.0 on chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # Com2 + device pnp 2e.3 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # CIR + device pnp 2e.6 off // CIR io 0x60 = 0x100 end - device pnp 2e.7 off # GAME_MIDI_GIPO1 + device pnp 2e.7 off // GAME_MIDI_GIPO1 io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.8 off end // GPIO2 + device pnp 2e.9 off end // GPIO3 + device pnp 2e.a off end // ACPI + device pnp 2e.b on // HW Monitor io 0x60 = 0x290 irq 0x70 = 5 end @@ -81,52 +81,52 @@ chip northbridge/amd/amdk8/root_complex device pci 1.1 on end device pci 1.2 on end device pci 1.3 on - chip drivers/generic/generic #dimm 0-0-0 + chip drivers/generic/generic //dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 + chip drivers/generic/generic //dimm 0-0-1 device i2c 51 on end end - chip drivers/generic/generic #dimm 0-1-0 + chip drivers/generic/generic //dimm 0-1-0 device i2c 52 on end end - chip drivers/generic/generic #dimm 0-1-1 + chip drivers/generic/generic //dimm 0-1-1 device i2c 53 on end end - chip drivers/generic/generic #dimm 1-0-0 + chip drivers/generic/generic //dimm 1-0-0 device i2c 54 on end end - chip drivers/generic/generic #dimm 1-0-1 + chip drivers/generic/generic //dimm 1-0-1 device i2c 55 on end end - chip drivers/generic/generic #dimm 1-1-0 + chip drivers/generic/generic //dimm 1-1-0 device i2c 56 on end end - chip drivers/generic/generic #dimm 1-1-1 + chip drivers/generic/generic //dimm 1-1-1 device i2c 57 on end end - end # acpi + end // acpi device pci 1.5 on end device pci 1.6 off end register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 + end // device pci 18.0
device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end
- end #pci_domain + end //pci_domain
-# chip drivers/generic/debug -# device pnp 0.0 off end -# device pnp 0.1 off end -# device pnp 0.2 off end -# device pnp 0.3 off end -# device pnp 0.4 off end -# device pnp 0.5 on end -# end +// chip drivers/generic/debug +// device pnp 0.0 off end +// device pnp 0.1 off end +// device pnp 0.2 off end +// device pnp 0.3 off end +// device pnp 0.4 off end +// device pnp 0.5 on end +// end end
diff --git a/src/mainboard/tyan/s2891/devicetree.cb b/src/mainboard/tyan/s2891/devicetree.cb index d793640..2d2b118 100644 --- a/src/mainboard/tyan/s2891/devicetree.cb +++ b/src/mainboard/tyan/s2891/devicetree.cb @@ -1,125 +1,125 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device lapic_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_940 # CPU socket - device lapic 0 on end # Local APIC of the CPU +chip northbridge/amd/amdk8/root_complex // Root complex + device lapic_cluster 0 on // (L)APIC cluster + chip cpu/amd/socket_940 // CPU socket + device lapic 0 on end // Local APIC of the CPU end end - device pci_domain 0 on # PCI domain + device pci_domain 0 on // PCI domain subsystemid 0x10f1 0x2891 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy + chip northbridge/amd/amdk8 // Northbridge / RAM controller + device pci 18.0 on // Link 0 == LDT 0 + chip southbridge/nvidia/ck804 // Southbridge + device pci 0.0 on end // HT + device pci 1.0 on // LPC + chip superio/winbond/w83627hf // Super I/O + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel port + device pnp 2e.1 off // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.3 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # PS/2 keyboard & mouse + device pnp 2e.5 on // PS/2 keyboard & mouse io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # Consumer IR + device pnp 2e.6 off // Consumer IR io 0x60 = 0x100 end - device pnp 2e.7 off # Game port, MIDI, GPIO1 + device pnp 2e.7 off // Game port, MIDI, GPIO1 io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b off # Hardware monitor + device pnp 2e.8 off end // GPIO2 + device pnp 2e.9 off end // GPIO3 + device pnp 2e.a off end // ACPI + device pnp 2e.b off // Hardware monitor io 0x60 = 0x290 irq 0x70 = 5 end end end - device pci 1.1 on # SM 0 - # chip drivers/generic/generic # DIMM 0-0-0 - # device i2c 50 on end - # end - # chip drivers/generic/generic # DIMM 0-0-1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # DIMM 0-1-0 - # device i2c 52 on end - # end - # chip drivers/generic/generic # DIMM 0-1-1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # DIMM 1-0-0 - # device i2c 54 on end - # end - # chip drivers/generic/generic # DIMM 1-0-1 - # device i2c 55 on end - # end - # chip drivers/generic/generic # DIMM 1-1-0 - # device i2c 56 on end - # end - # chip drivers/generic/generic # DIMM 1-1-1 - # device i2c 57 on end - # end + device pci 1.1 on // SM 0 + // chip drivers/generic/generic # DIMM 0-0-0 + // device i2c 50 on end + // end + // chip drivers/generic/generic # DIMM 0-0-1 + // device i2c 51 on end + // end + // chip drivers/generic/generic # DIMM 0-1-0 + // device i2c 52 on end + // end + // chip drivers/generic/generic # DIMM 0-1-1 + // device i2c 53 on end + // end + // chip drivers/generic/generic # DIMM 1-0-0 + // device i2c 54 on end + // end + // chip drivers/generic/generic # DIMM 1-0-1 + // device i2c 55 on end + // end + // chip drivers/generic/generic # DIMM 1-1-0 + // device i2c 56 on end + // end + // chip drivers/generic/generic # DIMM 1-1-1 + // device i2c 57 on end + // end end - # device pci 1.1 on # SM 1 - # chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 - # device i2c 2d on end - # end - # chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 - # device i2c 2e on end - # end - # chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN - # device i2c 2a on end - # end - # chip drivers/generic/generic # Winbond HWM 0x92 - # device i2c 49 on end - # end - # chip drivers/generic/generic # Winbond HWM 0x94 - # device i2c 4a on end - # end - # end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 off end # ACI - device pci 4.1 off end # MCI - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on # PCI - # chip drivers/ati/ragexl + // device pci 1.1 on # SM 1 + // chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 + // device i2c 2d on end + // end + // chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 + // device i2c 2e on end + // end + // chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN + // device i2c 2a on end + // end + // chip drivers/generic/generic # Winbond HWM 0x92 + // device i2c 49 on end + // end + // chip drivers/generic/generic # Winbond HWM 0x94 + // device i2c 4a on end + // end + // end + device pci 2.0 on end // USB 1.1 + device pci 2.1 on end // USB 2 + device pci 4.0 off end // ACI + device pci 4.1 off end // MCI + device pci 6.0 on end // IDE + device pci 7.0 on end // SATA 1 + device pci 8.0 on end // SATA 0 + device pci 9.0 on // PCI + // chip drivers/ati/ragexl device pci 7.0 on end end - device pci a.0 off end # NIC - device pci b.0 off end # PCI E 3 - device pci c.0 off end # PCI E 2 - device pci d.0 on end # PCI E 1 - device pci e.0 on end # PCI E 0 + device pci a.0 off end // NIC + device pci b.0 off end // PCI E 3 + device pci c.0 off end // PCI E 2 + device pci d.0 on end // PCI E 1 + device pci e.0 on end // PCI E 0 register "ide0_enable" = "1" register "ide1_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" end end - device pci 18.0 on end # Link 1 - device pci 18.0 on # Link 2 == LDT 2 - chip southbridge/amd/amd8131 # Southbridge + device pci 18.0 on end // Link 1 + device pci 18.0 on // Link 2 == LDT 2 + chip southbridge/amd/amd8131 // Southbridge device pci 0.0 on end device pci 0.1 on end device pci 1.0 on @@ -134,15 +134,15 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 18.3 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end # chip name - # device pnp 0.1 off end # pci_regs_all - # device pnp 0.2 off end # mem - # device pnp 0.3 off end # cpuid - # device pnp 0.4 off end # smbus_regs_all - # device pnp 0.5 off end # dual core msr - # device pnp 0.6 off end # cache size - # device pnp 0.7 off end # tsc - # device pnp 0.8 on end # hard_reset - # end + // chip drivers/generic/debug + // device pnp 0.0 off end # chip name + // device pnp 0.1 off end # pci_regs_all + // device pnp 0.2 off end # mem + // device pnp 0.3 off end # cpuid + // device pnp 0.4 off end # smbus_regs_all + // device pnp 0.5 off end # dual core msr + // device pnp 0.6 off end # cache size + // device pnp 0.7 off end # tsc + // device pnp 0.8 on end # hard_reset + // end end diff --git a/src/mainboard/tyan/s2892/devicetree.cb b/src/mainboard/tyan/s2892/devicetree.cb index 3b999ca..a986ab2 100644 --- a/src/mainboard/tyan/s2892/devicetree.cb +++ b/src/mainboard/tyan/s2892/devicetree.cb @@ -1,132 +1,132 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device lapic_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_940 # CPU socket - device lapic 0 on end # Local APIC of the CPU +chip northbridge/amd/amdk8/root_complex // Root complex + device lapic_cluster 0 on // (L)APIC cluster + chip cpu/amd/socket_940 // CPU socket + device lapic 0 on end // Local APIC of the CPU end end - device pci_domain 0 on # PCI domain + device pci_domain 0 on // PCI domain subsystemid 0x10f1 0x2892 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 on # Floppy + chip northbridge/amd/amdk8 // Northbridge / RAM controller + device pci 18.0 on // Link 0 == LDT 0 + chip southbridge/nvidia/ck804 // Southbridge + device pci 0.0 on end // HT + device pci 1.0 on // LPC + chip superio/winbond/w83627hf // Super I/O + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Parallel port + device pnp 2e.1 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.3 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # PS/2 keyboard & mouse + device pnp 2e.5 on // PS/2 keyboard & mouse io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # Consumer IR + device pnp 2e.6 off // Consumer IR io 0x60 = 0x100 end - device pnp 2e.7 off # Game port, MIDI, GPIO1 + device pnp 2e.7 off // Game port, MIDI, GPIO1 io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor + device pnp 2e.8 off end // GPIO2 + device pnp 2e.9 off end // GPIO3 + device pnp 2e.a off end // ACPI + device pnp 2e.b on // Hardware monitor io 0x60 = 0x290 irq 0x70 = 5 end end end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 + device pci 1.1 on // SM 0 + chip drivers/generic/generic // DIMM 0-0-0 device i2c 50 on end end - chip drivers/generic/generic # DIMM 0-0-1 + chip drivers/generic/generic // DIMM 0-0-1 device i2c 51 on end end - chip drivers/generic/generic # DIMM 0-1-0 + chip drivers/generic/generic // DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 + chip drivers/generic/generic // DIMM 0-1-1 device i2c 53 on end end - chip drivers/generic/generic # DIMM 1-0-0 + chip drivers/generic/generic // DIMM 1-0-0 device i2c 54 on end end - chip drivers/generic/generic # DIMM 1-0-1 + chip drivers/generic/generic // DIMM 1-0-1 device i2c 55 on end end - chip drivers/generic/generic # DIMM 1-1-0 + chip drivers/generic/generic // DIMM 1-1-0 device i2c 56 on end end - chip drivers/generic/generic # DIMM 1-1-1 + chip drivers/generic/generic // DIMM 1-1-1 device i2c 57 on end end end - device pci 1.1 on # SM 1 - chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 + device pci 1.1 on // SM 1 + chip drivers/i2c/adm1027 // ADT7463A CPU0 temp, SYS FAN 2/3/4 device i2c 2d on end end - chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 + chip drivers/i2c/adm1027 // ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 device i2c 2e on end end - chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN + chip drivers/generic/generic // Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN device i2c 2a on end end - chip drivers/generic/generic # Winbond HWM 0x92 + chip drivers/generic/generic // Winbond HWM 0x92 device i2c 49 on end end - chip drivers/generic/generic # Winbond HWM 0x94 + chip drivers/generic/generic // Winbond HWM 0x94 device i2c 4a on end end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 off end # ACI - device pci 4.1 off end # MCI - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on # PCI - # chip drivers/ati/ragexl + device pci 2.0 on end // USB 1.1 + device pci 2.1 on end // USB 2 + device pci 4.0 off end // ACI + device pci 4.1 off end // MCI + device pci 6.0 on end // IDE + device pci 7.0 on end // SATA 1 + device pci 8.0 on end // SATA 0 + device pci 9.0 on // PCI + // chip drivers/ati/ragexl device pci 6.0 on end - # end + // end device pci 8.0 on end end - device pci a.0 off end # NIC - device pci b.0 off end # PCI E 3 - device pci c.0 off end # PCI E 2 - device pci d.0 on end # PCI E 1 - device pci e.0 on end # PCI E 0 + device pci a.0 off end // NIC + device pci b.0 off end // PCI E 3 + device pci c.0 off end // PCI E 2 + device pci d.0 on end // PCI E 1 + device pci e.0 on end // PCI E 0 register "ide0_enable" = "1" register "ide1_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" end end - device pci 18.0 on end # Link 1 - device pci 18.0 on # Link 2 == LDT 2 - chip southbridge/amd/amd8131 # Southbridge + device pci 18.0 on end // Link 1 + device pci 18.0 on // Link 2 == LDT 2 + chip southbridge/amd/amd8131 // Southbridge device pci 0.0 on end device pci 0.1 on end device pci 1.0 on - device pci 9.0 on end # Broadcom 5704 + device pci 9.0 on end // Broadcom 5704 device pci 9.1 on end end device pci 1.1 on end @@ -137,12 +137,12 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 18.3 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end - # device pnp 0.1 off end - # device pnp 0.2 off end - # device pnp 0.3 off end - # device pnp 0.4 off end - # device pnp 0.5 on end - # end + // chip drivers/generic/debug + // device pnp 0.0 off end + // device pnp 0.1 off end + // device pnp 0.2 off end + // device pnp 0.3 off end + // device pnp 0.4 off end + // device pnp 0.5 on end + // end end diff --git a/src/mainboard/tyan/s2895/devicetree.cb b/src/mainboard/tyan/s2895/devicetree.cb index 7d7abc3..fbbde6d 100644 --- a/src/mainboard/tyan/s2895/devicetree.cb +++ b/src/mainboard/tyan/s2895/devicetree.cb @@ -1,115 +1,115 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device lapic_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_940 # CPU socket - device lapic 0 on end # Local APIC of the CPU +chip northbridge/amd/amdk8/root_complex // Root complex + device lapic_cluster 0 on // (L)APIC cluster + chip cpu/amd/socket_940 // CPU socket + device lapic 0 on end // Local APIC of the CPU end end - device pci_domain 0 on # PCI domain + device pci_domain 0 on // PCI domain subsystemid 0x10f1 0x2895 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/smsc/lpc47b397 # Super I/O - device pnp 2e.0 on # Floppy + chip northbridge/amd/amdk8 // Northbridge / RAM controller + device pci 18.0 on // Link 0 == LDT 0 + chip southbridge/nvidia/ck804 // Southbridge + device pci 0.0 on end // HT + device pci 1.0 on // LPC + chip superio/smsc/lpc47b397 // Super I/O + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.3 on # Parallel port + device pnp 2e.3 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 4 end - device pnp 2e.4 on # Com1 + device pnp 2e.4 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.5 off # Com2 + device pnp 2e.5 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.7 on # PS/2 keyboard & mouse + device pnp 2e.7 on // PS/2 keyboard & mouse io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.8 on # Hardware monitor + device pnp 2e.8 on // Hardware monitor io 0x60 = 0x480 - chip drivers/generic/generic # LM95221 CPU temp + chip drivers/generic/generic // LM95221 CPU temp device i2c 2b on end end - chip drivers/generic/generic # EMCT03 + chip drivers/generic/generic // EMCT03 device i2c 54 on end end end - device pnp 2e.a on # RT + device pnp 2e.a on // RT io 0x60 = 0x400 end end end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 + device pci 1.1 on // SM 0 + chip drivers/generic/generic // DIMM 0-0-0 device i2c 50 on end end - chip drivers/generic/generic # DIMM 0-0-1 + chip drivers/generic/generic // DIMM 0-0-1 device i2c 51 on end end - chip drivers/generic/generic # DIMM 0-1-0 + chip drivers/generic/generic // DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 + chip drivers/generic/generic // DIMM 0-1-1 device i2c 53 on end end - chip drivers/generic/generic # DIMM 1-0-0 + chip drivers/generic/generic // DIMM 1-0-0 device i2c 54 on end end - chip drivers/generic/generic # DIMM 1-0-1 + chip drivers/generic/generic // DIMM 1-0-1 device i2c 55 on end end - chip drivers/generic/generic # DIMM 1-1-0 + chip drivers/generic/generic // DIMM 1-1-0 device i2c 56 on end end - chip drivers/generic/generic # DIMM 1-1-1 + chip drivers/generic/generic // DIMM 1-1-1 device i2c 57 on end end end - device pci 1.1 on # SM 1 - chip drivers/generic/generic # MAC EEPROM + device pci 1.1 on // SM 1 + chip drivers/generic/generic // MAC EEPROM device i2c 51 on end end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # ACI - device pci 4.1 off end # MCI - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on end # PCI - device pci a.0 on end # NIC - device pci b.0 off end # PCI E 3 - device pci c.0 off end # PCI E 2 - device pci d.0 off end # PCI E 1 - device pci e.0 on end # PCI E 0 + device pci 2.0 on end // USB 1.1 + device pci 2.1 on end // USB 2 + device pci 4.0 on end // ACI + device pci 4.1 off end // MCI + device pci 6.0 on end // IDE + device pci 7.0 on end // SATA 1 + device pci 8.0 on end // SATA 0 + device pci 9.0 on end // PCI + device pci a.0 on end // NIC + device pci b.0 off end // PCI E 3 + device pci c.0 off end // PCI E 2 + device pci d.0 off end // PCI E 1 + device pci e.0 on end // PCI E 0 register "ide0_enable" = "1" register "ide1_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 + // 1: SMBus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" end end - device pci 18.0 on end # Link 1 - device pci 18.0 on # Link 2 == LDT 2 - chip southbridge/amd/amd8131 # Southbridge + device pci 18.0 on end // Link 1 + device pci 18.0 on // Link 2 == LDT 2 + chip southbridge/amd/amd8131 // Southbridge device pci 0.0 on end device pci 0.1 on end device pci 1.0 on - device pci 6.0 on end # LSI SCSI + device pci 6.0 on end // LSI SCSI device pci 6.1 on end end device pci 1.1 on end @@ -119,26 +119,26 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 18.2 on end device pci 18.3 on end end - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 19.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on end # LPC - device pci 1.1 off end # SM - device pci 2.0 off end # USB 1.1 - device pci 2.1 off end # USB 2 - device pci 4.0 off end # ACI - device pci 4.1 off end # MCI - device pci 6.0 off end # IDE - device pci 7.0 off end # SATA 1 - device pci 8.0 off end # SATA 0 - device pci 9.0 off end # PCI - device pci a.0 on end # NIC - device pci b.0 off end # PCI E 3 - device pci c.0 off end # PCI E 2 - device pci d.0 off end # PCI E 1 - device pci e.0 on end # PCI E 0 - # 1: SMBus under 2e.8, 2: SM0 3: SM1 + chip northbridge/amd/amdk8 // Northbridge / RAM controller + device pci 19.0 on // Link 0 == LDT 0 + chip southbridge/nvidia/ck804 // Southbridge + device pci 0.0 on end // HT + device pci 1.0 on end // LPC + device pci 1.1 off end // SM + device pci 2.0 off end // USB 1.1 + device pci 2.1 off end // USB 2 + device pci 4.0 off end // ACI + device pci 4.1 off end // MCI + device pci 6.0 off end // IDE + device pci 7.0 off end // SATA 1 + device pci 8.0 off end // SATA 0 + device pci 9.0 off end // PCI + device pci a.0 on end // NIC + device pci b.0 off end // PCI E 3 + device pci c.0 off end // PCI E 2 + device pci d.0 off end // PCI E 1 + device pci e.0 on end // PCI E 0 + // 1: SMBus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" end @@ -150,14 +150,14 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 19.3 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end # chip name - # device pnp 0.1 off end # pci_regs_all - # device pnp 0.2 off end # mem - # device pnp 0.3 off end # cpuid - # device pnp 0.4 on end # smbus_regs_all - # device pnp 0.5 off end # dual core msr - # device pnp 0.6 off end # cache size - # device pnp 0.7 off end # tsc - # end + // chip drivers/generic/debug + // device pnp 0.0 off end # chip name + // device pnp 0.1 off end # pci_regs_all + // device pnp 0.2 off end # mem + // device pnp 0.3 off end # cpuid + // device pnp 0.4 on end # smbus_regs_all + // device pnp 0.5 off end # dual core msr + // device pnp 0.6 off end # cache size + // device pnp 0.7 off end # tsc + // end end diff --git a/src/mainboard/tyan/s2912/devicetree.cb b/src/mainboard/tyan/s2912/devicetree.cb index 0ce4a48..c05d9c9 100644 --- a/src/mainboard/tyan/s2912/devicetree.cb +++ b/src/mainboard/tyan/s2912/devicetree.cb @@ -1,131 +1,131 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device lapic_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F # CPU socket - device lapic 0 on end # Local APIC of the CPU +chip northbridge/amd/amdk8/root_complex // Root complex + device lapic_cluster 0 on // (L)APIC cluster + chip cpu/amd/socket_F // CPU socket + device lapic 0 on end // Local APIC of the CPU end end - device pci_domain 0 on # PCI domain + device pci_domain 0 on // PCI domain subsystemid 0x10f1 0x2912 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller + chip northbridge/amd/amdk8 // Northbridge / RAM controller device pci 18.0 on end device pci 18.0 on end device pci 18.0 on - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy + chip southbridge/nvidia/mcp55 // Southbridge + device pci 0.0 on end // HT + device pci 1.0 on // LPC + chip superio/winbond/w83627hf // Super I/O + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel port + device pnp 2e.1 off // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # Com2 + device pnp 2e.3 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # PS/2 keyboard + device pnp 2e.5 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # SFI + device pnp 2e.6 off // SFI io 0x62 = 0x100 end - device pnp 2e.7 off # GPIO, game port, MIDI + device pnp 2e.7 off // GPIO, game port, MIDI io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor + device pnp 2e.8 off end // WDTO PLED + device pnp 2e.9 off end // GPIO SUSLED + device pnp 2e.a off end // ACPI + device pnp 2e.b on // Hardware monitor io 0x60 = 0x290 irq 0x70 = 5 end end end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 + device pci 1.1 on // SM 0 + chip drivers/generic/generic // DIMM 0-0-0 device i2c 50 on end end - chip drivers/generic/generic # DIMM 0-0-1 + chip drivers/generic/generic // DIMM 0-0-1 device i2c 51 on end end - chip drivers/generic/generic # DIMM 0-1-0 + chip drivers/generic/generic // DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 + chip drivers/generic/generic // DIMM 0-1-1 device i2c 53 on end end - chip drivers/generic/generic # DIMM 1-0-0 + chip drivers/generic/generic // DIMM 1-0-0 device i2c 54 on end end - chip drivers/generic/generic # DIMM 1-0-1 + chip drivers/generic/generic // DIMM 1-0-1 device i2c 55 on end end - chip drivers/generic/generic # DIMM 1-1-0 + chip drivers/generic/generic // DIMM 1-1-0 device i2c 56 on end end - chip drivers/generic/generic # DIMM 1-1-1 + chip drivers/generic/generic // DIMM 1-1-1 device i2c 57 on end end end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM + device pci 1.1 on // SM 1 + // PCI device SMBus address will + // depend on addon PCI device, do + // we need to scan_smbus_bus? + // chip drivers/generic/generic # PCIXA slot 1 + // device i2c 50 on end + // end + // chip drivers/generic/generic # PCIXB slot 1 + // device i2c 51 on end + // end + // chip drivers/generic/generic # PCIXB slot 2 + // device i2c 52 on end + // end + // chip drivers/generic/generic # PCI slot 1 + // device i2c 53 on end + // end + // chip drivers/generic/generic # Master MCP55 PCI-E + // device i2c 54 on end + // end + // chip drivers/generic/generic # Slave MCP55 PCI-E + // device i2c 55 on end + // end + chip drivers/generic/generic // MAC EEPROM device i2c 51 on end end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on end # PCI - device pci 6.1 off end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 off end # PCI E 1 - device pci f.0 on end # PCI E 0 + device pci 2.0 on end // USB 1.1 + device pci 2.1 on end // USB 2 + device pci 4.0 on end // IDE + device pci 5.0 on end // SATA 0 + device pci 5.1 on end // SATA 1 + device pci 5.2 on end // SATA 2 + device pci 6.0 on end // PCI + device pci 6.1 off end // AZA + device pci 8.0 on end // NIC + device pci 9.0 on end // NIC + device pci a.0 on end // PCI E 5 + device pci b.0 off end // PCI E 4 + device pci c.0 off end // PCI E 3 + device pci d.0 on end // PCI E 2 + device pci e.0 off end // PCI E 1 + device pci f.0 on end // PCI E 0 register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 + // 1: SMBus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" end @@ -135,16 +135,16 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 18.3 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end # chip name - # device pnp 0.1 on end # pci_regs_all - # device pnp 0.2 on end # mem - # device pnp 0.3 off end # cpuid - # device pnp 0.4 on end # smbus_regs_all - # device pnp 0.5 off end # dual core msr - # device pnp 0.6 off end # cache size - # device pnp 0.7 off end # tsc - # device pnp 0.8 off end # io - # device pnp 0.9 off end # io - # end + // chip drivers/generic/debug + // device pnp 0.0 off end # chip name + // device pnp 0.1 on end # pci_regs_all + // device pnp 0.2 on end # mem + // device pnp 0.3 off end # cpuid + // device pnp 0.4 on end # smbus_regs_all + // device pnp 0.5 off end # dual core msr + // device pnp 0.6 off end # cache size + // device pnp 0.7 off end # tsc + // device pnp 0.8 off end # io + // device pnp 0.9 off end # io + // end end diff --git a/src/mainboard/tyan/s2912_fam10/devicetree.cb b/src/mainboard/tyan/s2912_fam10/devicetree.cb index 43bdeb6..d4678ad 100644 --- a/src/mainboard/tyan/s2912_fam10/devicetree.cb +++ b/src/mainboard/tyan/s2912_fam10/devicetree.cb @@ -1,133 +1,133 @@ -chip northbridge/amd/amdfam10/root_complex # Root complex - device lapic_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F_1207 # CPU socket - device lapic 0 on end # Local APIC of the CPU +chip northbridge/amd/amdfam10/root_complex // Root complex + device lapic_cluster 0 on // (L)APIC cluster + chip cpu/amd/socket_F_1207 // CPU socket + device lapic 0 on end // Local APIC of the CPU end end - device pci_domain 0 on # PCI domain + device pci_domain 0 on // PCI domain subsystemid 0x10f1 0x2912 inherit - chip northbridge/amd/amdfam10 # Northbridge / RAM controller + chip northbridge/amd/amdfam10 // Northbridge / RAM controller device pci 18.0 on end device pci 18.0 on end - device pci 18.0 on # SB on link 2 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy + device pci 18.0 on // SB on link 2 + chip southbridge/nvidia/mcp55 // Southbridge + device pci 0.0 on end // HT + device pci 1.0 on // LPC + chip superio/winbond/w83627hf // Super I/O + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel port + device pnp 2e.1 off // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # Com2 + device pnp 2e.3 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # PS/2 keyboard + device pnp 2e.5 on // PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # SFI + device pnp 2e.6 off // SFI io 0x62 = 0x100 end - device pnp 2e.7 off # GPIO, game port, MIDI + device pnp 2e.7 off // GPIO, game port, MIDI io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor + device pnp 2e.8 off end // WDTO PLED + device pnp 2e.9 off end // GPIO SUSLED + device pnp 2e.a off end // ACPI + device pnp 2e.b on // Hardware monitor io 0x60 = 0x290 irq 0x70 = 5 end end end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 + device pci 1.1 on // SM 0 + chip drivers/generic/generic // DIMM 0-0-0 device i2c 50 on end end - chip drivers/generic/generic # DIMM 0-0-1 + chip drivers/generic/generic // DIMM 0-0-1 device i2c 51 on end end - chip drivers/generic/generic # DIMM 0-1-0 + chip drivers/generic/generic // DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 + chip drivers/generic/generic // DIMM 0-1-1 device i2c 53 on end end - chip drivers/generic/generic # DIMM 1-0-0 + chip drivers/generic/generic // DIMM 1-0-0 device i2c 54 on end end - chip drivers/generic/generic # DIMM 1-0-1 + chip drivers/generic/generic // DIMM 1-0-1 device i2c 55 on end end - chip drivers/generic/generic # DIMM 1-1-0 + chip drivers/generic/generic // DIMM 1-1-0 device i2c 56 on end end - chip drivers/generic/generic # DIMM 1-1-1 + chip drivers/generic/generic // DIMM 1-1-1 device i2c 57 on end end end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM + device pci 1.1 on // SM 1 + // PCI device SMBus address will + // depend on addon PCI device, do + // we need to scan_smbus_bus? + // chip drivers/generic/generic # PCIXA slot 1 + // device i2c 50 on end + // end + // chip drivers/generic/generic # PCIXB slot 1 + // device i2c 51 on end + // end + // chip drivers/generic/generic # PCIXB slot 2 + // device i2c 52 on end + // end + // chip drivers/generic/generic # PCI slot 1 + // device i2c 53 on end + // end + // chip drivers/generic/generic # Master MCP55 PCI-E + // device i2c 54 on end + // end + // chip drivers/generic/generic # Slave MCP55 PCI-E + // device i2c 55 on end + // end + chip drivers/generic/generic // MAC EEPROM device i2c 51 on end end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # PCI + device pci 2.0 on end // USB 1.1 + device pci 2.1 on end // USB 2 + device pci 4.0 on end // IDE + device pci 5.0 on end // SATA 0 + device pci 5.1 on end // SATA 1 + device pci 5.2 on end // SATA 2 + device pci 6.0 on // PCI device pci 4.0 on end end - device pci 6.1 off end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 off end # PCI E 1 - device pci f.0 on end # PCI E 0 + device pci 6.1 off end // AZA + device pci 8.0 on end // NIC + device pci 9.0 on end // NIC + device pci a.0 on end // PCI E 5 + device pci b.0 off end // PCI E 4 + device pci c.0 off end // PCI E 3 + device pci d.0 on end // PCI E 2 + device pci e.0 off end // PCI E 1 + device pci f.0 on end // PCI E 0 register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 + // 1: SMBus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" end @@ -138,16 +138,16 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device pci 18.4 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end # chip name - # device pnp 0.1 on end # pci_regs_all - # device pnp 0.2 on end # mem - # device pnp 0.3 off end # cpuid - # device pnp 0.4 on end # smbus_regs_all - # device pnp 0.5 off end # dual core msr - # device pnp 0.6 off end # cache size - # device pnp 0.7 off end # tsc - # device pnp 0.8 off end # io - # device pnp 0.9 off end # io - # end + // chip drivers/generic/debug + // device pnp 0.0 off end # chip name + // device pnp 0.1 on end # pci_regs_all + // device pnp 0.2 on end # mem + // device pnp 0.3 off end # cpuid + // device pnp 0.4 on end # smbus_regs_all + // device pnp 0.5 off end # dual core msr + // device pnp 0.6 off end # cache size + // device pnp 0.7 off end # tsc + // device pnp 0.8 off end # io + // device pnp 0.9 off end # io + // end end diff --git a/src/mainboard/tyan/s4880/devicetree.cb b/src/mainboard/tyan/s4880/devicetree.cb index e1aa23a..e946fe6 100644 --- a/src/mainboard/tyan/s4880/devicetree.cb +++ b/src/mainboard/tyan/s4880/devicetree.cb @@ -8,18 +8,18 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on subsystemid 0x10f1 0x4880 inherit chip northbridge/amd/amdk8 - device pci 18.0 on end # LDT0 - device pci 18.0 on end # LDT1 - device pci 18.0 on # northbridge - # devices on link 2, link 2 == LDT 2 + device pci 18.0 on end // LDT0 + device pci 18.0 on end // LDT1 + device pci 18.0 on // northbridge + // devices on link 2, link 2 == LDT 2 chip southbridge/amd/amd8131 - # the on/off keyword is mandatory + // the on/off keyword is mandatory device pci 0.0 on -# chip drivers/lsi/53c1030 -# device pci 4.0 on end -# device pci 4.1 on end -# register "fw_address" = "0xfff8c000" -# end +// chip drivers/lsi/53c1030 +// device pci 4.0 on end +// device pci 4.1 on end +// register "fw_address" = "0xfff8c000" +// end device pci 9.0 on end device pci 9.1 on end end @@ -28,8 +28,8 @@ chip northbridge/amd/amdk8/root_complex device pci 1.1 on end end chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge + // this "device pci 0.0" is the parent the next one + // PCI bridge device pci 0.0 on device pci 0.0 on end device pci 0.1 on end @@ -39,41 +39,41 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.0 on chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.3 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # CIR + device pnp 2e.6 off // CIR io 0x60 = 0x100 end - device pnp 2e.7 off # GAME_MIDI_GIPO1 + device pnp 2e.7 off // GAME_MIDI_GIPO1 io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.8 off end // GPIO2 + device pnp 2e.9 off end // GPIO3 + device pnp 2e.a off end // ACPI + device pnp 2e.b on // HW Monitor io 0x60 = 0x290 irq 0x70 = 5 end @@ -87,13 +87,13 @@ chip northbridge/amd/amdk8/root_complex register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 + end // device pci 18.0
device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end
- end #pci_domain + end //pci_domain end
diff --git a/src/mainboard/tyan/s4882/devicetree.cb b/src/mainboard/tyan/s4882/devicetree.cb index 767def9..6b2c9d6 100644 --- a/src/mainboard/tyan/s4882/devicetree.cb +++ b/src/mainboard/tyan/s4882/devicetree.cb @@ -7,18 +7,18 @@ chip northbridge/amd/amdk8/root_complex device pci_domain 0 on subsystemid 0x10f1 0x4882 inherit chip northbridge/amd/amdk8 - device pci 18.0 on end # LDT0 - device pci 18.0 on # northbridge - # devices on link 1, link 1 == LDT 1 + device pci 18.0 on end // LDT0 + device pci 18.0 on // northbridge + // devices on link 1, link 1 == LDT 1 chip southbridge/amd/amd8131 - # the on/off keyword is mandatory + // the on/off keyword is mandatory device pci 0.0 on -# chip drivers/lsi/53c1030 -# device pci 4.0 on end -# device pci 4.1 on end -# register "fw_address" = "0xfff8c000" -# end - device pci 9.0 on end #Broadcom +// chip drivers/lsi/53c1030 +// device pci 4.0 on end +// device pci 4.1 on end +// register "fw_address" = "0xfff8c000" +// end + device pci 9.0 on end //Broadcom device pci 9.1 on end end device pci 0.1 on end @@ -26,55 +26,55 @@ chip northbridge/amd/amdk8/root_complex device pci 1.1 on end end chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge + // this "device pci 0.0" is the parent the next one + // PCI bridge device pci 0.0 on device pci 0.0 on end device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - #chip drivers/ati/ragexl + //chip drivers/ati/ragexl device pci 6.0 on end - #end - device pci 5.0 on end #SiI + //end + device pci 5.0 on end //SiI end device pci 1.0 on chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # Com2 + device pnp 2e.3 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # CIR + device pnp 2e.6 off // CIR io 0x60 = 0x100 end - device pnp 2e.7 off # GAME_MIDI_GIPO1 + device pnp 2e.7 off // GAME_MIDI_GIPO1 io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.8 off end // GPIO2 + device pnp 2e.9 off end // GPIO3 + device pnp 2e.a off end // ACPI + device pnp 2e.b on // HW Monitor io 0x60 = 0x290 irq 0x70 = 5 end @@ -83,106 +83,106 @@ chip northbridge/amd/amdk8/root_complex device pci 1.1 on end device pci 1.2 on end device pci 1.3 on -# chip drivers/i2c/i2cmux # pca9556 smbus mux -# device i2c 18 on #0 pca9516 2, 1 -# chip drivers/i2c/lm63 #cpu0 temp -# device i2c 4c on end -# end -# end -# device i2c 18 on #1 pca9516 1, 1 -# chip drivers/generic/generic #dimm 1-0-0 -# device i2c 50 on end -# end -# chip drivers/generic/generic #dimm 1-0-1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #dimm 1-1-0 -# device i2c 52 on end -# end -# chip drivers/generic/generic #dimm 1-1-1 -# device i2c 53 on end -# end -# end -# device i2c 18 on #2 pca9516 1, 2 -# chip drivers/generic/generic #dimm 0-0-0 -# device i2c 50 on end -# end -# chip drivers/generic/generic #dimm 0-0-1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #dimm 0-1-0 -# device i2c 52 on end -# end -# chip drivers/generic/generic #dimm 0-1-1 -# device i2c 53 on end -# end -# end -# device i2c 18 on #3 pca9516 1, 3 -# chip drivers/generic/generic #dimm 3-0-0 -# device i2c 50 on end -# end -# chip drivers/generic/generic #dimm 3-0-1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #dimm 3-1-0 -# device i2c 52 on end -# end -# chip drivers/generic/generic #dimm 3-1-1 -# device i2c 53 on end -# end -# end -# device i2c 18 on #4 pca9516 1, 4 -# chip drivers/generic/generic #dimm 2-0-0 -# device i2c 50 on end -# end -# chip drivers/generic/generic #dimm 2-0-1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #dimm 2-1-0 -# device i2c 52 on end -# end -# chip drivers/generic/generic #dimm 2-1-1 -# device i2c 53 on end -# end -# end -# device i2c 18 on #5 pca9516 2, 2 -# chip drivers/i2c/lm63 #cpu1 temp -# device i2c 4c on end -# end -# end -# device i2c 18 on #6 pca9516 2, 3 -# chip drivers/i2c/lm63 #cpu2 temp -# device i2c 4c on end -# end -# end -# device i2c 18 on #7 pca9516 2, 4 -# chip drivers/i2c/lm63 #cpu3 temp -# device i2c 4c on end -# end -# end -# end # i2cmux -# chip drivers/i2c/adm1027 # ADM1027 CPU1 vid and System FAN... -# device i2c 2e on end -# end -# chip drivers/generic/generic # Winbond HWM 0x54 CPU0 vid -# device i2c 2a on end -# end -# chip drivers/generic/generic # Winbond HWM 0x92 -# device i2c 49 on end -# end -# chip drivers/generic/generic # Winbond HWM 0x94 -# device i2c 4a on end -# end -# chip drivers/generic/generic # ?? -# device i2c 69 on end -# end - end # acpi +// chip drivers/i2c/i2cmux # pca9556 smbus mux +// device i2c 18 on #0 pca9516 2, 1 +// chip drivers/i2c/lm63 #cpu0 temp +// device i2c 4c on end +// end +// end +// device i2c 18 on #1 pca9516 1, 1 +// chip drivers/generic/generic #dimm 1-0-0 +// device i2c 50 on end +// end +// chip drivers/generic/generic #dimm 1-0-1 +// device i2c 51 on end +// end +// chip drivers/generic/generic #dimm 1-1-0 +// device i2c 52 on end +// end +// chip drivers/generic/generic #dimm 1-1-1 +// device i2c 53 on end +// end +// end +// device i2c 18 on #2 pca9516 1, 2 +// chip drivers/generic/generic #dimm 0-0-0 +// device i2c 50 on end +// end +// chip drivers/generic/generic #dimm 0-0-1 +// device i2c 51 on end +// end +// chip drivers/generic/generic #dimm 0-1-0 +// device i2c 52 on end +// end +// chip drivers/generic/generic #dimm 0-1-1 +// device i2c 53 on end +// end +// end +// device i2c 18 on #3 pca9516 1, 3 +// chip drivers/generic/generic #dimm 3-0-0 +// device i2c 50 on end +// end +// chip drivers/generic/generic #dimm 3-0-1 +// device i2c 51 on end +// end +// chip drivers/generic/generic #dimm 3-1-0 +// device i2c 52 on end +// end +// chip drivers/generic/generic #dimm 3-1-1 +// device i2c 53 on end +// end +// end +// device i2c 18 on #4 pca9516 1, 4 +// chip drivers/generic/generic #dimm 2-0-0 +// device i2c 50 on end +// end +// chip drivers/generic/generic #dimm 2-0-1 +// device i2c 51 on end +// end +// chip drivers/generic/generic #dimm 2-1-0 +// device i2c 52 on end +// end +// chip drivers/generic/generic #dimm 2-1-1 +// device i2c 53 on end +// end +// end +// device i2c 18 on #5 pca9516 2, 2 +// chip drivers/i2c/lm63 #cpu1 temp +// device i2c 4c on end +// end +// end +// device i2c 18 on #6 pca9516 2, 3 +// chip drivers/i2c/lm63 #cpu2 temp +// device i2c 4c on end +// end +// end +// device i2c 18 on #7 pca9516 2, 4 +// chip drivers/i2c/lm63 #cpu3 temp +// device i2c 4c on end +// end +// end +// end # i2cmux +// chip drivers/i2c/adm1027 # ADM1027 CPU1 vid and System FAN... +// device i2c 2e on end +// end +// chip drivers/generic/generic # Winbond HWM 0x54 CPU0 vid +// device i2c 2a on end +// end +// chip drivers/generic/generic # Winbond HWM 0x92 +// device i2c 49 on end +// end +// chip drivers/generic/generic # Winbond HWM 0x94 +// device i2c 4a on end +// end +// chip drivers/generic/generic # ?? +// device i2c 69 on end +// end + end // acpi device pci 1.5 off end device pci 1.6 off end register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 + end // device pci 18.0
device pci 18.0 on end
@@ -192,15 +192,15 @@ chip northbridge/amd/amdk8/root_complex end
end -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 off end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 on end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 on end # dual core msr -# device pnp 0.6 on end # cache size -# device pnp 0.7 on end # tsc -# end +// chip drivers/generic/debug +// device pnp 0.0 off end # chip name +// device pnp 0.1 off end # pci_regs_all +// device pnp 0.2 off end # mem +// device pnp 0.3 on end # cpuid +// device pnp 0.4 off end # smbus_regs_all +// device pnp 0.5 on end # dual core msr +// device pnp 0.6 on end # cache size +// device pnp 0.7 on end # tsc +// end end
diff --git a/src/mainboard/via/epia-cn/devicetree.cb b/src/mainboard/via/epia-cn/devicetree.cb index 727ccc5..9868bba 100644 --- a/src/mainboard/via/epia-cn/devicetree.cb +++ b/src/mainboard/via/epia-cn/devicetree.cb @@ -1,61 +1,61 @@ -chip northbridge/via/cn700 # Northbridge - device pci_domain 0 on # PCI domain - device pci 0.0 on end # AGP Bridge - device pci 0.1 on end # Error Reporting - device pci 0.2 on end # Host Bus Control - device pci 0.3 on end # Memory Controller - device pci 0.4 on end # Power Management - device pci 0.7 on end # V-Link Controller - device pci 1.0 on end # PCI Bridge - chip southbridge/via/vt8237r # Southbridge - # Enable both IDE channels. +chip northbridge/via/cn700 // Northbridge + device pci_domain 0 on // PCI domain + device pci 0.0 on end // AGP Bridge + device pci 0.1 on end // Error Reporting + device pci 0.2 on end // Host Bus Control + device pci 0.3 on end // Memory Controller + device pci 0.4 on end // Power Management + device pci 0.7 on end // V-Link Controller + device pci 1.0 on end // PCI Bridge + chip southbridge/via/vt8237r // Southbridge + // Enable both IDE channels. register "ide0_enable" = "1" register "ide1_enable" = "1" - # Both cables are 40pin. + // Both cables are 40pin. register "ide0_80pin_cable" = "0" register "ide1_80pin_cable" = "0" - device pci f.0 on end # IDE + device pci f.0 on end // IDE register "fn_ctrl_lo" = "0x80" register "fn_ctrl_hi" = "0x1d" - device pci 10.0 on end # OHCI - device pci 10.1 on end # OHCI - device pci 10.2 on end # OHCI - device pci 10.3 on end # OHCI - device pci 10.4 on end # EHCI - device pci 10.5 on end # UDCI - device pci 11.0 on # Southbridge LPC - chip superio/via/vt1211 # Super I/O - device pnp 2e.0 off # Floppy + device pci 10.0 on end // OHCI + device pci 10.1 on end // OHCI + device pci 10.2 on end // OHCI + device pci 10.3 on end // OHCI + device pci 10.4 on end // EHCI + device pci 10.5 on end // UDCI + device pci 11.0 on // Southbridge LPC + chip superio/via/vt1211 // Super I/O + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Parallel Port + device pnp 2e.1 on // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 end - device pnp 2e.2 on # COM1 + device pnp 2e.2 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # COM2 + device pnp 2e.3 on // COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.b on # HWM + device pnp 2e.b on // HWM io 0x60 = 0xec00 end end end - device pci 11.5 on end # AC'97 audio - # device pci 11.6 off end # AC'97 Modem - device pci 12.0 on end # Ethernet + device pci 11.5 on end // AC'97 audio + // device pci 11.6 off end # AC'97 Modem + device pci 12.0 on end // Ethernet end end - device lapic_cluster 0 on # APIC cluster - chip cpu/via/model_c7 # VIA C7 - device lapic 0 on end # APIC + device lapic_cluster 0 on // APIC cluster + chip cpu/via/model_c7 // VIA C7 + device lapic 0 on end // APIC end end end diff --git a/src/mainboard/via/epia-m/devicetree.cb b/src/mainboard/via/epia-m/devicetree.cb index cc4a39d..91db63e 100644 --- a/src/mainboard/via/epia-m/devicetree.cb +++ b/src/mainboard/via/epia-m/devicetree.cb @@ -13,45 +13,45 @@ chip northbridge/via/vt8623
chip southbridge/via/vt8235
- device pci 10.0 on end # USB 1.1 - device pci 10.1 on end # USB 1.1 - device pci 10.2 on end # USB 1.1 - device pci 10.3 on end # USB 2 + device pci 10.0 on end // USB 1.1 + device pci 10.1 on end // USB 1.1 + device pci 10.2 on end // USB 1.1 + device pci 10.3 on end // USB 2
- device pci 11.0 on # Southbridge + device pci 11.0 on // Southbridge chip superio/via/vt1211 - device pnp 2e.0 on # Floppy + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Parallel Port + device pnp 2e.1 on // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 end - device pnp 2e.2 on # COM1 + device pnp 2e.2 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # COM2 + device pnp 2e.3 on // COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.b on # HWM + device pnp 2e.b on // HWM io 0x60 = 0xec00 end
end end
- device pci 11.1 on end # IDE - # 2-4 non existant? - device pci 11.5 on end # AC97 Audio - device pci 11.6 off end # AC97 Modem - device pci 12.0 on end # Ethernet + device pci 11.1 on end // IDE + // 2-4 non existant? + device pci 11.5 on end // AC97 Audio + device pci 11.6 off end // AC97 Modem + device pci 12.0 on end // Ethernet end -# This is on the EPIA MII, not the M. +// This is on the EPIA MII, not the M. chip southbridge/ricoh/rl5c476 register "enable_cf" = "1" device pci 0a.0 on end diff --git a/src/mainboard/via/epia-m700/devicetree.cb b/src/mainboard/via/epia-m700/devicetree.cb index 4e8e2a8..3160b0e 100644 --- a/src/mainboard/via/epia-m700/devicetree.cb +++ b/src/mainboard/via/epia-m700/devicetree.cb @@ -1,24 +1,24 @@ -chip northbridge/via/vx800 # Northbridge +chip northbridge/via/vx800 // Northbridge device pci_domain 0 on - device pci 0.0 on end # AGP Bridge - device pci 0.1 on end # Error Reporting - device pci 0.2 on end # Host Bus Control - device pci 0.3 on end # Memory Controller - device pci 0.4 on end # Power Management - device pci 0.7 on end # V-Link Controller - device pci 1.0 on end # PCI Bridge - # device pci f.0 on end # IDE/SATA - # device pci f.1 on end # IDE - # device pci 10.0 on end # USB 1.1 - # device pci 10.1 on end # USB 1.1 - # device pci 10.2 on end # USB 1.1 - # device pci 10.4 on end # USB 2.0 - # device pci 11.0 on # Southbridge LPC - # end + device pci 0.0 on end // AGP Bridge + device pci 0.1 on end // Error Reporting + device pci 0.2 on end // Host Bus Control + device pci 0.3 on end // Memory Controller + device pci 0.4 on end // Power Management + device pci 0.7 on end // V-Link Controller + device pci 1.0 on end // PCI Bridge + // device pci f.0 on end # IDE/SATA + // device pci f.1 on end # IDE + // device pci 10.0 on end # USB 1.1 + // device pci 10.1 on end # USB 1.1 + // device pci 10.2 on end # USB 1.1 + // device pci 10.4 on end # USB 2.0 + // device pci 11.0 on # Southbridge LPC + // end end - device lapic_cluster 0 on # APIC cluster - chip cpu/via/model_c7 # VIA C7 - device lapic 0 on end # APIC + device lapic_cluster 0 on // APIC cluster + chip cpu/via/model_c7 // VIA C7 + device lapic 0 on end // APIC end end end diff --git a/src/mainboard/via/epia-n/devicetree.cb b/src/mainboard/via/epia-n/devicetree.cb index 651a1a2..3891e84 100644 --- a/src/mainboard/via/epia-n/devicetree.cb +++ b/src/mainboard/via/epia-n/devicetree.cb @@ -1,101 +1,101 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 VIA Technologies, Inc. -## (Written by Aaron Lwe aaron.lwe@gmail.com for VIA) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +// +// This file is part of the coreboot project. +// +// Copyright (C) 2008 VIA Technologies, Inc. +// (Written by Aaron Lwe aaron.lwe@gmail.com for VIA) +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +//
-chip northbridge/via/cn400 # Northbridge +chip northbridge/via/cn400 // Northbridge
- device lapic_cluster 0 on # APIC cluster - chip cpu/via/model_c3 # VIA C3 - device lapic 0 on end # APIC + device lapic_cluster 0 on // APIC cluster + chip cpu/via/model_c3 // VIA C3 + device lapic 0 on end // APIC end end
- device pci_domain 0 on # PCI domain - device pci 0.0 on end # AGP Bridge - device pci 0.1 on end # Error Reporting - device pci 0.2 on end # Host Bus Control - device pci 0.3 on end # Memory Controller - device pci 0.4 on end # Power Management - device pci 0.7 on end # V-Link Controller - device pci 1.0 on end # PCI Bridge - chip southbridge/via/vt8237r # Southbridge - # Enable both IDE channels. + device pci_domain 0 on // PCI domain + device pci 0.0 on end // AGP Bridge + device pci 0.1 on end // Error Reporting + device pci 0.2 on end // Host Bus Control + device pci 0.3 on end // Memory Controller + device pci 0.4 on end // Power Management + device pci 0.7 on end // V-Link Controller + device pci 1.0 on end // PCI Bridge + chip southbridge/via/vt8237r // Southbridge + // Enable both IDE channels. register "ide0_enable" = "1" register "ide1_enable" = "1" - # Both cables are 40pin. + // Both cables are 40pin. register "ide0_80pin_cable" = "0" register "ide1_80pin_cable" = "0" - device pci f.0 on end # IDE/SATA - device pci f.1 on end # IDE - register "fn_ctrl_lo" = "0xC0" # Disable AC/MC97 - register "fn_ctrl_hi" = "0x9d" # Disable USB Direct & LAN Gating - device pci 10.0 on end # OHCI - device pci 10.1 on end # OHCI - device pci 10.2 on end # OHCI - device pci 10.3 on end # OHCI - device pci 10.4 on end # EHCI - device pci 10.5 off end # USB Direct - device pci 11.0 on # Southbridge LPC - chip superio/winbond/w83697hf # Super I/O - device pnp 2e.0 off # Floppy + device pci f.0 on end // IDE/SATA + device pci f.1 on end // IDE + register "fn_ctrl_lo" = "0xC0" // Disable AC/MC97 + register "fn_ctrl_hi" = "0x9d" // Disable USB Direct & LAN Gating + device pci 10.0 on end // OHCI + device pci 10.1 on end // OHCI + device pci 10.2 on end // OHCI + device pci 10.3 on end // OHCI + device pci 10.4 on end // EHCI + device pci 10.5 off end // USB Direct + device pci 11.0 on // Southbridge LPC + chip superio/winbond/w83697hf // Super I/O + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 end - device pnp 2e.2 on # COM1 + device pnp 2e.2 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # COM2 + device pnp 2e.3 off // COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.6 off # IR Port + device pnp 2e.6 off // IR Port io 0x60 = 0x000 end - device pnp 2e.7 off # GPIO 1 - io 0x60 = 0x201 # 0x201 + device pnp 2e.7 off // GPIO 1 + io 0x60 = 0x201 // 0x201 end - device pnp 2e.8 off # GPIO 5 - io 0x60 = 0x330 # 0x330 + device pnp 2e.8 off // GPIO 5 + io 0x60 = 0x330 // 0x330 end - device pnp 2e.9 off # GPIO 2, 3,and 4 - io 0x60 = 0x000 # + device pnp 2e.9 off // GPIO 2, 3,and 4 + io 0x60 = 0x000 // end - device pnp 2e.a off # ACPI - io 0x60 = 0x000 # + device pnp 2e.a off // ACPI + io 0x60 = 0x000 // end - device pnp 2e.b on # HWM + device pnp 2e.b on // HWM io 0x60 = 0x290 irq 0x70 = 0 end end end - device pci 11.5 off end # AC'97 audio - device pci 11.6 off end # AC'97 Modem - device pci 12.0 on end # Ethernet + device pci 11.5 off end // AC'97 audio + device pci 11.6 off end // AC'97 Modem + device pci 12.0 on end // Ethernet end end end diff --git a/src/mainboard/via/epia/devicetree.cb b/src/mainboard/via/epia/devicetree.cb index 1e19a32..61f8e96 100644 --- a/src/mainboard/via/epia/devicetree.cb +++ b/src/mainboard/via/epia/devicetree.cb @@ -1,33 +1,33 @@ chip northbridge/via/vt8601 device pci_domain 0 on - device pci 0.0 on end # Northbridge -# device pci 0.1 on # AGP bridge - # device pci 0.0 on end # Integrated VGA -# end + device pci 0.0 on end // Northbridge +// device pci 0.1 on # AGP bridge + // device pci 0.0 on end # Integrated VGA +// end chip southbridge/via/vt8231 register "enable_native_ide" = "0" register "enable_com_ports" = "1" register "enable_keyboard" = "0" - device pci 11.0 on # Southbrdge + device pci 11.0 on // Southbrdge chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.3 off // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 @@ -35,22 +35,22 @@ chip northbridge/via/vt8601 end register "com1" = "{CONFIG_TTYS0_BAUD}" end - device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GAME_MIDI_GIPO1 - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.6 off end // CIR + device pnp 2e.7 off end // GAME_MIDI_GIPO1 + device pnp 2e.8 off end // GPIO2 + device pnp 2e.9 off end // GPIO3 + device pnp 2e.a off end // ACPI + device pnp 2e.b on // HW Monitor io 0x60 = 0x290 end end - device pci 11.1 on end # Ide - device pci 11.2 off end # Usb port 0-1 - device pci 11.3 off end # Usb port 2-3 - device pci 11.4 off end # ACPI - device pci 11.5 off end # AC97 Audio - device pci 11.6 on end # AC97 Modem - device pci 12.0 on end # Ethernet + device pci 11.1 on end // Ide + device pci 11.2 off end // Usb port 0-1 + device pci 11.3 off end // Usb port 2-3 + device pci 11.4 off end // ACPI + device pci 11.5 off end // AC97 Audio + device pci 11.6 on end // AC97 Modem + device pci 12.0 on end // Ethernet end end
diff --git a/src/mainboard/via/pc2500e/devicetree.cb b/src/mainboard/via/pc2500e/devicetree.cb index 05ce877..3280cad 100644 --- a/src/mainboard/via/pc2500e/devicetree.cb +++ b/src/mainboard/via/pc2500e/devicetree.cb @@ -1,89 +1,89 @@ -chip northbridge/via/cn700 # Northbridge - device pci_domain 0 on # PCI domain +chip northbridge/via/cn700 // Northbridge + device pci_domain 0 on // PCI domain subsystemid 0x1019 0xaa51 inherit - device pci 0.0 on end # AGP Bridge - device pci 0.1 on end # Error Reporting - device pci 0.2 on end # Host Bus Control - device pci 0.3 on end # Memory Controller - device pci 0.4 on end # Power Management - device pci 0.7 on end # V-Link Controller - device pci 1.0 on end # PCI Bridge - chip southbridge/via/vt8237r # Southbridge - # Enable both IDE channels. + device pci 0.0 on end // AGP Bridge + device pci 0.1 on end // Error Reporting + device pci 0.2 on end // Host Bus Control + device pci 0.3 on end // Memory Controller + device pci 0.4 on end // Power Management + device pci 0.7 on end // V-Link Controller + device pci 1.0 on end // PCI Bridge + chip southbridge/via/vt8237r // Southbridge + // Enable both IDE channels. register "ide0_enable" = "1" register "ide1_enable" = "1" - # Both cables are 40pin. + // Both cables are 40pin. register "ide0_80pin_cable" = "0" register "ide1_80pin_cable" = "0" - device pci f.0 on end # SATA - device pci f.1 on end # IDE + device pci f.0 on end // SATA + device pci f.1 on end // IDE register "fn_ctrl_lo" = "0x80" register "fn_ctrl_hi" = "0x1d" - device pci 10.0 on end # UHCI - device pci 10.1 on end # UHCI - device pci 10.2 on end # UHCI - device pci 10.3 on end # UHCI - device pci 10.4 on end # EHCI - device pci 10.5 on end # UDCI - device pci 11.0 on # Southbridge LPC - chip superio/ite/it8716f # Super I/O - device pnp 2e.0 on # Floppy + device pci 10.0 on end // UHCI + device pci 10.1 on end // UHCI + device pci 10.2 on end // UHCI + device pci 10.3 on end // UHCI + device pci 10.4 on end // EHCI + device pci 10.5 on end // UDCI + device pci 11.0 on // Southbridge LPC + chip superio/ite/it8716f // Super I/O + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # COM1 + device pnp 2e.1 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 off # COM2 (N/A on this board) + device pnp 2e.2 off // COM2 (N/A on this board) io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 on # Parallel port + device pnp 2e.3 on // Parallel port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 end - device pnp 2e.4 on # Environment controller + device pnp 2e.4 on // Environment controller io 0x60 = 0x290 io 0x62 = 0x0000 irq 0x70 = 9 end - device pnp 2e.5 off # PS/2 keyboard (not used) + device pnp 2e.5 off // PS/2 keyboard (not used) io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.6 off # PS/2 mouse (not used) + device pnp 2e.6 off // PS/2 mouse (not used) irq 0x70 = 12 end - device pnp 2e.7 on # GPIO + device pnp 2e.7 on // GPIO io 0x60 = 0x0000 io 0x62 = 0x0800 io 0x64 = 0x0000 end - device pnp 2e.8 off # MIDI port (N/A) + device pnp 2e.8 off // MIDI port (N/A) io 0x60 = 0x300 irq 0x70 = 10 end - device pnp 2e.9 off # Game port (N/A) + device pnp 2e.9 off // Game port (N/A) io 0x60 = 0x201 end - device pnp 2e.a on # Consumer IR + device pnp 2e.a on // Consumer IR io 0x60 = 0x310 irq 0x70 = 11 end end end - device pci 11.5 on end # AC'97 audio - # device pci 11.6 off end # AC'97 modem (N/A) - device pci 12.0 on end # Ethernet + device pci 11.5 on end // AC'97 audio + // device pci 11.6 off end # AC'97 modem (N/A) + device pci 12.0 on end // Ethernet end end - device lapic_cluster 0 on # APIC cluster - chip cpu/via/model_c7 # VIA C7 - device lapic 0 on end # APIC + device lapic_cluster 0 on // APIC cluster + chip cpu/via/model_c7 // VIA C7 + device lapic 0 on end // APIC end end end diff --git a/src/mainboard/via/vt8454c/devicetree.cb b/src/mainboard/via/vt8454c/devicetree.cb index 1a5bf54..2b341fd 100644 --- a/src/mainboard/via/vt8454c/devicetree.cb +++ b/src/mainboard/via/vt8454c/devicetree.cb @@ -5,50 +5,50 @@ chip northbridge/via/cx700 end end device pci_domain 0 on - device pci 0.0 on end # AGP Bridge - device pci 0.1 on end # Error Reporting - device pci 0.2 on end # Host Bus Control - device pci 0.3 on end # Memory Controller - device pci 0.4 on end # Power Management - device pci 0.7 on end # V-Link Controller - device pci 1.0 on # PCI Bridge - device pci 0.0 on end # Onboard Video - end # PCI Bridge - device pci f.0 on end # IDE/SATA - #device pci f.1 on end # IDE - device pci 10.0 on end # USB 1.1 - device pci 10.1 on end # USB 1.1 - device pci 10.2 on end # USB 1.1 - device pci 10.4 on end # USB 2.0 - device pci 11.0 on # Southbridge LPC + device pci 0.0 on end // AGP Bridge + device pci 0.1 on end // Error Reporting + device pci 0.2 on end // Host Bus Control + device pci 0.3 on end // Memory Controller + device pci 0.4 on end // Power Management + device pci 0.7 on end // V-Link Controller + device pci 1.0 on // PCI Bridge + device pci 0.0 on end // Onboard Video + end // PCI Bridge + device pci f.0 on end // IDE/SATA + //device pci f.1 on end # IDE + device pci 10.0 on end // USB 1.1 + device pci 10.1 on end // USB 1.1 + device pci 10.2 on end // USB 1.1 + device pci 10.4 on end // USB 2.0 + device pci 11.0 on // Southbridge LPC chip superio/via/vt1211 - device pnp 2e.0 on # Floppy + device pnp 2e.0 on // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 on # Parallel Port + device pnp 2e.1 on // Parallel Port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 end - device pnp 2e.2 on # COM1 + device pnp 2e.2 on // COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # COM2 + device pnp 2e.3 on // COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.b on # HWM + device pnp 2e.b on // HWM io 0x60 = 0xec00 end - end # superio - end # pci 11.0 - # 1-4 non existant - #device pci 11.5 on end # AC97 Audio - #device pci 11.6 off end # AC97 Modem - #device pci 12.0 on end # Ethernet - end # pci domain 0 -end # cx700 + end // superio + end // pci 11.0 + // 1-4 non existant + //device pci 11.5 on end # AC97 Audio + //device pci 11.6 off end # AC97 Modem + //device pci 12.0 on end # Ethernet + end // pci domain 0 +end // cx700
diff --git a/src/mainboard/winent/pl6064/devicetree.cb b/src/mainboard/winent/pl6064/devicetree.cb index ff20fed..0b2176c 100644 --- a/src/mainboard/winent/pl6064/devicetree.cb +++ b/src/mainboard/winent/pl6064/devicetree.cb @@ -1,77 +1,77 @@ chip northbridge/amd/lx device pci_domain 0 on - device pci 1.0 on end # Northbridge - device pci 1.1 on end # Graphics + device pci 1.0 on end // Northbridge + device pci 1.1 on end // Graphics chip southbridge/amd/cs5536 - # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK - # SIRQ Mode = Active(Quiet) mode. Save power.... - # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK + // IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + // SIRQ Mode = Active(Quiet) mode. Save power.... + // Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK register "lpc_serirq_enable" = "0x0000105a" register "lpc_serirq_polarity" = "0x0000EFA5" register "lpc_serirq_mode" = "1" register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "1" # 0: host, 1:device - register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "enable_ide_nand_flash" = "0" // 0:ide mode, 1:flash + register "enable_USBP4_device" = "1" // 0: host, 1:device + register "enable_USBP4_overcurrent" = "0" //0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) register "com1_enable" = "0" register "com1_address" = "0x3F8" register "com1_irq" = "4" register "com2_enable" = "0" register "com2_address" = "0x2F8" register "com2_irq" = "3" - register "unwanted_vpci[0]" = "0" # End of list has a zero + register "unwanted_vpci[0]" = "0" // End of list has a zero
- device pci d.0 on end # Ethernet 4 - device pci a.0 on end # Ethernet 1 - device pci b.0 on end # Ethernet 2 - device pci c.0 on end # Ethernet 3 - device pci e.0 on end # Slot1 - device pci f.0 on # ISA Bridge + device pci d.0 on end // Ethernet 4 + device pci a.0 on end // Ethernet 1 + device pci b.0 on end // Ethernet 2 + device pci c.0 on end // Ethernet 3 + device pci e.0 on end // Slot1 + device pci f.0 on // ISA Bridge chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy + device pnp 2e.0 off // Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel port + device pnp 2e.1 off // Parallel port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on // Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end
- device pnp 2e.3 on # Com2 + device pnp 2e.3 on // Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end
- device pnp 2e.5 on # Keyboard + device pnp 2e.5 on // Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GAME_MIDI_GIPO1 - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a on # ACPI + device pnp 2e.6 off end // CIR + device pnp 2e.7 off end // GAME_MIDI_GIPO1 + device pnp 2e.8 off end // GPIO2 + device pnp 2e.9 off end // GPIO3 + device pnp 2e.a on // ACPI irq 0x70 = 9 end - device pnp 2e.b on # HW Monitor + device pnp 2e.b on // HW Monitor io 0x60 = 0x290 end end end - device pci f.2 on end # IDE Controller - device pci f.3 off end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI + device pci f.2 on end // IDE Controller + device pci f.3 off end // Audio + device pci f.4 on end // OHCI + device pci f.5 on end // EHCI end end - # APIC cluster is late CPU init. + // APIC cluster is late CPU init. device lapic_cluster 0 on chip cpu/amd/model_lx device lapic 0 on end diff --git a/src/mainboard/wyse/s50/devicetree.cb b/src/mainboard/wyse/s50/devicetree.cb index 504a5de..5b57b40 100644 --- a/src/mainboard/wyse/s50/devicetree.cb +++ b/src/mainboard/wyse/s50/devicetree.cb @@ -1,23 +1,23 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Nils Jacobs -## -## This program is free software; you can redistribute it and/or -## modify it under the terms of the GNU General Public License as -## published by the Free Software Foundation; version 2 of -## the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -## MA 02110-1301 USA -## +// +// This file is part of the coreboot project. +// +// Copyright (C) 2010 Nils Jacobs +// +// This program is free software; you can redistribute it and/or +// modify it under the terms of the GNU General Public License as +// published by the Free Software Foundation; version 2 of +// the License. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +// MA 02110-1301 USA +//
chip northbridge/amd/gx2 register "irqmap" = "0xaa5b" @@ -33,21 +33,21 @@ chip northbridge/amd/gx2 device pci 1.1 on end chip southbridge/amd/cs5536 register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "0" #0: host, 1:device - register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "enable_ide_nand_flash" = "0" // 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" //0: host, 1:device + register "enable_USBP4_overcurrent" = "0" //0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) register "com1_enable" = "1" register "com1_address" = "0x3F8" register "com1_irq" = "4" register "com2_enable" = "0" register "com2_address" = "0x2F8" register "com2_irq" = "3" - device pci e.0 on end # Realtek 8139 LAN - device pci f.0 on end # ISA Bridge - device pci f.2 on end # IDE Controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI + device pci e.0 on end // Realtek 8139 LAN + device pci f.0 on end // ISA Bridge + device pci f.2 on end // IDE Controller + device pci f.3 on end // Audio + device pci f.4 on end // OHCI + device pci f.5 on end // EHCI end end end diff --git a/util/sconfig/main.c b/util/sconfig/main.c index c3448f3..af27b1b 100755 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -435,15 +435,14 @@ static void inherit_subsystem_ids(FILE *file, struct device *dev) }
int main(int argc, char** argv) { - if (argc != 3) { - printf("usage: sconfig vendor/mainboard outputdir\n"); + if (argc != 4) { + printf("usage: sconfig vendor/mainboard outputdir devicetree\n"); return 1; } char *mainboard=argv[1]; char *outputdir=argv[2]; - char *devtree=malloc(strlen(mainboard)+30); + char *devtree=argv[3]; char *outputc=malloc(strlen(outputdir)+10); - sprintf(devtree, "src/mainboard/%s/devicetree.cb", mainboard); sprintf(outputc, "%s/static.c", outputdir);
headers.next = malloc(sizeof(struct header)); diff --git a/util/sconfig/sconfig.l b/util/sconfig/sconfig.l index 50c315b..6026e09 100755 --- a/util/sconfig/sconfig.l +++ b/util/sconfig/sconfig.l @@ -26,8 +26,8 @@ int linenum = 0; %option nodebug %% [ \t]+ {} -#.*\n {linenum++;} \r?\n {linenum++;} +#.*\n {linenum++;} chip {return(CHIP);} device {return(DEVICE);} register {return(REGISTER);}
On 03/27/2011 01:02 PM, Sven Schnelle wrote:
pass devicetree.cb trough cpp before parse it with sconfig. This has the advantage that we can use Kconfig variables in devicetree.cb.
Signed-off-by: Sven Schnelle svens@stackframe.org
I like the idea.
If abuild doesn't complain, then Acked-by: Alexandru Gagniuc mr.nuke.me@gmail.com
Alex
P.S. Next time please send the patch as an attachment, not in the body of the email. I'm certain a few devs right now are cursing at their mail clients crashing ;).
On 03/27/2011 01:02 PM, Sven Schnelle wrote:
Signed-off-by: Sven Schnelle svens@stackframe.org
Acked-by: Alexandru Gagniuc mr.nuke.me@gmail.com
Am Sonntag, den 27.03.2011, 12:02 +0200 schrieb Sven Schnelle:
Signed-off-by: Sven Schnelle svens@stackframe.org
Acked-by: Patrick Georgi patrick.georgi@secunet.com
-
Alex G. -
Georgi, Patrick -
Sven Schnelle