[v2] r4238 - in trunk/coreboot-v2/src/northbridge: amd/amdfam10 amd/gx1 amd/gx2 amd/lx intel/e7501 intel/e7520 intel/e7525 intel/i3100 intel/i440bx intel/i82810 intel/i82830 intel/i855gme intel/i855pm via/cn700 via/cx700 via/vt8601 via/vt8623
Author: stepan Date: 2009-04-30 15:58:42 +0200 (Thu, 30 Apr 2009) New Revision: 4238
Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/Config.lb trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c trunk/coreboot-v2/src/northbridge/amd/gx1/Config.lb trunk/coreboot-v2/src/northbridge/amd/gx1/northbridge.c trunk/coreboot-v2/src/northbridge/amd/gx2/Config.lb trunk/coreboot-v2/src/northbridge/amd/gx2/northbridge.c trunk/coreboot-v2/src/northbridge/amd/lx/Config.lb trunk/coreboot-v2/src/northbridge/amd/lx/northbridge.c trunk/coreboot-v2/src/northbridge/intel/e7501/Config.lb trunk/coreboot-v2/src/northbridge/intel/e7501/northbridge.c trunk/coreboot-v2/src/northbridge/intel/e7520/Config.lb trunk/coreboot-v2/src/northbridge/intel/e7520/northbridge.c trunk/coreboot-v2/src/northbridge/intel/e7525/Config.lb trunk/coreboot-v2/src/northbridge/intel/e7525/northbridge.c trunk/coreboot-v2/src/northbridge/intel/i3100/Config.lb trunk/coreboot-v2/src/northbridge/intel/i3100/northbridge.c trunk/coreboot-v2/src/northbridge/intel/i440bx/Config.lb trunk/coreboot-v2/src/northbridge/intel/i440bx/northbridge.c trunk/coreboot-v2/src/northbridge/intel/i82810/Config.lb trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c trunk/coreboot-v2/src/northbridge/intel/i82830/Config.lb trunk/coreboot-v2/src/northbridge/intel/i82830/northbridge.c trunk/coreboot-v2/src/northbridge/intel/i855gme/Config.lb trunk/coreboot-v2/src/northbridge/intel/i855gme/northbridge.c trunk/coreboot-v2/src/northbridge/intel/i855pm/Config.lb trunk/coreboot-v2/src/northbridge/intel/i855pm/northbridge.c trunk/coreboot-v2/src/northbridge/via/cn700/Config.lb trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c trunk/coreboot-v2/src/northbridge/via/cx700/northbridge.c trunk/coreboot-v2/src/northbridge/via/vt8601/Config.lb trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c trunk/coreboot-v2/src/northbridge/via/vt8623/Config.lb trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c Log: Add high tables support to all northbridges.
Signed-off-by: Stefan Reinauer stepan@coresystems.de Acked-by: Patrick Georgi patrick.georgi@coresystems.de
Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/Config.lb 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/Config.lb 2009-04-30 13:58:42 UTC (rev 4238) @@ -19,8 +19,10 @@
uses AGP_APERTURE_SIZE uses HAVE_ACPI_TABLES +uses HAVE_HIGH_TABLES
default AGP_APERTURE_SIZE=0x4000000 +default HAVE_HIGH_TABLES=1
config chip.h
Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c 2009-04-30 13:58:42 UTC (rev 4238) @@ -911,6 +911,11 @@
#endif
+#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif + static void pci_domain_set_resources(device_t dev) { #if CONFIG_PCI_64BIT_PREF_MEM == 1 @@ -1084,6 +1089,15 @@ ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; +#if HAVE_HIGH_TABLES==1 + if (i==0 && high_tables_base==0) { + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; + printk_debug("(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE, + high_tables_base); + } +#endif } #if CONFIG_AMDMCT == 0 #if HW_MEM_HOLE_SIZEK != 0 @@ -1108,6 +1122,15 @@ } ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; +#if HAVE_HIGH_TABLES==1 + printk_debug("%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n", + i, mmio_basek, basek, limitk); + if (i==0 && high_tables_base==0) { + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; + } +#endif }
for(link = 0; link < dev->links; link++) {
Modified: trunk/coreboot-v2/src/northbridge/amd/gx1/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/gx1/Config.lb 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/amd/gx1/Config.lb 2009-04-30 13:58:42 UTC (rev 4238) @@ -1,2 +1,4 @@ +uses HAVE_HIGH_TABLES config chip.h driver northbridge.o +default HAVE_HIGH_TABLES=1
Modified: trunk/coreboot-v2/src/northbridge/amd/gx1/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/gx1/northbridge.c 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/amd/gx1/northbridge.c 2009-04-30 13:58:42 UTC (rev 4238) @@ -126,6 +126,11 @@ return tolm; }
+#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif + static void pci_domain_set_resources(device_t dev) { device_t mc_dev; @@ -168,6 +173,13 @@ */ tolmk = tomk; } + +#if HAVE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif + /* Report the memory regions */ idx = 10; ram_resource(dev, idx++, 0, tolmk);
Modified: trunk/coreboot-v2/src/northbridge/amd/gx2/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/gx2/Config.lb 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/amd/gx2/Config.lb 2009-04-30 13:58:42 UTC (rev 4238) @@ -1,3 +1,4 @@ +uses HAVE_HIGH_TABLES config chip.h driver northbridge.o object northbridgeinit.o @@ -3,2 +4,3 @@ object chipsetinit.o object grphinit.o +default HAVE_HIGH_TABLES=1
Modified: trunk/coreboot-v2/src/northbridge/amd/gx2/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/gx2/northbridge.c 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/amd/gx2/northbridge.c 2009-04-30 13:58:42 UTC (rev 4238) @@ -501,6 +501,11 @@
void chipsetInit (void);
+#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif + static void enable_dev(struct device *dev) { printk_debug("gx2 north: enable_dev\n"); @@ -512,6 +517,7 @@ if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info; extern void cpubug(void); + u32 tomk; printk_debug("DEVICE_PATH_PCI_DOMAIN\n"); /* cpubug MUST be called before setup_gx2(), so we force the issue here */ northbridgeinit(); @@ -524,7 +530,13 @@ graphics_init(); dev->ops = &pci_domain_ops; pci_set_method(dev); - ram_resource(dev, 0, 0, ((sizeram() - VIDEO_MB) * 1024) - SMM_SIZE); + tomk = ((sizeram() - VIDEO_MB) * 1024) - SMM_SIZE; +#if HAVE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif + ram_resource(dev, 0, 0, tomk); } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { printk_debug("DEVICE_PATH_APIC_CLUSTER\n"); dev->ops = &cpu_bus_ops;
Modified: trunk/coreboot-v2/src/northbridge/amd/lx/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/lx/Config.lb 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/amd/lx/Config.lb 2009-04-30 13:58:42 UTC (rev 4238) @@ -1,3 +1,4 @@ +uses HAVE_HIGH_TABLES config chip.h driver northbridge.o object northbridgeinit.o @@ -2 +3,2 @@ object grphinit.o +default HAVE_HIGH_TABLES=1
Modified: trunk/coreboot-v2/src/northbridge/amd/lx/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/lx/northbridge.c 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/amd/lx/northbridge.c 2009-04-30 13:58:42 UTC (rev 4238) @@ -415,19 +415,32 @@ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; }
+#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif + static void pci_domain_set_resources(device_t dev) { int idx; + u32 tomk; device_t mc_dev;
printk_spew(">> Entering northbridge.c: %s\n", __func__);
mc_dev = dev->link[0].children; if (mc_dev) { + tomk = get_systop() / 1024; /* Report the memory regions */ idx = 10; ram_resource(dev, idx++, 0, 640); - ram_resource(dev, idx++, 1024, (get_systop() - 0x100000) / 1024); // Systop - 1 MB -> KB + ram_resource(dev, idx++, 1024, tomk - 1024); // Systop - 1 MB -> KB + +#if HAVE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif }
assign_resources(&dev->link[0]);
Modified: trunk/coreboot-v2/src/northbridge/intel/e7501/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/e7501/Config.lb 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/intel/e7501/Config.lb 2009-04-30 13:58:42 UTC (rev 4238) @@ -1,3 +1,7 @@ +uses HAVE_HIGH_TABLES + config chip.h
object northbridge.o + +default HAVE_HIGH_TABLES=1
Modified: trunk/coreboot-v2/src/northbridge/intel/e7501/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/e7501/northbridge.c 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/intel/e7501/northbridge.c 2009-04-30 13:58:42 UTC (rev 4238) @@ -65,6 +65,11 @@ return tolm; }
+#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif + static void pci_domain_set_resources(device_t dev) { device_t mc_dev; @@ -140,6 +145,12 @@ ram_resource(dev, idx++, remapbasek, (remaplimitk + 64*1024) - remapbasek); } + +#if HAVE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif } assign_resources(&dev->link[0]); }
Modified: trunk/coreboot-v2/src/northbridge/intel/e7520/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/e7520/Config.lb 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/intel/e7520/Config.lb 2009-04-30 13:58:42 UTC (rev 4238) @@ -1,3 +1,5 @@ +uses HAVE_HIGH_TABLES + config chip.h driver northbridge.o driver pciexp_porta.o @@ -5,6 +7,8 @@ driver pciexp_portb.o driver pciexp_portc.o
+default HAVE_HIGH_TABLES=1 + makerule raminit_test depends "$(TOP)/src/northbridge/intel/e7520/raminit_test.c" depends "$(TOP)/src/northbridge/intel/e7520/raminit.c"
Modified: trunk/coreboot-v2/src/northbridge/intel/e7520/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/e7520/northbridge.c 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/intel/e7520/northbridge.c 2009-04-30 13:58:42 UTC (rev 4238) @@ -76,6 +76,10 @@ return tolm; }
+#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif
static void pci_domain_set_resources(device_t dev) { @@ -164,6 +168,12 @@ ram_resource(dev, 6, remapbasek, (remaplimitk + 64*1024) - remapbasek); } + +#if HAVE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif } assign_resources(&dev->link[0]); }
Modified: trunk/coreboot-v2/src/northbridge/intel/e7525/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/e7525/Config.lb 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/intel/e7525/Config.lb 2009-04-30 13:58:42 UTC (rev 4238) @@ -1,3 +1,5 @@ +uses HAVE_HIGH_TABLES + config chip.h driver northbridge.o driver pciexp_porta.o @@ -5,6 +7,8 @@ driver pciexp_portb.o driver pciexp_portc.o
+default HAVE_HIGH_TABLES=1 + makerule raminit_test depends "$(TOP)/src/northbridge/intel/e7525/raminit_test.c" depends "$(TOP)/src/northbridge/intel/e7525/raminit.c"
Modified: trunk/coreboot-v2/src/northbridge/intel/e7525/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/e7525/northbridge.c 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/intel/e7525/northbridge.c 2009-04-30 13:58:42 UTC (rev 4238) @@ -76,6 +76,10 @@ return tolm; }
+#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif
static void pci_domain_set_resources(device_t dev) { @@ -164,6 +168,12 @@ ram_resource(dev, 6, remapbasek, (remaplimitk + 64*1024) - remapbasek); } + +#if HAVE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif } assign_resources(&dev->link[0]); }
Modified: trunk/coreboot-v2/src/northbridge/intel/i3100/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i3100/Config.lb 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/intel/i3100/Config.lb 2009-04-30 13:58:42 UTC (rev 4238) @@ -17,6 +17,11 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
+uses HAVE_HIGH_TABLES + config chip.h + driver northbridge.o driver pciexp_porta.o + +default HAVE_HIGH_TABLES=1
Modified: trunk/coreboot-v2/src/northbridge/intel/i3100/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i3100/northbridge.c 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/intel/i3100/northbridge.c 2009-04-30 13:58:42 UTC (rev 4238) @@ -97,6 +97,10 @@ return tolm; }
+#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif
static void pci_domain_set_resources(device_t dev) { @@ -185,6 +189,12 @@ ram_resource(dev, 6, remapbasek, (remaplimitk + 64*1024) - remapbasek); } + +#if HAVE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif } assign_resources(&dev->link[0]); }
Modified: trunk/coreboot-v2/src/northbridge/intel/i440bx/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i440bx/Config.lb 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/intel/i440bx/Config.lb 2009-04-30 13:58:42 UTC (rev 4238) @@ -18,5 +18,10 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
+uses HAVE_HIGH_TABLES + config chip.h + driver northbridge.o + +default HAVE_HIGH_TABLES=1
Modified: trunk/coreboot-v2/src/northbridge/intel/i440bx/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i440bx/northbridge.c 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/intel/i440bx/northbridge.c 2009-04-30 13:58:42 UTC (rev 4238) @@ -91,6 +91,10 @@ return tolm; }
+#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif static void pci_domain_set_resources(device_t dev) { device_t mc_dev; @@ -127,6 +131,12 @@ idx = 10; ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); + +#if HAVE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif }
assign_resources(&dev->link[0]);
Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82810/Config.lb 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/intel/i82810/Config.lb 2009-04-30 13:58:42 UTC (rev 4238) @@ -18,5 +18,10 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
+uses HAVE_HIGH_TABLES + config chip.h + driver northbridge.o + +default HAVE_HIGH_TABLES=1
Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c 2009-04-30 13:58:42 UTC (rev 4238) @@ -122,6 +122,11 @@ /* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256, };
+#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif + static void pci_domain_set_resources(device_t dev) { device_t mc_dev; @@ -166,6 +171,12 @@ idx = 10; ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 1024, tolmk - 1024); + +#if HAVE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif } assign_resources(&dev->link[0]); }
Modified: trunk/coreboot-v2/src/northbridge/intel/i82830/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82830/Config.lb 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/intel/i82830/Config.lb 2009-04-30 13:58:42 UTC (rev 4238) @@ -18,5 +18,10 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
+uses HAVE_HIGH_TABLES + config chip.h + driver northbridge.o + +default HAVE_HIGH_TABLES=1
Modified: trunk/coreboot-v2/src/northbridge/intel/i82830/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82830/northbridge.c 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/intel/i82830/northbridge.c 2009-04-30 13:58:42 UTC (rev 4238) @@ -107,6 +107,10 @@ return tolm; }
+#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif static void pci_domain_set_resources(device_t dev) { device_t mc_dev; @@ -144,6 +148,12 @@ idx = 10; ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 1024, tolmk - 1024); + +#if HAVE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif } assign_resources(&dev->link[0]); }
Modified: trunk/coreboot-v2/src/northbridge/intel/i855gme/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i855gme/Config.lb 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/intel/i855gme/Config.lb 2009-04-30 13:58:42 UTC (rev 4238) @@ -18,7 +18,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+uses HAVE_HIGH_TABLES + config chip.h + object northbridge.o -#driver misc_control.o
+default HAVE_HIGH_TABLES=1
Modified: trunk/coreboot-v2/src/northbridge/intel/i855gme/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i855gme/northbridge.c 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/intel/i855gme/northbridge.c 2009-04-30 13:58:42 UTC (rev 4238) @@ -88,6 +88,10 @@ return tolm; }
+#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif static void pci_domain_set_resources(device_t dev) { device_t mc_dev; @@ -143,6 +147,11 @@ /* ram_resource(dev, idx++, 1024, tolmk - 1024); */ ram_resource(dev, idx++, 768, tolmk - 768);
+#if HAVE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif } assign_resources(&dev->link[0]); }
Modified: trunk/coreboot-v2/src/northbridge/intel/i855pm/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i855pm/Config.lb 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/intel/i855pm/Config.lb 2009-04-30 13:58:42 UTC (rev 4238) @@ -1,4 +1,7 @@ +uses HAVE_HIGH_TABLES + config chip.h + object northbridge.o -#driver misc_control.o
+default HAVE_HIGH_TABLES=1
Modified: trunk/coreboot-v2/src/northbridge/intel/i855pm/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i855pm/northbridge.c 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/intel/i855pm/northbridge.c 2009-04-30 13:58:42 UTC (rev 4238) @@ -66,6 +66,11 @@ return tolm; }
+#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif + static void pci_domain_set_resources(device_t dev) { device_t mc_dev; @@ -108,6 +113,12 @@ idx = 10; ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); + +#if HAVE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif } assign_resources(&dev->link[0]); }
Modified: trunk/coreboot-v2/src/northbridge/via/cn700/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/via/cn700/Config.lb 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/via/cn700/Config.lb 2009-04-30 13:58:42 UTC (rev 4238) @@ -18,8 +18,14 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
+uses HAVE_HIGH_TABLES + config chip.h + object vgabios.o + driver northbridge.o driver agp.o driver vga.o + +default HAVE_HIGH_TABLES=1
Modified: trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c 2009-04-30 13:58:42 UTC (rev 4238) @@ -163,6 +163,12 @@ return tolm; }
+#if HAVE_HIGH_TABLES==1 +/* maximum size of high tables in KB */ +#define HIGH_TABLES_SIZE 64 +extern uint64_t high_tables_base, high_tables_size; +#endif + static void pci_domain_set_resources(device_t dev) { /* The order is important to find the correct RAM size. */ @@ -199,6 +205,13 @@ /* The PCI hole does does not overlap the memory. */ tolmk = tomk; } + +#if HAVE_HIGH_TABLES == 1 + high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE* 1024; + printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); +#endif + /* Report the memory regions. */ idx = 10; /* TODO: Hole needed? */
Modified: trunk/coreboot-v2/src/northbridge/via/cx700/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/cx700/northbridge.c 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/via/cx700/northbridge.c 2009-04-30 13:58:42 UTC (rev 4238) @@ -123,12 +123,6 @@ else tomk = (((rambits << 6) - (4 << reg) - 1) * 1024);
-#if HAVE_HIGH_TABLES == 1 - high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE* 1024; - printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); -#endif - /* Compute the top of Low memory */ tolmk = pci_tolm >> 10; if (tolmk >= tomk) { @@ -137,6 +131,12 @@ tolmk -= 1024; // TOP 1M SM Memory }
+#if HAVE_HIGH_TABLES == 1 + high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE* 1024; + printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); +#endif + /* Report the memory regions */ idx = 10;
Modified: trunk/coreboot-v2/src/northbridge/via/vt8601/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vt8601/Config.lb 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/via/vt8601/Config.lb 2009-04-30 13:58:42 UTC (rev 4238) @@ -1,2 +1,7 @@ +uses HAVE_HIGH_TABLES + config chip.h + driver northbridge.o + +default HAVE_HIGH_TABLES=1
Modified: trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c 2009-04-30 13:58:42 UTC (rev 4238) @@ -101,6 +101,12 @@ return tolm; }
+#if HAVE_HIGH_TABLES==1 +/* maximum size of high tables in KB */ +#define HIGH_TABLES_SIZE 64 +extern uint64_t high_tables_base, high_tables_size; +#endif + static void pci_domain_set_resources(device_t dev) { static const uint8_t ramregs[] = { @@ -140,6 +146,13 @@ */ tolmk = tomk; } + +#if HAVE_HIGH_TABLES == 1 + high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE* 1024; + printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); +#endif + /* Report the memory regions */ idx = 10; ram_resource(dev, idx++, 0, tolmk);
Modified: trunk/coreboot-v2/src/northbridge/via/vt8623/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vt8623/Config.lb 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/via/vt8623/Config.lb 2009-04-30 13:58:42 UTC (rev 4238) @@ -1,2 +1,7 @@ +uses HAVE_HIGH_TABLES + config chip.h + driver northbridge.o + +default HAVE_HIGH_TABLES=1
Modified: trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c 2009-04-30 12:53:00 UTC (rev 4237) +++ trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c 2009-04-30 13:58:42 UTC (rev 4238) @@ -15,25 +15,11 @@ #include "northbridge.h"
/* - * This fixup is based on capturing values from an Award bios. Without + * This fixup is based on capturing values from an Award BIOS. Without * this fixup the DMA write performance is awful (i.e. hdparm -t /dev/hda is 20x * slower than normal, ethernet drops packets). * Apparently these registers govern some sort of bus master behavior. */ -#if 0 -static void dump_dev(device_t dev) -{ - int i,j; - - for(i = 0; i < 256; i += 16) { - printk_debug("0x%x: ", i); - for(j = 0; j < 16; j++) { - printk_debug("%02x ", pci_read_config8(dev, i+j)); - } - printk_debug("\n"); - } -} -#endif
static void northbridge_init(device_t dev) { @@ -72,7 +58,6 @@ pci_write_config8(dev, 0xe0, c); pci_write_config8(dev, 0xe2, 0x42); /* 'cos award does */ } - //dump_dev(dev); }
static void nullfunc(){} @@ -100,7 +85,6 @@ pci_write_config8(dev, 0x43, 0x44); pci_write_config8(dev, 0x44, 0x34); pci_write_config8(dev, 0x83, 0x02); - //dump_dev(dev); }
static struct device_operations agp_operations = { @@ -129,8 +113,6 @@ pci_write_config32(dev,0x10,0xd8000008); pci_write_config32(dev,0x14,0xdc000000);
- //dump_dev(dev); - // set up performnce counters for debugging vga init sequence //setup.lo = 0x1c0; // count instructions //wrmsr(0x187,setup); @@ -175,7 +157,6 @@ #endif
- pci_write_config32(dev,0x30,0);
/* Set the vga mtrrs - disable for the moment as the add_var_mtrr function has vapourised */ @@ -272,6 +253,12 @@ return tolm; }
+#if HAVE_HIGH_TABLES==1 +/* maximum size of high tables in KB */ +#define HIGH_TABLES_SIZE 64 +extern uint64_t high_tables_base, high_tables_size; +#endif + static void pci_domain_set_resources(device_t dev) { static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d }; @@ -311,6 +298,13 @@ */ tolmk = tomk; } + +#if HAVE_HIGH_TABLES == 1 + high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE* 1024; + printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); +#endif + /* Report the memory regions */ idx = 10; ram_resource(dev, idx++, 0, 640); /* first 640k */
-
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