Hi,
I'm getting C1 (pause 6 seconds) C6, hang on the post card. I modified the smartcore-p3 (also 440BX based. Possibly there's 0x10 for an instant to start.
I'll post all the lspci stuff tomorrow, just wondering if those post codes ring a bell for anyone. I can't find those in the code anywhere.
Regards,
Jeremy
* Jeremy Jackson jerj@coplanar.net [040824 08:51]:
Hi,
I'm getting C1 (pause 6 seconds) C6, hang on the post card. I modified the smartcore-p3 (also 440BX based. Possibly there's 0x10 for an instant to start.
I'll post all the lspci stuff tomorrow, just wondering if those post codes ring a bell for anyone. I can't find those in the code anywhere.
Any serial console output? It seems there is neither post code C1 nor C6 in all of LinuxBIOS.
What's the reason for having both post_code() and intel_chip_post_macro()? I'd suggest renaming the later to post_macro() or post_code() as well..
Stefan
On Tue, 24 Aug 2004, Jeremy Jackson wrote:
Hi,
I'm getting C1 (pause 6 seconds) C6, hang on the post card. I modified the smartcore-p3 (also 440BX based. Possibly there's 0x10 for an instant to start.
10 is an early post. C1 I will have to look up. Anyone who wants to make up a post code table is welcome ...
you should try to hook up serial.
ron
I already have serial... but the problem was an incomplete flashing. I'm guessing the NIC I was using seems to be only wired for the 1st 64k, and the previous contents in the upper half of the 128k part (old bios from other mobo) were writing the c1..c6 post codes
Uniflash to the rescue! Haven't gotten around to porting devbios to MTD yet...sigh.
I have to say, wow that was easy! Linuxbios really is modular. Change the superio, flash size, and off you go. Kudos!
Any ideas about the etherboot no heap found?
Cheers,
Jeremy
LinuxBIOS-1.0.0 Tue Aug 24 10:17:36 EDT 2004 starting... Ram1 Ram2 Ram3 Ram Enable 1 Ram Enable 2 Ram Enable 3 Ram Enable 4 Ram Enable 5 Ram4 Ram5 Ram6 Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.0.0 Tue Aug 24 10:17:36 EDT 2004 booting... Finding PCI configuration type. PCI: Using configuration type 1 Scanning PCI bus...PCI: pci_scan_bus for bus 0 PCI: 00:00.0 [8086/7190] PCI: 00:01.0 [8086/7191] PCI: 00:07.0 [8086/7110] PCI: 00:07.1 [8086/7111] PCI: 00:07.2 [8086/7112] PCI: 00:07.3 [8086/7113] PCI: 00:0f.0 [8086/1229] PCI: pci_scan_bus for bus 1 PCI: 01:00.0 [1023/9750] PCI: pci_scan_bus returning with max=01 PCI: pci_scan_bus returning with max=01 done Allocating PCI resources... ASSIGN RESOURCES, bus 0 PCI: 00:00.0 10 <- [0xe0000000 - 0xefffffff] prefmem PCI: 00:01.0 1c <- [0x00001000 - 0x00000fff] bus 1 io PCI: 00:01.0 24 <- [0xf0a00000 - 0xf09fffff] bus 1 prefmem PCI: 00:01.0 20 <- [0xf0000000 - 0xf08fffff] bus 1 mem ASSIGN RESOURCES, bus 1 PCI: 01:00.0 10 <- [0xf0000000 - 0xf03fffff] mem PCI: 01:00.0 14 <- [0xf0800000 - 0xf081ffff] mem PCI: 01:00.0 18 <- [0xf0400000 - 0xf07fffff] mem ASSIGNED RESOURCES, bus 1 PCI: 00:07.1 20 <- [0x00001040 - 0x0000104f] io PCI: 00:07.2 20 <- [0x00001000 - 0x0000101f] io PCI: 00:0f.0 10 <- [0xf0a00000 - 0xf0a00fff] prefmem PCI: 00:0f.0 14 <- [0x00001020 - 0x0000103f] io PCI: 00:0f.0 18 <- [0xf0900000 - 0xf09fffff] mem ASSIGNED RESOURCES, bus 0 Allocating VGA resource done. Enabling PCI resourcess...PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 cmd <- 07 PCI: 00:07.0 cmd <- 07 PCI: 00:07.1 cmd <- 01 PCI: 00:07.2 cmd <- 01 PCI: 00:07.3 cmd <- 01 PCI: 00:0f.0 cmd <- 03 PCI: 01:00.0 cmd <- 03 done. Initializing PCI devices... PCI devices initialized totalram: 16M Initializing CPU #0 Enabling cache... Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 16MB, type WB DONE variable MTRRs Clear out the extra MTRR's call intel_enable_var_mtrr() Leave setup_mtrrs done.
Max cpuid index : 2 Vendor ID : GenuineIntel Processor Type : 0x00 Processor Family : 0x06 Processor Model : 0x05 Processor Mask : 0x00 Processor Stepping : 0x01 Feature flags : 0x0183fbff
Cache/TLB descriptor values: 1 reads required Desc 0x01 : Instr TLB: 4KB pages, 4-way set assoc, 32 entries Desc 0x02 : Instr TLB: 4MB pages, fully assoc, 2 entries Desc 0x03 : Data TLB: 4KB pages, 4-way set assoc, 64 entries Desc 0x00 : null Desc 0x00 : null Desc 0x00 : null Desc 0x00 : null Desc 0x00 : null Desc 0x00 : null Desc 0x00 : null Desc 0x00 : null Desc 0x00 : null Desc 0x40 : No L2 cache Desc 0x08 : Inst cache: 16K bytes, 4-way set assoc, 32 byte line size Desc 0x04 : Data TLB: 4MB pages, 4-way set assoc, 8 entries Gesc 0x0c : Data cache: 16K bytes, 2-way or 4-way set assoc, 32 byte line size
.TRR check .ixed MTRRs : Enabled Variable MTRRs: Enabled . ../ ... . O/. . .... . . /Disabling local apic...done. CPU #0 Initialized intel_mainboard_fixup() Testing SMI SMI disabled Enabling IDE...0x40 = 0x8000 0x42 = 0x8000 Enabled IDE for channels 1 and 2 Enabling Legacy IDE Word at 4 is now 0x0001 enabling smbus enable pm functions Setting up RTC RTC Init Invalid CMOS LB checksum done. Enabling extended BIOS access Enabling Full ISA Mode Enabling IRQ8 Enabling Mouse IRQ12 on piix4e done. Checking IRQ routing tables... /data/build/linuxbios/freebios/src/arch/i386/lib/pirq_routing.c: 30:check_pi done. Copying IRQ routing tables to 0xf0000...done. Verifing priq routing tables copy at 0xf0000...failed Wrote linuxbios table at: 00000500 - 00000688 checksum db75
Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.2
37:init_bytes() - zkernel_start:0xfffc0000 zkernel_mask:0x0000007f Found ELF candiate at offset 0 Loading Etherboot version: 5.2.5 Dropping non PT_LOAD segment New segment addr 0x20000 size 0xe740 offset 0xb0 filesize 0x63dc (cleaned up) New segment addr 0x20000 size 0xe740 offset 0xb0 filesize 0x63dc cLoading Segment: addr: 0x0000000000f80f68 memsz: 0x000000000000e740 filesz: 0x0 Clearing Segment: addr: 0x0000000000f87344 memsz: 0x0000000000008364 Jumping to boot code at 0x20000 ROM segment 0x0f0f length 0x161e reloc 0x00020000 CPU 360 Mhz Etherboot 5.2.5 (GPL) http://etherboot.org Tagged ELF for [EEPRO100] init_heap: No heap found.
ron minnich wrote:
On Tue, 24 Aug 2004, Jeremy Jackson wrote:
Hi,
I'm getting C1 (pause 6 seconds) C6, hang on the post card. I modified the smartcore-p3 (also 440BX based. Possibly there's 0x10 for an instant to start.
10 is an early post. C1 I will have to look up. Anyone who wants to make up a post code table is welcome ...
you should try to hook up serial.
ron
Jeremy Jackson wrote:
Any ideas about the etherboot no heap found?
Seems 16M isn't enough. swapping for a 256M DIMM fixes it. Son of a gun it boots fast! I can't stop giggling.
On Tue, 24 Aug 2004, Jeremy Jackson wrote:
I already have serial... but the problem was an incomplete flashing. I'm guessing the NIC I was using seems to be only wired for the 1st 64k, and the previous contents in the upper half of the 128k part (old bios from other mobo) were writing the c1..c6 post codes
yes, that makes sense, C1 ... C6 are common post codes from standard bios.
no idea on etherboot error ...
ron
cool, tell us more about this mobo, and send me patches for it.
ron
ron minnich wrote:
cool, tell us more about this mobo, and send me patches for it.
Superio is it8671f, which is different from digitallogic/smartcore-p3
Well, I can netboot Linux or memetest86 using etherboot. Intel e100. Linux can mount root from an IDE CD-ROM, but the network card(s) don't work, so no NFS root. Manual ifconfig doesn't help. The cards can send, but don't seem to recieve. I suspect they're not getting interrupts.
(none):~# cat /proc/interrupts CPU0 0: 65294 XT-PIC timer 1: 0 XT-PIC keyboard 2: 0 XT-PIC cascade 4: 869 XT-PIC serial 5: 0 XT-PIC eth0 14: 2271 XT-PIC ide0 NMI: 0 LOC: 65255 ERR: 0 MIS: 0
Included is linuxbios, Linux output, and lspci -v and -vv for NIC.
On Tue, 24 Aug 2004, Jeremy Jackson wrote:
Well, I can netboot Linux or memetest86 using etherboot. Intel e100. Linux can mount root from an IDE CD-ROM, but the network card(s) don't work, so no NFS root. Manual ifconfig doesn't help. The cards can send, but don't seem to recieve. I suspect they're not getting interrupts.
what's getpir say?
ron
ron minnich wrote:
what's getpir say?
Running on Linuxbios? In that case:
(none):/mnt# ./getpir Opening memory... Found PCI IRQ Routing table signature at 81422ac bytes from top of the memory Validating../ Version is:256 Table size:336 Reading 19 slot entries... Checksum is ok! Closing memory Creating irq_tables.c ..... Done, you can move the file to the LinuxBios tree now. (none):/mnt# echo linuxbios booted me!
USB is working... i used a memory key to run getpir/capture results.
irq_tables.c attached. no idea what i'm doing.
Li-Ta Lo wrote:
No, we need it under factory bios.
the one generated by vendor BIOS:
$ cd util/getpir $ make test .... Validating checksum, file: irq_tables.c that was in ./ at compile time... (no other tests are done) BAD CHECKSUM for IRQ Routing table !!!! If you want to make it valid, change the checksum to: 0x73
I will try what it suggests. Where is this information used? By Linuxbios or Linux? What messages would indicate that either of those has detected the table correctly or incorrectly?
Regards,
Jeremy
you want to use that irq_tables.c for your mainboard irq_tables.c
that might fix it.
I assume you ran this one NOT under linuxbios, if you did run it under linuxbios, then reboot with fuctory bios and run it again.
ron
On Tue, 24 Aug 2004, Jeremy Jackson wrote:
I will try what it suggests. Where is this information used? By Linuxbios or Linux?
it is compiled into linuxbios.
What messages would indicate that either of those has detected the table correctly or incorrectly?
just run getpir under fuctory bios and you should be ok, try that and let us know.
ron
ron minnich wrote:
just run getpir under fuctory bios and you should be ok, try that and let us know.
It's ALIVE! Interrupts working now. Sorry if I bugged everyone for info in the manual, it's just so darn exciting!
The only problem I had that wasn't something stupid, was that I had to correct the checksum in irq_tables.c that getpir generated. Shouldn't the generated file have the right checksum? Or maybe it doesn't matter.
I can't believe it's this easy! From newb to 1st mobo up in 24 hours.
Thanks for your help guys.
Cheers,
Jeremy
I remeber reading that asus does non-standard things with SPD. I'm trying to get a P2B up and it dosen't do ram right.
Anything I can try that worked on other asus motherboards?
ron minnich wrote:
On Tue, 24 Aug 2004, Jeremy Jackson wrote:
I can't believe it's this easy! From newb to 1st mobo up in 24 hours.
now you have to write up your experiences for the web page. That title above will do :-)
Sadly my writeup will have to include taking a voltage reading and finding the board locked up. It will no longer boot, do to a red hot south bridge. Not sure what I did... But these 440BX boards are a dime a dozen, so I will find another to continue the work.
Actually, I will still have to send the patch, I did get the board working completely before I fried it.
Now on to the SiS 735... be afraid, be very afraid!
-
Jeremy Jackson -
Li-Ta Lo -
Richard Smith -
ron minnich -
Stefan Reinauer