Hi Mart,
Hey,
this is awesome, thanks! Unfortunately I won't have time to review this in the next 6 weeks, so if you get any Ack, don't delay. v3 can use some new activity.
Professors bothering you again? :)
On 22.01.2009 20:03, Mart Raudsepp wrote:
The following four patches in subsequent e-mails are a coreboot-v3 port to Artec Group ThinCan DBE63 whose prototype is on my table. [...] For reference, the hardware is like DBE62, with the following differences:
- Instead of 64MB NAND flash it has a CompactFlash slot
Nice. That way the hardware remains competitive if flash prices go down even further.
- Instead of 256MB soldered-on RAM, it has one SO-DIMM DDR1 slot
Two comments about this. First, the ability to use real SPD is awesome.
Yeah, it's quite nice to push that particular work down to the SO-DIMM module manufacturers ;) (in addition to the obvious benefit of choice in the size, price and speed, though likely higher price if the choice happens to be similar to the one that would be soldered-on)
Second, how does this relate to the DDR1/DDR2 adapter doe GeodeLX mentioned at http://www.techpowerup.com/82143/AMD_Adds_DDR2_Support_for_Embedded_Geode_Pl... and http://www.digitimes.com/news/a20090115VL201.html
It doesn't right now, as the prototype was already at factory stage in the pipeline by the time these news cropped up. However I have already forwarded the information to our hardware team for evaluation, shortly after Bari mentioned the digitimes link on IRC, and it might or might not affect the final product. There is quite a question for the coreboot side of things here, as "BIOS" changes are told to be necessary for this. If we can't do this in coreboot, then that could be a showstopper.
This is tested on actual hardware.
Even better.
Regards, Mart Raudsepp
On Thu, Jan 22, 2009 at 5:43 PM, Mart Raudsepp mart.raudsepp@artecdesign.ee wrote:
Second, how does this relate to the DDR1/DDR2 adapter doe GeodeLX mentioned at http://www.techpowerup.com/82143/AMD_Adds_DDR2_Support_for_Embedded_Geode_Pl... and http://www.digitimes.com/news/a20090115VL201.html
It doesn't right now, as the prototype was already at factory stage in the pipeline by the time these news cropped up. However I have already forwarded the information to our hardware team for evaluation, shortly after Bari mentioned the digitimes link on IRC, and it might or might not affect the final product. There is quite a question for the coreboot side of things here, as "BIOS" changes are told to be necessary for this. If we can't do this in coreboot, then that could be a showstopper.
We should be able to get the changes from AMD and add them to coreboot. I'll ask if/when we could get them.
Marc
On Thu, Jan 22, 2009 at 9:32 PM, Marc Jones marcj303@gmail.com wrote:
On Thu, Jan 22, 2009 at 5:43 PM, Mart Raudsepp mart.raudsepp@artecdesign.ee wrote:
Second, how does this relate to the DDR1/DDR2 adapter doe GeodeLX mentioned at http://www.techpowerup.com/82143/AMD_Adds_DDR2_Support_for_Embedded_Geode_Pl... and http://www.digitimes.com/news/a20090115VL201.html
It doesn't right now, as the prototype was already at factory stage in the pipeline by the time these news cropped up. However I have already forwarded the information to our hardware team for evaluation, shortly after Bari mentioned the digitimes link on IRC, and it might or might not affect the final product. There is quite a question for the coreboot side of things here, as "BIOS" changes are told to be necessary for this. If we can't do this in coreboot, then that could be a showstopper.
We should be able to get the changes from AMD and add them to coreboot. I'll ask if/when we could get them.
I recieved an email back from AMD that they will be providing a document and/or source after the initial roll out.
Marc
On 23.01.2009 19:45, Marc Jones wrote:
On Thu, Jan 22, 2009 at 9:32 PM, Marc Jones marcj303@gmail.com wrote:
On Thu, Jan 22, 2009 at 5:43 PM, Mart Raudsepp mart.raudsepp@artecdesign.ee wrote:
Second, how does this relate to the DDR1/DDR2 adapter doe GeodeLX mentioned at http://www.techpowerup.com/82143/AMD_Adds_DDR2_Support_for_Embedded_Geode_Pl... and http://www.digitimes.com/news/a20090115VL201.html
It doesn't right now, as the prototype was already at factory stage in the pipeline by the time these news cropped up. However I have already forwarded the information to our hardware team for evaluation, shortly after Bari mentioned the digitimes link on IRC, and it might or might not affect the final product. There is quite a question for the coreboot side of things here, as "BIOS" changes are told to be necessary for this. If we can't do this in coreboot, then that could be a showstopper.
We should be able to get the changes from AMD and add them to coreboot. I'll ask if/when we could get them.
I recieved an email back from AMD that they will be providing a document and/or source after the initial roll out.
Thanks for initiating that.
Regards, Carl-Daniel
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Carl-Daniel Hailfinger -
Marc Jones -
Mart Raudsepp