Dear all,
I'm currently actually trying to access the content of the bios chip while the bios is doing its execution. I'm working on Intel Q35 chipset. And i understand that while the bios is executing, i can actually access the TOP 2MB of the 4 GB address space to access the bios chip raw data content.
However, my bios chip is actually 4MB in size, can someone advice how do i go about accessing the other 2MB of the bios chip while the bios is executing? Because not much documentation on this and i hope someone in the coreboot community could help me on this.
Thank you very much.
Rgds. Stanne.
Hi Stanne,
mtech se13b wrote:
However, my bios chip is actually 4MB in size, can someone advice how do i go about accessing the other 2MB of the bios chip
I think you have to find the correct decode settings for the north- and southbridge, so that accesses to the top 4MB are decoded to the flash chip. You need documentation. Maybe the 945 code in coreboot implements some of this, maybe inteltool can help, but there's no guarantee that the decode registers are the same in your chipset.
//Peter
Hi Stanne,
On 25.09.2009 03:20, mtech se13b wrote:
I'm currently actually trying to access the content of the bios chip while the bios is doing its execution. I'm working on Intel Q35 chipset. And i understand that while the bios is executing, i can actually access the TOP 2MB of the 4 GB address space to access the bios chip raw data content.
However, my bios chip is actually 4MB in size, can someone advice how do i go about accessing the other 2MB of the bios chip while the bios is executing? Because not much documentation on this and i hope someone in the coreboot community could help me on this.
It's all documented in the public ICH9 datsheets. If you need example code, take a look at chipset_enable.c in current flashrom. It can make sure the top 4 MB are mapped to flash if you specify a special parameter.
Regards, Carl-Daniel
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Carl-Daniel Hailfinger -
mtech se13b -
Peter Stuge