Greeting,
With Ron and Eric help, we were able to build a romimage for our VIA vt133 platform with reset_vector correctly located at 0x7fff0.
The resulting romimage seems to have successfully initialized memory and copied code from rom to ram, but seems to be stucked at the call to hardwaremain from crt0. (Post code is 0xfd, which is right before the call).
Anyone has a good idea as to why this call would possibly fail? I'm assuming that SDRAM is successfully initialized because the copy operation to ram was successful (e.g. it didn't hang the system), but I'm not too sure. I'm going to insert some code in crt0 tomorrow to verify that the image in rom and ram are the same, but if anyone has any other idea, I would very much like to know.
Regards,
-- HT
On Thu, 10 Oct 2002, Hieu T. Tran wrote:
The resulting romimage seems to have successfully initialized memory and copied code from rom to ram, but seems to be stucked at the call to hardwaremain from crt0. (Post code is 0xfd, which is right before the call).
the call may not be failing. What may be happening is that you saw the last successful post code; the memory is configured wrong; and the system failed when you jumped to hardwaremain. This is what makes this chipset so frustrating.
Anyone has a good idea as to why this call would possibly fail? I'm assuming that SDRAM is successfully initialized because the copy operation to ram was successful (e.g. it didn't hang the system), but I'm not too sure.
You are right not to be sure. Often the copy operation can work but the memory will fail when the processor tries to use it for a stack, for example. Any operation that causes a burst to memory can cause trouble. The chip is EXTREMELY sensitive to the SDRAM drive level settings.
ron
Ronald G Minnich rminnich@lanl.gov writes:
On Thu, 10 Oct 2002, Hieu T. Tran wrote:
The resulting romimage seems to have successfully initialized memory and copied code from rom to ram, but seems to be stucked at the call to hardwaremain from crt0. (Post code is 0xfd, which is right before the call).
the call may not be failing. What may be happening is that you saw the last successful post code; the memory is configured wrong; and the system failed when you jumped to hardwaremain. This is what makes this chipset so frustrating.
Anyone has a good idea as to why this call would possibly fail? I'm assuming that SDRAM is successfully initialized because the copy operation to ram was successful (e.g. it didn't hang the system), but I'm not too sure.
You are right not to be sure. Often the copy operation can work but the memory will fail when the processor tries to use it for a stack, for example. Any operation that causes a burst to memory can cause trouble. The chip is EXTREMELY sensitive to the SDRAM drive level settings.
For even more fun I have had a hardware glitch that caused the the memory size to be set to 0 after initializing it, properly. The copy succeeded when I had no ram at all. Of course I couldn't execute the LinuxBIOS code.
Have you enabled the serial port?
There is a file ramtest.inc that you can included that will do a basic sanity check on the ram to see if is working. Usually that is a help when brining up a new port.
Eric
Eric W. Biederman wrote:
For even more fun I have had a hardware glitch that caused the the memory size to be set to 0 after initializing it, properly. The copy succeeded when I had no ram at all. Of course I couldn't execute the LinuxBIOS code.
Have you enabled the serial port?
I have enabled the serial port, but no console message so far. Perhaps, my bigger challenge is to get access to documentation for this board. It's manufactured by Portwell (NAD-2050), but there is very data that is available on their site or from the live techsupport contact.
There is a file ramtest.inc that you can included that will do a basic sanity check on the ram to see if is working. Usually that is a help when brining up a new port.
I haved tried including ramtest.inc, but without serial port output, it's difficult to tell. BTW: I'm attaching my lspci output and config file for reference. I'm going to do more due-dilligence on SDRAM initialization before I have more progress to report.
-- HT
Another good thing to do is to learn how to use the dump_northbridge .inc file. For an example see the 430tx port. You can dump northbridge state as you configure it, so that you can see if you are making errors.
ron
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Eric W Biederman -
Hieu T. Tran -
Ronald G Minnich