Hi all,
This is RFC patch. It adds support for automatic PSS object generation for AMD pre fam Fh CPU. Those CPUs require a hardcoded table, which I managed to rewrite during one particularly boring flight. Too pity it is only for Opteron CPUs. Someone needs to finish the second PDF for All others Athlons and Semprons.
It just adds the table to same place where is the fam0fh generator. To make the powernow work on my Asrock 939 board I had to enable undocumented bit1 in PM_Misc 67h of SB710. It looks like this bit is documented in SB600 and it is doing LDT_STOP toggle for C states (and for FID/VID). I remember I had to fix this toggle for VIA chipset too. It took me some time to figure it out. It helped that it started to work if the orig bios was booted and halted to S5. All search was to find out what register was not updated by coreboot).
Whom to ask to fix the AMD documentation?
It is unknown if the bit is necessary for fam 0fh or fam10h, question is if the second bit CC_en which says: "C State enable. This bit must be set in order to exercise the C state" should be enabled (it is for me with orig BIOS).
Thanks, Rudolf
2010/12/25 Rudolf Marek r.marek@assembler.cz:
Hi all,
This is RFC patch. It adds support for automatic PSS object generation for AMD pre fam Fh CPU. Those CPUs require a hardcoded table, which I managed to rewrite during one particularly boring flight. Too pity it is only for Opteron CPUs. Someone needs to finish the second PDF for All others Athlons and Semprons.
It just adds the table to same place where is the fam0fh generator. To make the powernow work on my Asrock 939 board I had to enable undocumented bit1 in PM_Misc 67h of SB710. It looks like this bit is documented in SB600 and it is doing LDT_STOP toggle for C states (and for FID/VID). I remember I had to fix this toggle for VIA chipset too. It took me some time to figure it out. It helped that it started to work if the orig bios was booted and halted to S5. All search was to find out what register was not updated by coreboot).
Whom to ask to fix the AMD documentation?
Hi Rudolf,
I don't know if this is the case for this bit, but some registers are only documented in the register programming requirements document (rpr) and not in the register reference guide (rrg). This is intentional by AMD and they probably won't be changed.
Frank Vibrans is on this list and should be able to relay the request back to the document gatekeepers next week, when they get back from the holiday shutdown.
Marc
Hi all
Attaching update patch. Not much changed, only comments added.
It adds support for automatic PSS object generation for AMD pre fam Fh CPU. Those CPUs require a hardcoded table, which I managed to rewrite during one particularly boring flight. Too pity it is only for Opteron CPUs. Someone needs to finish the second PDF for All others Athlons and Semprons.
Also it enables the FID/VID changes in SB. Jakllsch had some troubles with that too but on am2 CPU. Those bits are only documented in SB600. They arent in RRG RPR and BDG.
Signed-off-by:Rudolf Marek r.marek@asssembler.cz
Thanks, Rudolf
* Rudolf Marek r.marek@assembler.cz [110224 21:04]:
Hi all
Attaching update patch. Not much changed, only comments added.
It adds support for automatic PSS object generation for AMD pre fam Fh CPU. Those CPUs require a hardcoded table, which I managed to rewrite during one particularly boring flight. Too pity it is only for Opteron CPUs. Someone needs to finish the second PDF for All others Athlons and Semprons.
Also it enables the FID/VID changes in SB. Jakllsch had some troubles with that too but on am2 CPU. Those bits are only documented in SB600. They arent in RRG RPR and BDG.
Signed-off-by:Rudolf Marek r.marek@asssembler.cz
Acked-by: Stefan Reinauer stefan.reinauer@coreboot.org
Thanks, Rudolf
Stefan
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Marc Jones -
Rudolf Marek -
Stefan Reinauer