Dear coreboot folks,
please take a look at the following difference of two files.
$ diff -u src/southbridge/amd/cimx/sb{8,9}00/late.c --- src/southbridge/amd/cimx/sb800/late.c 2013-03-02 08:52:51.313654244 +0100 +++ src/southbridge/amd/cimx/sb900/late.c 2013-03-02 08:51:52.157327591 +0100 @@ -21,25 +21,25 @@ #include <device/device.h> /* device_t */ #include <device/pci.h> /* device_operations */ #include <device/pci_ids.h> -#include <arch/ioapic.h> #include <device/smbus.h> /* smbus_bus_operations */ #include <pc80/mc146818rtc.h> #include <console/console.h> /* printk */ -#include <arch/acpi.h> #include "lpc.h" /* lpc_read_resources */ -#include "SBPLATFORM.h" /* Platfrom Specific Definitions */ -#include "cfg.h" /* sb800 Cimx configuration */ -#include "chip.h" /* struct southbridge_amd_cimx_sb800_config */ -#include "sb_cimx.h" /* AMD CIMX wrapper entries */ -#include "smbus.h" -#include "fan.h" +#include "SbPlatform.h" /* Platfrom Specific Definitions */ +#include "chip.h" /* struct southbridge_amd_cimx_sb900_config */ +
/*implement in mainboard.c*/ +//void set_pcie_assert(void); +//void set_pcie_deassert(void); void set_pcie_reset(void); void set_pcie_dereset(void);
-static AMDSBCFG sb_late_cfg; //global, init in sb800_cimx_config +#ifndef _RAMSTAGE_ +#define _RAMSTAGE_ +#endif +static AMDSBCFG sb_late_cfg; //global, init in sb900_cimx_config static AMDSBCFG *sb_config = &sb_late_cfg;
@@ -53,79 +53,52 @@ * @param[in] sb_config Southbridge configuration structure pointer. * */ -u32 sb800_callout_entry(u32 func, u32 data, void* config) +u32 sb900_callout_entry(u32 func, u32 data, void* config) { u32 ret = 0; - printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__); + + printk(BIOS_DEBUG, "SB900 - Late.c - sb900_callout_entry - Start.\n"); switch (func) { case CB_SBGPP_RESET_ASSERT: - set_pcie_reset(); + //set_pcie_assert(); +//- set_pcie_reset(); break;
case CB_SBGPP_RESET_DEASSERT: - set_pcie_dereset(); + //set_pcie_deassert(); +//- set_pcie_dereset(); break;
- case IMC_FIRMWARE_FAIL: - break; +//- case IMC_FIRMWARE_FAIL: +//- break;
default: break; }
- printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__); + printk(BIOS_DEBUG, "SB900 - Late.c - sb900_callout_entry - End.\n"); return ret; }
-#define HOST_CAP 0x00 /* host capabilities */ -#define HOST_CTL 0x04 /* global host control */ -#define HOST_IRQ_STAT 0x08 /* interrupt status */ -#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ - -#define HOST_CTL_AHCI_EN (1 << 31) /* AHCI enabled */ -static void ahci_raid_init(struct device *dev) -{ - u8 irq = 0; - u32 bar5, caps, ports, val; - - val = pci_read_config16(dev, PCI_CLASS_DEVICE); - if (val == PCI_CLASS_STORAGE_SATA) { - printk(BIOS_DEBUG, "AHCI controller "); - } else if (val == PCI_CLASS_STORAGE_RAID) { - printk(BIOS_DEBUG, "RAID controller "); - } else { - printk(BIOS_WARNING, "device class:%x, neither in ahci or raid mode\n", val); - return; - } - - irq = pci_read_config8(dev, PCI_INTERRUPT_LINE); - bar5 = pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "IOMEM base: 0x%X, IRQ: 0x%X\n", bar5, irq); - - caps = *(volatile u32 *)(bar5 + HOST_CAP); - caps = (caps & 0x1F) + 1; - ports= *(volatile u32 *)(bar5 + HOST_PORTS_IMPL); - printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports); - - /* make sure ahci is enabled */ - val = *(volatile u32 *)(bar5 + HOST_CTL); - if (!(val & HOST_CTL_AHCI_EN)) { - *(volatile u32 *)(bar5 + HOST_CTL) = val | HOST_CTL_AHCI_EN; - } - - dev->command |= PCI_COMMAND_MASTER; - pci_write_config8(dev, PCI_COMMAND, dev->command); - printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n"); -}
static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = 0, };
-static void lpc_init(device_t dev) +static void lpc_enable_resources(device_t dev) { - printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n");
+ printk(BIOS_DEBUG, "SB900 - Late.c - lpc_enable_resources - Start.\n"); + pci_dev_enable_resources(dev); + //lpc_enable_childrens_resources(dev); + printk(BIOS_DEBUG, "SB900 - Late.c - lpc_enable_resources - End.\n"); +} + +static void lpc_init(device_t dev) +{ + printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - Start.\n"); + /* SB Configure HPET base and enable bit */ +//- hpetInit(sb_config, &(sb_config->BuildParameters)); rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
/* Initialize the real time clock. @@ -135,13 +108,13 @@ */ rtc_init(0);
- printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - End.\n"); + printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - End.\n"); }
static struct device_operations lpc_ops = { .read_resources = lpc_read_resources, .set_resources = lpc_set_resources, - .enable_resources = pci_dev_enable_resources, + .enable_resources = lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, .ops_pci = &lops_pci, @@ -149,35 +122,58 @@
static const struct pci_driver lpc_driver __pci_driver = { .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_LPC, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_LPC, };
+ +static void sata_enable_resources(struct device *dev) +{ + printk(BIOS_DEBUG, "SB900 - Late.c - sata_enable_resources - Start.\n"); +//- sataInitAfterPciEnum(sb_config); + pci_dev_enable_resources(dev); + printk(BIOS_DEBUG, "SB900 - Late.c - sata_enable_resources - End.\n"); +} + +static void sata_init(struct device *dev) +{ + printk(BIOS_DEBUG, "SB900 - Late.c - sata_init - Start.\n"); + sb_config->StdHeader.Func = SB_MID_POST_INIT; +//- AmdSbDispatcher(sb_config); //sataInitMidPost only +//- commonInitLateBoot(sb_config); +//- sataInitLatePost(sb_config); + printk(BIOS_DEBUG, "SB900 - Late.c - sata_init - End.\n"); +} + static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ahci_raid_init, + .enable_resources = sata_enable_resources, //pci_dev_enable_resources, + .init = sata_init, .scan_bus = 0, .ops_pci = &lops_pci, };
-static const struct pci_driver ahci_driver __pci_driver = { +static const struct pci_driver sata_driver __pci_driver = { .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_SATA_AHCI, + .vendor = PCI_VENDOR_ID_AMD, +#if (CONFIG_SATA_CONTROLLER_MODE == 0x0 || CONFIG_SATA_CONTROLLER_MODE == 0x3) + .device = PCI_DEVICE_ID_ATI_SB900_SATA, //SATA IDE Mode +#endif +#if (CONFIG_SATA_CONTROLLER_MODE == 0x2 || CONFIG_SATA_CONTROLLER_MODE == 0x4) + .device = PCI_DEVICE_ID_ATI_SB900_SATA_AHCI, //SATA AHCI Mode +#endif +#if (CONFIG_SATA_CONTROLLER_MODE == 0x5 || CONFIG_SATA_CONTROLLER_MODE == 0x6) + .device = PCI_DEVICE_ID_ATI_SB900_SATA_AMDAHCI, //SATA AMDAHCI Mode +#endif +#if (CONFIG_SATA_CONTROLLER_MODE == 0x1 && INCHIP_SATA_FORCE_RAID5 == 0x0) + .device = PCI_DEVICE_ID_ATI_SB900_SATA_RAID5, //SATA RAID5 Mode +#endif +#if (CONFIG_SATA_CONTROLLER_MODE == 0x1 && INCHIP_SATA_FORCE_RAID5 == 0x1) + .device = PCI_DEVICE_ID_ATI_SB900_SATA_RAID, //SATA RAID Mode +#endif };
-static const struct pci_driver raid_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID, -}; -static const struct pci_driver raid5_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID5, -};
#if CONFIG_USBDEBUG static void usb_set_resources(struct device *dev) @@ -186,7 +182,7 @@ u32 base; u32 old_debug;
- printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__); + printk(BIOS_DEBUG, "SB900 - Late.c - usb_set_resources - Start.\n"); old_debug = get_ehci_debug(); set_ehci_debug(0);
@@ -199,10 +195,18 @@ base = res->base; set_ehci_base(base); report_resource_stored(dev, res, ""); - printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__); + printk(BIOS_DEBUG, "SB900 - Late.c - usb_set_resources - End.\n"); } #endif
+static void usb_init(struct device *dev) +{ + printk(BIOS_DEBUG, "SB900 - Late.c - usb_init - Start.\n"); +//- usbInitAfterPciInit(sb_config); +//- commonInitLateBoot(sb_config); + printk(BIOS_DEBUG, "SB900 - Late.c - usb_init - End.\n"); +} + static struct device_operations usb_ops = { .read_resources = pci_dev_read_resources, #if CONFIG_USBDEBUG @@ -211,7 +215,7 @@ .set_resources = pci_dev_set_resources, #endif .enable_resources = pci_dev_enable_resources, - .init = 0, + .init = usb_init, .scan_bus = 0, .ops_pci = &lops_pci, }; @@ -219,78 +223,90 @@ /* * The pci id of usb ctrl 0 and 1 are the same. */ +static const struct pci_driver usb_xhci123_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_USB_16_0, /* XHCI-USB1, XHCI-USB2 */ +}; + static const struct pci_driver usb_ohci123_driver __pci_driver = { .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */ + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */ };
static const struct pci_driver usb_ehci123_driver __pci_driver = { .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */ + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */ };
static const struct pci_driver usb_ohci4_driver __pci_driver = { .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_USB_20_5, /* OHCI-USB4 */ + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_USB_20_5, /* OHCI-USB4 */ };
+static void azalia_init(struct device *dev) +{ + printk(BIOS_DEBUG, "SB900 - Late.c - azalia_init - Start.\n"); +//- azaliaInitAfterPciEnum(sb_config); //Detect and configure High Definition Audio + printk(BIOS_DEBUG, "SB900 - Late.c - azalia_init - End.\n"); +} + static struct device_operations azalia_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, + .init = azalia_init, .scan_bus = 0, .ops_pci = &lops_pci, };
static const struct pci_driver azalia_driver __pci_driver = { .ops = &azalia_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_HDA, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_HDA, };
+static void gec_init(struct device *dev) +{ + printk(BIOS_DEBUG, "SB900 - Late.c - gec_init - Start.\n"); +//- gecInitAfterPciEnum(sb_config); +//- gecInitLatePost(sb_config); + printk(BIOS_DEBUG, "SB900 - Late.c - gec_init - End.\n"); +} + static struct device_operations gec_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, + .init = gec_init, .scan_bus = 0, .ops_pci = &lops_pci, };
static const struct pci_driver gec_driver __pci_driver = { .ops = &gec_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_GEC, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_GEC, };
-/** - * @brief Enable PCI Bridge - * - * PcibConfig [PM_Reg: EAh], PCIDisable [Bit0] - * 'PCIDisable' set to 0 to enable P2P bridge. - * 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins - * to function as GPIO {GPIO 35:0}. - */ -static void pci_init(device_t dev) + +static void pcie_init(device_t dev) { - /* PCI Bridge SHOULD be enabled by default according to SB800 rrg, - * but actually was disabled in some platform, so I have to enabled it. - */ - RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0); + printk(BIOS_DEBUG, "SB900 - Late.c - pcie_init - Start.\n"); +//- sbPcieGppLateInit(sb_config); + printk(BIOS_DEBUG, "SB900 - Late.c - pcie_init - End.\n"); }
- static struct device_operations pci_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = pci_init, + .init = pcie_init, .scan_bus = pci_scan_bridge, .reset_bus = pci_bus_reset, .ops_pci = &lops_pci, @@ -298,8 +314,8 @@
static const struct pci_driver pci_driver __pci_driver = { .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_PCI, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCI, };
@@ -307,109 +323,95 @@ .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = 0, + .init = pcie_init, .scan_bus = pci_scan_bridge, .enable = 0, .reset_bus = pci_bus_reset, .ops_pci = &lops_pci, };
-/** - * South Bridge CIMx ramstage entry point wrapper. - */ -void sb_Before_Pci_Init(void) -{ - sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; - AmdSbDispatcher(sb_config); -} - -void sb_After_Pci_Init(void) -{ - sb_config->StdHeader.Func = SB_AFTER_PCI_INIT; - AmdSbDispatcher(sb_config); -} - -void sb_Mid_Post_Init(void) -{ - sb_config->StdHeader.Func = SB_MID_POST_INIT; - AmdSbDispatcher(sb_config); -} - -void sb_Late_Post(void) -{ - sb_config->StdHeader.Func = SB_LATE_POST_INIT; - AmdSbDispatcher(sb_config); -} - -void sb_Before_Pci_Restore_Init(void) -{ - sb_config->StdHeader.Func = SB_BEFORE_PCI_RESTORE_INIT; - AmdSbDispatcher(sb_config); -} +/* 0:15:0 PCIe PortA */ +static const struct pci_driver PORTA_driver __pci_driver = { + .ops = &bridge_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCIEA, +}; + +/* 0:15:1 PCIe PortB */ +static const struct pci_driver PORTB_driver __pci_driver = { + .ops = &bridge_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCIEB, +}; + +/* 0:15:2 PCIe PortC */ +static const struct pci_driver PORTC_driver __pci_driver = { + .ops = &bridge_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCIEC, +}; + +/* 0:15:3 PCIe PortD */ +static const struct pci_driver PORTD_driver __pci_driver = { + .ops = &bridge_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCIED, +};
-void sb_After_Pci_Restore_Init(void) -{ - sb_config->StdHeader.Func = SB_AFTER_PCI_RESTORE_INIT; - AmdSbDispatcher(sb_config); -}
/** * @brief SB Cimx entry point sbBeforePciInit wrapper */ -static void sb800_enable(device_t dev) +static void sb900_enable(device_t dev) { - struct southbridge_amd_cimx_sb800_config *sb_chip = - (struct southbridge_amd_cimx_sb800_config *)(dev->chip_info); - - printk(BIOS_DEBUG, "sb800_enable() "); + u8 gpp_port = 0; + struct southbridge_amd_cimx_sb900_config *sb_chip = + (struct southbridge_amd_cimx_sb900_config *)(dev->chip_info); + + sb900_cimx_config(sb_config); + printk(BIOS_DEBUG, "sb900_enable() "); + + /* Config SouthBridge SMBUS/ACPI/IDE/LPC/PCIB.*/ +//- commonInitEarlyBoot(sb_config); +//- commonInitEarlyPost(sb_config);
switch (dev->path.pci.devfn) { - case (0x11 << 3) | 0: /* 0:11.0 SATA */ - /* the first sb800 device */ - switch (GPP_CFGMODE) { /* config the GPP PCIe ports */ - case GPP_CFGMODE_X2200: - abcfg_reg(0xc0, 0x01FF, 0x030); /* x2 Port_0, x2 Port_1 */ - break; - case GPP_CFGMODE_X2110: - abcfg_reg(0xc0, 0x01FF, 0x070); /* x2 Port_0, x1 Port_1&2 */ - break; - case GPP_CFGMODE_X1111: - abcfg_reg(0xc0, 0x01FF, 0x0F0); /* x1 Port_0&1&2&3 */ - break; - case GPP_CFGMODE_X4000: - default: - abcfg_reg(0xc0, 0x01FF, 0x010); /* x4 Port_0 */ - break; - } - sb800_cimx_config(sb_config); + case (0x10 << 3) | 0: /* 0:10:0 XHCI-USB */ +//- usbInitBeforePciEnum(sb_config); // USB POST TIME Only + break;
+ case (0x11 << 3) | 0: /* 0:11.0 SATA */ if (dev->enabled) { - sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; + sb_config->SATAMODE.SataMode.SataController = ENABLED; if (1 == sb_chip->boot_switch_sata_ide) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. else if (0 == sb_chip->boot_switch_sata_ide) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. } else { - sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; + sb_config->SATAMODE.SataMode.SataController = DISABLED; } + +//- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY + break; + + case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */ + case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */ + case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */ + case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */ + case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */ +//- usbInitBeforePciEnum(sb_config); // USB POST TIME Only break;
case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ - printk(BIOS_INFO, "sm_init().\n"); - clear_ioapic(IO_APIC_ADDR); - /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ -#if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16) - /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ - setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS); -#elif (CONFIG_APIC_ID_OFFSET > 0) - /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ - setup_ioapic(IO_APIC_ADDR, 0); -#else -#error "The processor APIC IDs must be lifted to make room for the I/O APIC ID" -#endif break;
case (0x14 << 3) | 1: /* 0:14:1 IDE */ + if (dev->enabled) { + sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED; + } else { + sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED; + } +//- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY break;
case (0x14 << 3) | 2: /* 0:14:2 HDA */ @@ -422,16 +424,11 @@ sb_config->AzaliaController = AZALIA_DISABLE; printk(BIOS_DEBUG, "hda disabled\n"); } +//- azaliaInitBeforePciEnum(sb_config); // Detect and configure High Definition Audio break;
case (0x14 << 3) | 3: /* 0:14:3 LPC */ - /* Initialize the fans */ -#if CONFIG_SB800_IMC_FAN_CONTROL - init_sb800_IMC_fans(dev); -#elif CONFIG_SB800_MANUAL_FAN_CONTROL - init_sb800_MANUAL_fans(dev); -#endif break;
case (0x14 << 3) | 4: /* 0:14:4 PCI */ @@ -445,67 +442,45 @@ sb_config->GecConfig = 1; printk(BIOS_DEBUG, "gec disabled\n"); } +//- gecInitBeforePciEnum(sb_config); // Init GEC break;
case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */ - { - device_t device; - for (device = dev; device; device = device->next) { - if (dev->path.type != DEVICE_PATH_PCI) continue; - if ((device->path.pci.devfn & ~7) != PCI_DEVFN(0x15,0)) break; - sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled; - } + case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */ + case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */ + case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */ + gpp_port = (dev->path.pci.devfn) & 0x03; + if (dev->enabled) { + sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED; + } else { + sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = DISABLED; + }
- /* - * GPP_CFGMODE_X4000: PortA Lanes[3:0] - * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2] - * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3 - * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 - */ + /* + * GPP_CFGMODE_X4000: PortA Lanes[3:0] + * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2] + * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3 + * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 + */ + if (sb_config->GppLinkConfig != sb_chip->gpp_configuration) { sb_config->GppLinkConfig = sb_chip->gpp_configuration; } - break; - - case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */ - sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled; - break; - case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */ - sb_config->USBMODE.UsbMode.Ehci1 = dev->enabled; - break; - case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */ - sb_config->USBMODE.UsbMode.Ohci2 = dev->enabled; - break; - case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */ - sb_config->USBMODE.UsbMode.Ehci2 = dev->enabled; - break; - case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */ - sb_config->USBMODE.UsbMode.Ohci4 = dev->enabled; - break; - case (0x16 << 3) | 0: /* 0:16:0 OHCI-USB3 */ - sb_config->USBMODE.UsbMode.Ohci3 = dev->enabled; - break; - case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */ - sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled;
- /* call the CIMX entry at the last sb800 device, - * so make sure the mainboard devicetree is complete - */ -#if CONFIG_HAVE_ACPI_RESUME - if (acpi_slp_type != 3) - sb_Before_Pci_Init(); - else - sb_Before_Pci_Restore_Init(); -#else - sb_Before_Pci_Init(); -#endif +//- sbPcieGppEarlyInit(sb_config); break;
default: break; } + + /* Special setting ABCFG registers before PCI emulation. */ +//- abSpecialSetBeforePciEnum(sb_config); +//- usbDesertPll(sb_config); + //sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; + //AmdSbDispatcher(sb_config); }
-struct chip_operations southbridge_amd_cimx_sb800_ops = { - CHIP_NAME("ATI SB800") - .enable_dev = sb800_enable, +struct chip_operations southbridge_amd_cimx_sb900_ops = { + CHIP_NAME("ATI SB900") + .enable_dev = sb900_enable, };--- src/southbridge/amd/cimx/sb800/late.c 2013-03-02 08:52:51.313654244 +0100 +++ src/southbridge/amd/cimx/sb900/late.c 2013-03-02 08:51:52.157327591 +0100 @@ -21,25 +21,25 @@ #include <device/device.h> /* device_t */ #include <device/pci.h> /* device_operations */ #include <device/pci_ids.h> -#include <arch/ioapic.h> #include <device/smbus.h> /* smbus_bus_operations */ #include <pc80/mc146818rtc.h> #include <console/console.h> /* printk */ -#include <arch/acpi.h> #include "lpc.h" /* lpc_read_resources */ -#include "SBPLATFORM.h" /* Platfrom Specific Definitions */ -#include "cfg.h" /* sb800 Cimx configuration */ -#include "chip.h" /* struct southbridge_amd_cimx_sb800_config */ -#include "sb_cimx.h" /* AMD CIMX wrapper entries */ -#include "smbus.h" -#include "fan.h" +#include "SbPlatform.h" /* Platfrom Specific Definitions */ +#include "chip.h" /* struct southbridge_amd_cimx_sb900_config */ +
/*implement in mainboard.c*/ +//void set_pcie_assert(void); +//void set_pcie_deassert(void); void set_pcie_reset(void); void set_pcie_dereset(void);
-static AMDSBCFG sb_late_cfg; //global, init in sb800_cimx_config +#ifndef _RAMSTAGE_ +#define _RAMSTAGE_ +#endif +static AMDSBCFG sb_late_cfg; //global, init in sb900_cimx_config static AMDSBCFG *sb_config = &sb_late_cfg;
@@ -53,79 +53,52 @@ * @param[in] sb_config Southbridge configuration structure pointer. * */ -u32 sb800_callout_entry(u32 func, u32 data, void* config) +u32 sb900_callout_entry(u32 func, u32 data, void* config) { u32 ret = 0; - printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__); + + printk(BIOS_DEBUG, "SB900 - Late.c - sb900_callout_entry - Start.\n"); switch (func) { case CB_SBGPP_RESET_ASSERT: - set_pcie_reset(); + //set_pcie_assert(); +//- set_pcie_reset(); break;
case CB_SBGPP_RESET_DEASSERT: - set_pcie_dereset(); + //set_pcie_deassert(); +//- set_pcie_dereset(); break;
- case IMC_FIRMWARE_FAIL: - break; +//- case IMC_FIRMWARE_FAIL: +//- break;
default: break; }
- printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__); + printk(BIOS_DEBUG, "SB900 - Late.c - sb900_callout_entry - End.\n"); return ret; }
-#define HOST_CAP 0x00 /* host capabilities */ -#define HOST_CTL 0x04 /* global host control */ -#define HOST_IRQ_STAT 0x08 /* interrupt status */ -#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ - -#define HOST_CTL_AHCI_EN (1 << 31) /* AHCI enabled */ -static void ahci_raid_init(struct device *dev) -{ - u8 irq = 0; - u32 bar5, caps, ports, val; - - val = pci_read_config16(dev, PCI_CLASS_DEVICE); - if (val == PCI_CLASS_STORAGE_SATA) { - printk(BIOS_DEBUG, "AHCI controller "); - } else if (val == PCI_CLASS_STORAGE_RAID) { - printk(BIOS_DEBUG, "RAID controller "); - } else { - printk(BIOS_WARNING, "device class:%x, neither in ahci or raid mode\n", val); - return; - } - - irq = pci_read_config8(dev, PCI_INTERRUPT_LINE); - bar5 = pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "IOMEM base: 0x%X, IRQ: 0x%X\n", bar5, irq); - - caps = *(volatile u32 *)(bar5 + HOST_CAP); - caps = (caps & 0x1F) + 1; - ports= *(volatile u32 *)(bar5 + HOST_PORTS_IMPL); - printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports); - - /* make sure ahci is enabled */ - val = *(volatile u32 *)(bar5 + HOST_CTL); - if (!(val & HOST_CTL_AHCI_EN)) { - *(volatile u32 *)(bar5 + HOST_CTL) = val | HOST_CTL_AHCI_EN; - } - - dev->command |= PCI_COMMAND_MASTER; - pci_write_config8(dev, PCI_COMMAND, dev->command); - printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n"); -}
static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = 0, };
-static void lpc_init(device_t dev) +static void lpc_enable_resources(device_t dev) { - printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n");
+ printk(BIOS_DEBUG, "SB900 - Late.c - lpc_enable_resources - Start.\n"); + pci_dev_enable_resources(dev); + //lpc_enable_childrens_resources(dev); + printk(BIOS_DEBUG, "SB900 - Late.c - lpc_enable_resources - End.\n"); +} + +static void lpc_init(device_t dev) +{ + printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - Start.\n"); + /* SB Configure HPET base and enable bit */ +//- hpetInit(sb_config, &(sb_config->BuildParameters)); rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
/* Initialize the real time clock. @@ -135,13 +108,13 @@ */ rtc_init(0);
- printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - End.\n"); + printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - End.\n"); }
static struct device_operations lpc_ops = { .read_resources = lpc_read_resources, .set_resources = lpc_set_resources, - .enable_resources = pci_dev_enable_resources, + .enable_resources = lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, .ops_pci = &lops_pci, @@ -149,35 +122,58 @@
static const struct pci_driver lpc_driver __pci_driver = { .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_LPC, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_LPC, };
+ +static void sata_enable_resources(struct device *dev) +{ + printk(BIOS_DEBUG, "SB900 - Late.c - sata_enable_resources - Start.\n"); +//- sataInitAfterPciEnum(sb_config); + pci_dev_enable_resources(dev); + printk(BIOS_DEBUG, "SB900 - Late.c - sata_enable_resources - End.\n"); +} + +static void sata_init(struct device *dev) +{ + printk(BIOS_DEBUG, "SB900 - Late.c - sata_init - Start.\n"); + sb_config->StdHeader.Func = SB_MID_POST_INIT; +//- AmdSbDispatcher(sb_config); //sataInitMidPost only +//- commonInitLateBoot(sb_config); +//- sataInitLatePost(sb_config); + printk(BIOS_DEBUG, "SB900 - Late.c - sata_init - End.\n"); +} + static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ahci_raid_init, + .enable_resources = sata_enable_resources, //pci_dev_enable_resources, + .init = sata_init, .scan_bus = 0, .ops_pci = &lops_pci, };
-static const struct pci_driver ahci_driver __pci_driver = { +static const struct pci_driver sata_driver __pci_driver = { .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_SATA_AHCI, + .vendor = PCI_VENDOR_ID_AMD, +#if (CONFIG_SATA_CONTROLLER_MODE == 0x0 || CONFIG_SATA_CONTROLLER_MODE == 0x3) + .device = PCI_DEVICE_ID_ATI_SB900_SATA, //SATA IDE Mode +#endif +#if (CONFIG_SATA_CONTROLLER_MODE == 0x2 || CONFIG_SATA_CONTROLLER_MODE == 0x4) + .device = PCI_DEVICE_ID_ATI_SB900_SATA_AHCI, //SATA AHCI Mode +#endif +#if (CONFIG_SATA_CONTROLLER_MODE == 0x5 || CONFIG_SATA_CONTROLLER_MODE == 0x6) + .device = PCI_DEVICE_ID_ATI_SB900_SATA_AMDAHCI, //SATA AMDAHCI Mode +#endif +#if (CONFIG_SATA_CONTROLLER_MODE == 0x1 && INCHIP_SATA_FORCE_RAID5 == 0x0) + .device = PCI_DEVICE_ID_ATI_SB900_SATA_RAID5, //SATA RAID5 Mode +#endif +#if (CONFIG_SATA_CONTROLLER_MODE == 0x1 && INCHIP_SATA_FORCE_RAID5 == 0x1) + .device = PCI_DEVICE_ID_ATI_SB900_SATA_RAID, //SATA RAID Mode +#endif };
-static const struct pci_driver raid_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID, -}; -static const struct pci_driver raid5_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID5, -};
#if CONFIG_USBDEBUG static void usb_set_resources(struct device *dev) @@ -186,7 +182,7 @@ u32 base; u32 old_debug;
- printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__); + printk(BIOS_DEBUG, "SB900 - Late.c - usb_set_resources - Start.\n"); old_debug = get_ehci_debug(); set_ehci_debug(0);
@@ -199,10 +195,18 @@ base = res->base; set_ehci_base(base); report_resource_stored(dev, res, ""); - printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__); + printk(BIOS_DEBUG, "SB900 - Late.c - usb_set_resources - End.\n"); } #endif
+static void usb_init(struct device *dev) +{ + printk(BIOS_DEBUG, "SB900 - Late.c - usb_init - Start.\n"); +//- usbInitAfterPciInit(sb_config); +//- commonInitLateBoot(sb_config); + printk(BIOS_DEBUG, "SB900 - Late.c - usb_init - End.\n"); +} + static struct device_operations usb_ops = { .read_resources = pci_dev_read_resources, #if CONFIG_USBDEBUG @@ -211,7 +215,7 @@ .set_resources = pci_dev_set_resources, #endif .enable_resources = pci_dev_enable_resources, - .init = 0, + .init = usb_init, .scan_bus = 0, .ops_pci = &lops_pci, }; @@ -219,78 +223,90 @@ /* * The pci id of usb ctrl 0 and 1 are the same. */ +static const struct pci_driver usb_xhci123_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_USB_16_0, /* XHCI-USB1, XHCI-USB2 */ +}; + static const struct pci_driver usb_ohci123_driver __pci_driver = { .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */ + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */ };
static const struct pci_driver usb_ehci123_driver __pci_driver = { .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */ + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */ };
static const struct pci_driver usb_ohci4_driver __pci_driver = { .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_USB_20_5, /* OHCI-USB4 */ + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_USB_20_5, /* OHCI-USB4 */ };
+static void azalia_init(struct device *dev) +{ + printk(BIOS_DEBUG, "SB900 - Late.c - azalia_init - Start.\n"); +//- azaliaInitAfterPciEnum(sb_config); //Detect and configure High Definition Audio + printk(BIOS_DEBUG, "SB900 - Late.c - azalia_init - End.\n"); +} + static struct device_operations azalia_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, + .init = azalia_init, .scan_bus = 0, .ops_pci = &lops_pci, };
static const struct pci_driver azalia_driver __pci_driver = { .ops = &azalia_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_HDA, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_HDA, };
+static void gec_init(struct device *dev) +{ + printk(BIOS_DEBUG, "SB900 - Late.c - gec_init - Start.\n"); +//- gecInitAfterPciEnum(sb_config); +//- gecInitLatePost(sb_config); + printk(BIOS_DEBUG, "SB900 - Late.c - gec_init - End.\n"); +} + static struct device_operations gec_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, + .init = gec_init, .scan_bus = 0, .ops_pci = &lops_pci, };
static const struct pci_driver gec_driver __pci_driver = { .ops = &gec_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_GEC, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_GEC, };
-/** - * @brief Enable PCI Bridge - * - * PcibConfig [PM_Reg: EAh], PCIDisable [Bit0] - * 'PCIDisable' set to 0 to enable P2P bridge. - * 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins - * to function as GPIO {GPIO 35:0}. - */ -static void pci_init(device_t dev) + +static void pcie_init(device_t dev) { - /* PCI Bridge SHOULD be enabled by default according to SB800 rrg, - * but actually was disabled in some platform, so I have to enabled it. - */ - RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0); + printk(BIOS_DEBUG, "SB900 - Late.c - pcie_init - Start.\n"); +//- sbPcieGppLateInit(sb_config); + printk(BIOS_DEBUG, "SB900 - Late.c - pcie_init - End.\n"); }
- static struct device_operations pci_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = pci_init, + .init = pcie_init, .scan_bus = pci_scan_bridge, .reset_bus = pci_bus_reset, .ops_pci = &lops_pci, @@ -298,8 +314,8 @@
static const struct pci_driver pci_driver __pci_driver = { .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_PCI, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCI, };
@@ -307,109 +323,95 @@ .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = 0, + .init = pcie_init, .scan_bus = pci_scan_bridge, .enable = 0, .reset_bus = pci_bus_reset, .ops_pci = &lops_pci, };
-/** - * South Bridge CIMx ramstage entry point wrapper. - */ -void sb_Before_Pci_Init(void) -{ - sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; - AmdSbDispatcher(sb_config); -} - -void sb_After_Pci_Init(void) -{ - sb_config->StdHeader.Func = SB_AFTER_PCI_INIT; - AmdSbDispatcher(sb_config); -} - -void sb_Mid_Post_Init(void) -{ - sb_config->StdHeader.Func = SB_MID_POST_INIT; - AmdSbDispatcher(sb_config); -} - -void sb_Late_Post(void) -{ - sb_config->StdHeader.Func = SB_LATE_POST_INIT; - AmdSbDispatcher(sb_config); -} - -void sb_Before_Pci_Restore_Init(void) -{ - sb_config->StdHeader.Func = SB_BEFORE_PCI_RESTORE_INIT; - AmdSbDispatcher(sb_config); -} +/* 0:15:0 PCIe PortA */ +static const struct pci_driver PORTA_driver __pci_driver = { + .ops = &bridge_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCIEA, +}; + +/* 0:15:1 PCIe PortB */ +static const struct pci_driver PORTB_driver __pci_driver = { + .ops = &bridge_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCIEB, +}; + +/* 0:15:2 PCIe PortC */ +static const struct pci_driver PORTC_driver __pci_driver = { + .ops = &bridge_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCIEC, +}; + +/* 0:15:3 PCIe PortD */ +static const struct pci_driver PORTD_driver __pci_driver = { + .ops = &bridge_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCIED, +};
-void sb_After_Pci_Restore_Init(void) -{ - sb_config->StdHeader.Func = SB_AFTER_PCI_RESTORE_INIT; - AmdSbDispatcher(sb_config); -}
/** * @brief SB Cimx entry point sbBeforePciInit wrapper */ -static void sb800_enable(device_t dev) +static void sb900_enable(device_t dev) { - struct southbridge_amd_cimx_sb800_config *sb_chip = - (struct southbridge_amd_cimx_sb800_config *)(dev->chip_info); - - printk(BIOS_DEBUG, "sb800_enable() "); + u8 gpp_port = 0; + struct southbridge_amd_cimx_sb900_config *sb_chip = + (struct southbridge_amd_cimx_sb900_config *)(dev->chip_info); + + sb900_cimx_config(sb_config); + printk(BIOS_DEBUG, "sb900_enable() "); + + /* Config SouthBridge SMBUS/ACPI/IDE/LPC/PCIB.*/ +//- commonInitEarlyBoot(sb_config); +//- commonInitEarlyPost(sb_config);
switch (dev->path.pci.devfn) { - case (0x11 << 3) | 0: /* 0:11.0 SATA */ - /* the first sb800 device */ - switch (GPP_CFGMODE) { /* config the GPP PCIe ports */ - case GPP_CFGMODE_X2200: - abcfg_reg(0xc0, 0x01FF, 0x030); /* x2 Port_0, x2 Port_1 */ - break; - case GPP_CFGMODE_X2110: - abcfg_reg(0xc0, 0x01FF, 0x070); /* x2 Port_0, x1 Port_1&2 */ - break; - case GPP_CFGMODE_X1111: - abcfg_reg(0xc0, 0x01FF, 0x0F0); /* x1 Port_0&1&2&3 */ - break; - case GPP_CFGMODE_X4000: - default: - abcfg_reg(0xc0, 0x01FF, 0x010); /* x4 Port_0 */ - break; - } - sb800_cimx_config(sb_config); + case (0x10 << 3) | 0: /* 0:10:0 XHCI-USB */ +//- usbInitBeforePciEnum(sb_config); // USB POST TIME Only + break;
+ case (0x11 << 3) | 0: /* 0:11.0 SATA */ if (dev->enabled) { - sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; + sb_config->SATAMODE.SataMode.SataController = ENABLED; if (1 == sb_chip->boot_switch_sata_ide) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. else if (0 == sb_chip->boot_switch_sata_ide) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. } else { - sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; + sb_config->SATAMODE.SataMode.SataController = DISABLED; } + +//- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY + break; + + case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */ + case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */ + case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */ + case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */ + case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */ +//- usbInitBeforePciEnum(sb_config); // USB POST TIME Only break;
case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ - printk(BIOS_INFO, "sm_init().\n"); - clear_ioapic(IO_APIC_ADDR); - /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ -#if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16) - /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ - setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS); -#elif (CONFIG_APIC_ID_OFFSET > 0) - /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ - setup_ioapic(IO_APIC_ADDR, 0); -#else -#error "The processor APIC IDs must be lifted to make room for the I/O APIC ID" -#endif break;
case (0x14 << 3) | 1: /* 0:14:1 IDE */ + if (dev->enabled) { + sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED; + } else { + sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED; + } +//- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY break;
case (0x14 << 3) | 2: /* 0:14:2 HDA */ @@ -422,16 +424,11 @@ sb_config->AzaliaController = AZALIA_DISABLE; printk(BIOS_DEBUG, "hda disabled\n"); } +//- azaliaInitBeforePciEnum(sb_config); // Detect and configure High Definition Audio break;
case (0x14 << 3) | 3: /* 0:14:3 LPC */ - /* Initialize the fans */ -#if CONFIG_SB800_IMC_FAN_CONTROL - init_sb800_IMC_fans(dev); -#elif CONFIG_SB800_MANUAL_FAN_CONTROL - init_sb800_MANUAL_fans(dev); -#endif break;
case (0x14 << 3) | 4: /* 0:14:4 PCI */ @@ -445,67 +442,45 @@ sb_config->GecConfig = 1; printk(BIOS_DEBUG, "gec disabled\n"); } +//- gecInitBeforePciEnum(sb_config); // Init GEC break;
case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */ - { - device_t device; - for (device = dev; device; device = device->next) { - if (dev->path.type != DEVICE_PATH_PCI) continue; - if ((device->path.pci.devfn & ~7) != PCI_DEVFN(0x15,0)) break; - sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled; - } + case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */ + case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */ + case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */ + gpp_port = (dev->path.pci.devfn) & 0x03; + if (dev->enabled) { + sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED; + } else { + sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = DISABLED; + }
- /* - * GPP_CFGMODE_X4000: PortA Lanes[3:0] - * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2] - * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3 - * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 - */ + /* + * GPP_CFGMODE_X4000: PortA Lanes[3:0] + * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2] + * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3 + * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 + */ + if (sb_config->GppLinkConfig != sb_chip->gpp_configuration) { sb_config->GppLinkConfig = sb_chip->gpp_configuration; } - break; - - case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */ - sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled; - break; - case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */ - sb_config->USBMODE.UsbMode.Ehci1 = dev->enabled; - break; - case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */ - sb_config->USBMODE.UsbMode.Ohci2 = dev->enabled; - break; - case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */ - sb_config->USBMODE.UsbMode.Ehci2 = dev->enabled; - break; - case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */ - sb_config->USBMODE.UsbMode.Ohci4 = dev->enabled; - break; - case (0x16 << 3) | 0: /* 0:16:0 OHCI-USB3 */ - sb_config->USBMODE.UsbMode.Ohci3 = dev->enabled; - break; - case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */ - sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled;
- /* call the CIMX entry at the last sb800 device, - * so make sure the mainboard devicetree is complete - */ -#if CONFIG_HAVE_ACPI_RESUME - if (acpi_slp_type != 3) - sb_Before_Pci_Init(); - else - sb_Before_Pci_Restore_Init(); -#else - sb_Before_Pci_Init(); -#endif +//- sbPcieGppEarlyInit(sb_config); break;
default: break; } + + /* Special setting ABCFG registers before PCI emulation. */ +//- abSpecialSetBeforePciEnum(sb_config); +//- usbDesertPll(sb_config); + //sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; + //AmdSbDispatcher(sb_config); }
-struct chip_operations southbridge_amd_cimx_sb800_ops = { - CHIP_NAME("ATI SB800") - .enable_dev = sb800_enable, +struct chip_operations southbridge_amd_cimx_sb900_ops = { + CHIP_NAME("ATI SB900") + .enable_dev = sb900_enable, };
So changes are mainly,
1. Different capitalization of file names. 2. Different function names (sb800 vs. sb900). 3. Different comments. 4. Changes to the SB800 file which have not been ported to the SB900 file.
So looking at the lspci output,
00:14.5 USB controller: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
Linux drivers(?) seem to use the same code for SB7x0/SB8x0/SB9x0 too. So I just assume that they are indeed very similar.
Should not we do the same? Especially because of item 4., that fixes get ported to all generations.
If that is unfeasible at least spelling of filenames should be kept consistent in my opinion.
Thanks,
Paul
On Sat, Mar 2, 2013 at 2:07 AM, Paul Menzel < paulepanter@users.sourceforge.net> wrote:
Dear coreboot folks,
please take a look at the following difference of two files.
$ diff -u src/southbridge/amd/cimx/sb{8,9}00/late.c --- src/southbridge/amd/cimx/sb800/late.c 2013-03-0208:52:51.313654244 +0100 +++ src/southbridge/amd/cimx/sb900/late.c 2013-03-02 08:51:52.157327591 +0100
...
So changes are mainly,
- Different capitalization of file names.
- Different function names (sb800 vs. sb900).
- Different comments.
- Changes to the SB800 file which have not been ported to the SB900
file.
So looking at the lspci output,
00:14.5 USB controller: Advanced Micro Devices [AMD] nee ATISB7x0/SB8x0/SB9x0 USB OHCI2 Controller
Linux drivers(?) seem to use the same code for SB7x0/SB8x0/SB9x0 too. So I just assume that they are indeed very similar.
Should not we do the same? Especially because of item 4., that fixes get ported to all generations.
If that is unfeasible at least spelling of filenames should be kept consistent in my opinion.
Those seem to be from AGESA/CIMX. For better or worse, it models the vendor's internal code development processes so that coreboot gets code drops like the commercial BIOS vendors. I guess AMD developed the SB900 separately from the SB800 to utilize chipset-specific debug features, and then sanitized the code prior to releasing it.
You're right to point out the problems with this model, but in general I suspect it's best to simply accept the ugly parts rather than diverge from whatever AMD uses internally.
For more info about AGESA/CIMX and coreboot, see http://blogs.amd.com/work/2011/02/28/technical-details-coreboot/
-
David Hendricks -
Paul Menzel