Possible bug in DDR SDRAM init code for VT8623?

[Ian Smith]

I've been working on bringing up Linuxbios on a board which is based 
closely on the EPIA-M and I think I may have found a bug in the DDR 
SDRAM init code in src/northbridge/via/vt8623/raminit.inc

The VIA Northbridge data sheet says that as part of the DDR init 
sequence you need to read from specific addresses on the bank but I 
think the registers to do these reads are not being set up properly 
which can cause the RAM test to fail.

I adjusted a number of register settings to be the same as a sample 
Award Bios but it made no difference so I took a closer look at the DDR 
and found that %ecx was being set up with the memory location to read 
from instead of %esi.

The diff for my fix is as follows:

Index: src/northbridge/via/vt8623/raminit.inc
===================================================================
RCS file: 
/cvsroot/freebios/freebios/src/northbridge/via/vt8623/raminit.inc,v
retrieving revision 1.5
diff -r1.5 raminit.inc
85c85
<       movl $0x2000, %ecx
---
>   movl $0x2000, %esi     /* IAS changed from ecx to esi */

89c89
<       movl $0x800, %ecx
---
>   movl $0x800, %esi     /* IAS changed from ecx to esi */

119c119
<       movl $0x350, %ecx
---
>   movl $0x350, %esi     /* IAS changed from ecx to esi */

What is odd is that the original code works fine on the Via reference 
board (same design as EPIA-M) but when I try to run it on my customer 
board it fails until I make these changes.

Does anyone with more knowledge than me of the Via chipsets have any 
ideas about this?

Cheers

Ian

[ron minnich]

I think you have found a bug, but we need to let andrew ip take a close 
look. I would say your patch is correct as well.

ron

[Andrew Ip]

It is committed.  Thanks, Ian.

-Andrew

On Tue, Sep 23, 2003 at 03:35:53PM +0100, Ian Smith wrote:
> I've been working on bringing up Linuxbios on a board which is based 
> closely on the EPIA-M and I think I may have found a bug in the DDR 
> SDRAM init code in src/northbridge/via/vt8623/raminit.inc
>
> The VIA Northbridge data sheet says that as part of the DDR init 
> sequence you need to read from specific addresses on the bank but I 
> think the registers to do these reads are not being set up properly 
> which can cause the RAM test to fail.
>
> I adjusted a number of register settings to be the same as a sample 
> Award Bios but it made no difference so I took a closer look at the DDR 
> and found that %ecx was being set up with the memory location to read 
> from instead of %esi.
>
> The diff for my fix is as follows:
> Index: src/northbridge/via/vt8623/raminit.inc
>
> RCS file: 
> /cvsroot/freebios/freebios/src/northbridge/via/vt8623/raminit.inc,v
> retrieving revision 1.5
> diff -r1.5 raminit.inc
> 85c85
> <       movl $0x2000, %ecx
> >   movl $0x2000, %esi     /* IAS changed from ecx to esi */
>
> 89c89
> <       movl $0x800, %ecx
> >   movl $0x800, %esi     /* IAS changed from ecx to esi */
>
> 119c119
> <       movl $0x350, %ecx
> >   movl $0x350, %esi     /* IAS changed from ecx to esi */
>
> What is odd is that the original code works fine on the Via reference 
> board (same design as EPIA-M) but when I try to run it on my customer 
> board it fails until I make these changes.
>
> Does anyone with more knowledge than me of the Via chipsets have any 
> ideas about this?
>
> Cheers
>
> Ian
>
> Linuxbios mailing list
> [e-mail]
> http://www.clustermatic.org/mailman/listinfo/linuxbios