[LinuxBIOS] r2952 - in trunk/LinuxBIOSv2: src/mainboard/pcengines/alix1c src/northbridge/amd/lx targets/pcengines/alix1c
Author: rminnich Date: 2007-11-08 00:13:43 +0100 (Thu, 08 Nov 2007) New Revision: 2952
Modified: trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/Options.lb trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/irq_tables.c trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.c trunk/LinuxBIOSv2/targets/pcengines/alix1c/Config.lb Log: Final set of changes to make Alix1c work.
Fix IRQ tables (Thanks to Marc Jones)
Fix IRQ SLOT #
Comment out ram test in early startup.
make the debug print in lx/raminit.c a debug print, not emerg print
Set the default console log level to 3, but leave in the possibility of running with more info (leave maximum at 11)
Signed-off-by: Ronald G. Minnich rminnich@gmail.com
Acked-by: Marc Jones marc.jones@amd.com
Modified: trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/Options.lb 2007-11-07 22:09:02 UTC (rev 2951) +++ trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/Options.lb 2007-11-07 23:13:43 UTC (rev 2952) @@ -103,7 +103,7 @@ ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=9 +default IRQ_SLOT_COUNT=5 #object irq_tables.o
##
Modified: trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c 2007-11-07 22:09:02 UTC (rev 2951) +++ trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c 2007-11-07 23:13:43 UTC (rev 2952) @@ -169,7 +169,8 @@ sdram_initialize(1, memctrl);
/* Check memory */ - ram_check(0x00000000, 640 * 1024); + /* enable this only if you are having questions */ + /* ram_check(0x00000000, 640 * 1024);*/
/* Switch from Cache as RAM to real RAM * There are two ways we could think about this.
Modified: trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/irq_tables.c 2007-11-07 22:09:02 UTC (rev 2951) +++ trunk/LinuxBIOSv2/src/mainboard/pcengines/alix1c/irq_tables.c 2007-11-07 23:13:43 UTC (rev 2952) @@ -1,21 +1,21 @@ /* - * This file is part of the LinuxBIOS project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ +* This file is part of the LinuxBIOS project. +* +* Copyright (C) 2007 Advanced Micro Devices, Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/
#include <arch/pirq_routing.h> #include <console/console.h> @@ -25,83 +25,120 @@
/* Platform IRQs */ #define PIRQA 11 -#define PIRQB 5 -#define PIRQC 10 -#define PIRQD 10 +#define PIRQB 10 +#define PIRQC 11 +#define PIRQD 9
/* Map */ -#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ -#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ -#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ -#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
/* Link */ -#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ -#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ -#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ -#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
+/* ALIX 1c interrupt wiring. Devices are: + * 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 31) + * 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block + * 00:0d.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) + * 00:0e.0 Network controller: Intersil Corporation Prism 2.5 Wavelan chipset (rev 01) + * 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03) + * 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01) + * 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01) + * 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02) + * 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02) + * The only devices that interrupt are: + * What device IRQ PIN PIN WIRED TO + * AES 00:01.2 0a 01 A A + * 3VPCI 00:0c.0 0a 01 A A + * eth0 00:0d.0 0b 01 A B + * mpci 00:0e.0 0a 01 A A + * usb 00:0f.3 0b 02 B B + * usb 00:0f.4 0b 04 D D + * usb 00:0f.5 0b 04 D D + * + * The only swizzled interrupt is eth0, where INTA is wired to interrupt controller line B +*/ const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*IRQ_SLOT_COUNT, /* There can be total IRQ_SLOT_COUNT devices on the bus */ - 0x00, /* Where the interrupt router lies (bus) */ - (0x0f<<3)|0x0, /* Where the interrupt router lies (dev) */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x100b, /* Vendor */ - 0x2b, /* Device */ - 0, /* Crap (miniport) */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xe, /* u8 checksum. This has to be set to some - value that would give 0 after the sum of all - bytes for this structure (including checksum) */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x00,(0x0f<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x0, 0x0}, - {0x00,(0x13<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x00,(0x12<<3)|0x0, {{0x03, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x00,(0x11<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, - {0x00,(0x0a<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x1, 0x0}, - {0x00,(0x0b<<3)|0x0, {{0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x00400}}, 0x2, 0x0}, - {0x00,(0x0c<<3)|0x0, {{0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x00800}}, 0x3, 0x0}, - {0x00,(0x0d<<3)|0x0, {{0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x00400}}, 0x4, 0x0}, +PIRQ_SIGNATURE, /* u32 signature */ +PIRQ_VERSION, /* u16 version */ +32 + 16 * IRQ_SLOT_COUNT, +0x00, /* Where the interrupt router lies (bus) */ +(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ +0x00, /* IRQs devoted exclusively to PCI usage */ +0x100B, /* Vendor */ +0x002B, /* Device */ +0, /* Crap (miniport) */ +{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ +0x00, /* u8 checksum , this has to set to + * some value that would give 0 + * after the sum of all bytes + * for this structure + * (including checksum) + */ +{ + /* If you change the number of entries, + * change the IRQ_SLOT_COUNT above! + */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ + /* PCI SLOT */ + {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot1 */ + /* ONBOARD ETHER */ + {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ + /* MINI PCI */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0}, /* mini slot2 */ + /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ } };
+unsigned long write_pirq_routing_table(unsigned long addr) +{ + int i, j, k, num_entries; + unsigned char pirq[4]; + uint16_t chipset_irq_map; + uint32_t pciAddr, pirtable_end; + struct irq_routing_table *pirq_tbl;
-unsigned long write_pirq_routing_table(unsigned long addr){ - int i, j, k, num_entries; - unsigned int pirq[4]; - uint16_t chipset_irq_map; - uint32_t pciAddr, pirtable_end; - struct irq_routing_table *pirq_tbl; + pirtable_end = copy_pirq_routing_table(addr);
- pirtable_end = copy_pirq_routing_table(addr); + /* Set up chipset IRQ steering. */ + pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; + chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA); + printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr, + chipset_irq_map); + outl(pciAddr & ~3, 0xCF8); + outl(chipset_irq_map, 0xCFC);
- /* Set up chipset IRQ steering */ - pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; - chipset_irq_map = (11 << 12 | 10 << 8 | 11 << 4 | 10); - printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr, chipset_irq_map); - outl(pciAddr & ~3, 0xCF8); - outl(chipset_irq_map, 0xCFC); + pirq_tbl = (struct irq_routing_table *) (addr); + num_entries = (pirq_tbl->size - 32) / 16;
- pirq_tbl = (struct irq_routing_table *)(addr); - num_entries = (pirq_tbl->size - 32)/16; + /* Set PCI IRQs. */ + for (i = 0; i < num_entries; i++) { + printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i, + pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot); + for (j = 0; j < 4; j++) { + printk_debug("INT: %c bitmap: %x ", 'A' + j, + pirq_tbl->slots[i].irq[j].bitmap); + /* Finds lsb in bitmap to IRQ#. */ + for (k = 0; + (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) + && (pirq_tbl->slots[i].irq[j].bitmap != 0); + k++); + pirq[j] = k; + printk_debug("PIRQ: %d\n", k); + }
- /* Set PCI IRQs */ - for (i=0; i < num_entries; i++){ - printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i, pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot); - for (j = 0; j < 4; j++){ - printk_debug("INT: %c bitmap: %x ", 'A'+j, pirq_tbl->slots[i].irq[j].bitmap); - for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++); /* finds lsb in bitmap to IRQ# */ - pirq[j] = k; - printk_debug("PIRQ: %d\n", k); - } - pci_assign_irqs(pirq_tbl->slots[i].bus, pirq_tbl->slots[i].devfn, pirq); /* bus, device, slots IRQs for {A,B,C,D} */ - } + /* Bus, device, slots IRQs for {A,B,C,D}. */ + pci_assign_irqs(pirq_tbl->slots[i].bus, + pirq_tbl->slots[i].devfn >> 3, pirq); + }
- /* put the PIR table in memory and checksum */ - return pirtable_end; + /* Put the PIR table in memory and checksum. */ + return pirtable_end; } -
Modified: trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.c 2007-11-07 22:09:02 UTC (rev 2951) +++ trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.c 2007-11-07 23:13:43 UTC (rev 2952) @@ -29,9 +29,9 @@
void banner(char *s) { - print_emerg("==========================="); - print_emerg(s); - print_emerg("======================================\r\n"); + print_debug("==========================="); + print_debug(s); + print_debug("======================================\r\n"); } void hcf(void) {
Modified: trunk/LinuxBIOSv2/targets/pcengines/alix1c/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/pcengines/alix1c/Config.lb 2007-11-07 22:09:02 UTC (rev 2951) +++ trunk/LinuxBIOSv2/targets/pcengines/alix1c/Config.lb 2007-11-07 23:13:43 UTC (rev 2952) @@ -15,7 +15,7 @@
option FALLBACK_SIZE = ROM_SIZE
-option DEFAULT_CONSOLE_LOGLEVEL = 11 +option DEFAULT_CONSOLE_LOGLEVEL = 3 option MAXIMUM_CONSOLE_LOGLEVEL = 11 romimage "fallback" option USE_FALLBACK_IMAGE=1
-
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