[PATCH] flashrom: add i631x LPC support

[Sven Schnelle]

Hi List,

this patch adds support for the Intel i631x Chipset.

Signed-off-by: Sven Schnelle

Index: chipset_enable.c
===================================================================
--- chipset_enable.c	(revision 3845)
+++ chipset_enable.c	(working copy)
@@ -804,6 +804,12 @@
    return 0;
 }

+static int enable_flash_i631x(struct pci_dev *dev, const char *name)
+{
+	pci_write_byte(dev, 0xdc, pci_read_byte(dev, 0xdc) | 0x01);
+	return 0;
+}
+
 /**
  * Usually on the x86 architectures (and on other PC-like platforms like some
  * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
@@ -937,4 +943,5 @@
    {0x1002, 0x4377, "ATI SB400",		enable_flash_sb400},
    {0x1166, 0x0205, "Broadcom HT-1000",	enable_flash_ht1000},
    {0x1022, 0x3000, "AMD Elan SC520",	get_flashbase_sc520},
+	{0x8086, 0x2670, "Intel 631xESB/632xESB/3100",         enable_flash_i631x},
 };

void print_supported_chipsets(void)

[Uwe Hermann]

Hi,

On Sun, Jan 04, 2009 at 10:10:00PM +0100, Sven Schnelle wrote:
> this patch adds support for the Intel i631x Chipset.
>
> Signed-off-by: Sven Schnelle
> Index: chipset_enable.c
>
> --- chipset_enable.c	(revision 3845)
> +++ chipset_enable.c	(working copy)
> @@ -804,6 +804,12 @@
>    return 0;
>  }
>
> +static int enable_flash_i631x(struct pci_dev *dev, const char *name)
> +{
> pci_write_byte(dev, 0xdc, pci_read_byte(dev, 0xdc) | 0x01);
> return 0;
>
> +}
>
> /**
> Usually on the x86 architectures (and on other PC-like platforms like some
> Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
>
> @@ -937,4 +943,5 @@
>    {0x1002, 0x4377, "ATI SB400",		enable_flash_sb400},
>    {0x1166, 0x0205, "Broadcom HT-1000",	enable_flash_ht1000},
>    {0x1022, 0x3000, "AMD Elan SC520",	get_flashbase_sc520},
> {0x8086, 0x2670, "Intel 631xESB/632xESB/3100",         enable_flash_i631x},

We already have

{0x8086, 0x25a1, "Intel 6300ESB",       enable_flash_ich_4e},

Wouldn't enable_flash_ich_dc/enable_flash_ich also work for the
"Intel 631xESB/632xESB/3100" chipset(s)?

Uwe.

[Sven Schnelle]

> > Index: chipset_enable.c
> >
> > --- chipset_enable.c	(revision 3845)
> > +++ chipset_enable.c	(working copy)
> > @@ -804,6 +804,12 @@
> >    return 0;
> >  }
> >
> > +static int enable_flash_i631x(struct pci_dev *dev, const char *name)
> > +{
> > pci_write_byte(dev, 0xdc, pci_read_byte(dev, 0xdc) | 0x01);
> > return 0;
> >
> > +}
> >
> > /**
> > Usually on the x86 architectures (and on other PC-like platforms like some
> > Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
> >
> > @@ -937,4 +943,5 @@
> >    {0x1002, 0x4377, "ATI SB400",		enable_flash_sb400},
> >    {0x1166, 0x0205, "Broadcom HT-1000",	enable_flash_ht1000},
> >    {0x1022, 0x3000, "AMD Elan SC520",	get_flashbase_sc520},
> > {0x8086, 0x2670, "Intel 631xESB/632xESB/3100",         enable_flash_i631x},
>
> We already have
>     {0x8086, 0x25a1, "Intel 6300ESB",       enable_flash_ich_4e},
>
> Wouldn't enable_flash_ich_dc/enable_flash_ich also work for the
> "Intel 631xESB/632xESB/3100" chipset(s)?

Indeed. I should read the source before patching it. :)

Signed-off-by: Sven Schnelle

Index: coreboot-v2/util/flashrom/chipset_enable.c
===================================================================
--- coreboot-v2/util/flashrom/chipset_enable.c	(revision 3845)
+++ coreboot-v2/util/flashrom/chipset_enable.c	(working copy)
@@ -880,6 +880,7 @@
    {0x8086, 0x24cc, "Intel ICH4-M",	enable_flash_ich_4e},
    {0x8086, 0x24d0, "Intel ICH5/ICH5R",	enable_flash_ich_4e},
    {0x8086, 0x25a1, "Intel 6300ESB",	enable_flash_ich_4e},
+	{0x8086, 0x2670, "Intel 631xESB/632xESB/3100",    enable_flash_ich_dc},
    {0x8086, 0x2640, "Intel ICH6/ICH6R",	enable_flash_ich_dc},
    {0x8086, 0x2641, "Intel ICH6-M",	enable_flash_ich_dc},
    {0x8086, 0x5031, "Intel EP80579",	enable_flash_ich7},

[Uwe Hermann]

On Tue, Jan 06, 2009 at 09:37:42AM +0100, Sven Schnelle wrote:
> Signed-off-by: Sven Schnelle

Thanks, r3848.

Uwe.