RE: 4G 4 Rank memory module

[YhLu]

2G modules for CPU0
4G modules for CPU1.

-----Original Message-----
From: Stefan Reinauer [mailto:[e-mail]] 
Sent: Tuesday, November 23, 2004 12:56 PM
To: YhLu
Cc: 'Eric W. Biederman'; 'LinuxBIOS'
Subject: Re: 4G 4 Rank memory module

* YhLu  [041123 20:51]:
> Ram2.00
> rows: 0x0000000d 
> columns: 0x0000000c 
> banks: 0x00000004 
> module data width : 0x00000048 
> side2 banks: 0x00000002
> Ram2.01
> rows: 0x0000000d 
> columns: 0x0000000c 
> banks: 0x00000004 
> module data width : 0x00000048 
> side2 banks: 0x00000004 
> Bad SPD value
>
> CPU0 got 2G modules
> CPU1 got 4G modules
> Side2 banks is different.

Is this with two different modules? Ram2.00 Shows a difference.
Maybe noise on the I2C bus? Ram2.01 seems to be ok..?!?

Stefan

4G 4 Rank memory module

[Stefan Reinauer]

* YhLu  [041123 22:04]:
> 2G modules for CPU0

It seems to dislike the 2G Modules it seems..? Can you try with only the
4G modules?
> 4G modules for CPU1.
>
> -----Original Message-----
> From: Stefan Reinauer [mailto:[e-mail]] 
> Sent: Tuesday, November 23, 2004 12:56 PM
> To: YhLu
> Cc: 'Eric W. Biederman'; 'LinuxBIOS'
> Subject: Re: 4G 4 Rank memory module
> YhLu  [041123 20:51]:
> > Ram2.00
> > rows: 0x0000000d 
> > columns: 0x0000000c 
> > banks: 0x00000004 
> > module data width : 0x00000048 
> > side2 banks: 0x00000002
> > Ram2.01
> > rows: 0x0000000d 
> > columns: 0x0000000c 
> > banks: 0x00000004 
> > module data width : 0x00000048 
> > side2 banks: 0x00000004 
> > Bad SPD value
> >
> > CPU0 got 2G modules
> > CPU1 got 4G modules
> > Side2 banks is different.
>
> Is this with two different modules? Ram2.00 Shows a difference.
> Maybe noise on the I2C bus? Ram2.01 seems to be ok..?!?
>
> Stefan