Re: [coreboot] Kabylake H: SPI Transaction Error at Flash Offset d10000

[Zaolin]

Hey folks,

I guess this is an integration option. IMHO Chipset lockdown should be a
kconfig

option and not be defined as part of the device tree.

Maybe we should do a follow up and fix this issue. BTW same goes for SPI
flash

protection which should be interfaced globally, platform independent.

BR, Zaolin

On 19.11.18 13:04, Jose Trujillo via coreboot wrote:
> Thank you Christian,
>
> Works in my system too, Kabilake FSP2 issue?
> The only small drawback is the disabled ability to upgrade coreboot from itself which correct me if I am wrong is great in terms of security.
> Do you know if there is still the possibility to enable HECI to flash SPI in SMM mode even in CHIPSET_LOCKDOWN?
> But now this system boots fast.
> I owe you one bro.
>
> Jose Trujillo
>
> ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
> On Monday, November 19, 2018 1:15 PM, Christian Gmeiner  wrote:
> > Hi
> >
> > Am Fr., 16. Nov. 2018 um 15:57 Uhr schrieb Jose Trujillo via coreboot
> > [e-mail]:
> > > Hello coreboot engineers:
> > > My Kabylake H system "HM175" with coreboot "bsl6" and "kblrvp" platforms with properly configured I/O failed to save Memory training data to the SPI cache 'RW_MRC_CACHE'.
> > > FMAP: Found "FLASH" version 1.1 at d00000.
> > > FMAP: base = ff000000 size = 1000000 #areas = 4
> > > FMAP: area RW_MRC_CACHE found @ d10000 (65536 bytes)
> > > MRC: Checking cached data update for 'RW_MRC_CACHE'.
> > > SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x100000
> > > MRC: no data in 'RW_MRC_CACHE'
> > > MRC: cache data 'RW_MRC_CACHE' needs update.
> > > SPI Transaction Error at Flash Offset d10000 HSFSTS = 0x01046003
> > > REGF metadata allocation failed: 392 data blocks 4096 total blocks
> > > MRC: Could not find region 'UNIFIED_MRC_CACHE'
> > > FMAP: area RW_MRC_CACHE found @ d10000 (65536 bytes)
> > > MRC: NOT enabling PRR for 'RW_MRC_CACHE'
> > > As a consequence fast boot never works. (fast boot works correctly on my coffeelake system).
> > > Nico helped me to test the system ability to save data to the MRC_CACHE block from linux booting coreboot and I wrote random data to the 'RW_MRC_CACHE' block with the "flashrom" tool succesfully.
> > > Maybe someone that had experience with this issue or have some idea how to fix it can give me advise on how to resolve this problem.
> >
> > I run into the same problem:https://review.coreboot.org/c/coreboot/+/29159
> >
> > Make sure you have this block in your devicetree.cb
> >
> > # Lock Down
> > register "common_soc_config" = "{
> > .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
> > }"
> >
> > greets
> >
> > Christian Gmeiner, MSc
> >
> > https://christian-gmeiner.info

Kabylake H: SPI Transaction Error at Flash Offset d10000

[Jose Trujillo]

I agree.

‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
On Monday, November 19, 2018 3:35 PM, Zaolin  wrote:
> Hey folks,
>
> I guess this is an integration option. IMHO Chipset lockdown should be a
> kconfig
>
> option and not be defined as part of the device tree.
>
> Maybe we should do a follow up and fix this issue. BTW same goes for SPI
> flash
>
> protection which should be interfaced globally, platform independent.
>
> BR, Zaolin
>
> On 19.11.18 13:04, Jose Trujillo via coreboot wrote:
> > Thank you Christian,
> > Works in my system too, Kabilake FSP2 issue?
> > The only small drawback is the disabled ability to upgrade coreboot from itself which correct me if I am wrong is great in terms of security.
> > Do you know if there is still the possibility to enable HECI to flash SPI in SMM mode even in CHIPSET_LOCKDOWN?
> > But now this system boots fast.
> > I owe you one bro.
> > Jose Trujillo
> > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
> > On Monday, November 19, 2018 1:15 PM, Christian Gmeiner [e-mail] wrote:
> > > Hi
> > > Am Fr., 16. Nov. 2018 um 15:57 Uhr schrieb Jose Trujillo via coreboot
> > > [e-mail]:
> > > > Hello coreboot engineers:
> > > > My Kabylake H system "HM175" with coreboot "bsl6" and "kblrvp" platforms with properly configured I/O failed to save Memory training data to the SPI cache 'RW_MRC_CACHE'.
> > > > FMAP: Found "FLASH" version 1.1 at d00000.
> > > > FMAP: base = ff000000 size = 1000000 #areas = 4
> > > > FMAP: area RW_MRC_CACHE found @ d10000 (65536 bytes)
> > > > MRC: Checking cached data update for 'RW_MRC_CACHE'.
> > > > SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x100000
> > > > MRC: no data in 'RW_MRC_CACHE'
> > > > MRC: cache data 'RW_MRC_CACHE' needs update.
> > > > SPI Transaction Error at Flash Offset d10000 HSFSTS = 0x01046003
> > > > REGF metadata allocation failed: 392 data blocks 4096 total blocks
> > > > MRC: Could not find region 'UNIFIED_MRC_CACHE'
> > > > FMAP: area RW_MRC_CACHE found @ d10000 (65536 bytes)
> > > > MRC: NOT enabling PRR for 'RW_MRC_CACHE'
> > > > As a consequence fast boot never works. (fast boot works correctly on my coffeelake system).
> > > > Nico helped me to test the system ability to save data to the MRC_CACHE block from linux booting coreboot and I wrote random data to the 'RW_MRC_CACHE' block with the "flashrom" tool succesfully.
> > > > Maybe someone that had experience with this issue or have some idea how to fix it can give me advise on how to resolve this problem.
> > > > I run into the same problem:https://review.coreboot.org/c/coreboot/+/29159
> > >
> > > Make sure you have this block in your devicetree.cb
> > >
> > > Lock Down
> > >
> > > ==========
> > >
> > > register "common_soc_config" = "{
> > > .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
> > > }"
> > >
> > > greets
> > >
> > > Christian Gmeiner, MSc
> > > https://christian-gmeiner.info