Re: [coreboot] Getting started with Coreboot on Intel Core

[Karl-Heinz Nirschl]

Hi,

no i use crossgcc which looks fine, but still can't hang with postcode 0x23.

if have the following in crt0.disasm:
 153 0148 B023E680 		post_code(0x23)
 154              	
 155 014c E8FCFFFF 		call	stage1_main
 155      FF

and the following in romstage.inc (both from build dir):

stage1_main:
    subl	$24, %esp
/APP
/ 29 "/home/xxx/coreboot/src/cpu/intel/model_6ex/cache_as_ram_disable.c" 1
    movb	0xa4, %al
    outb	%al, $0x80

so i suppose i should at least see postcode 0xa4 if the call
instruction succeeds.

any further hints what i could have done wrong?

regards,

khn

Getting started with Coreboot on Intel Core

[Karl-Heinz Nirschl]

Hi,

i still haven't found whats wrong. toolchain seems to be ok, as
everything works fine with qemu.

could someone confirm that kontron 986lcd-m is working in the current
svn version?

regards,

karl

2010/3/9 Karl-Heinz Nirschl :
> Hi,
>
> no i use crossgcc which looks fine, but still can't hang with postcode 0x23.
>
> if have the following in crt0.disasm:
>  153 0148 B023E680              post_code(0x23)
>  154
>  155 014c E8FCFFFF              call    stage1_main
>  155      FF
>
> and the following in romstage.inc (both from build dir):
>
> stage1_main:
>        subl    $24, %esp
> /APP
> / 29 "/home/xxx/coreboot/src/cpu/intel/model_6ex/cache_as_ram_disable.c" 1
>        movb    0xa4, %al
>        outb    %al, $0x80
>
> so i suppose i should at least see postcode 0xa4 if the call
> instruction succeeds.
>
> any further hints what i could have done wrong?
>
> regards,
>
> khn