[LinuxBIOS] r2632 - in trunk/LinuxBIOSv2/src: include/cpu/amd mainboard/amd/rumba mainboard/olpc/btest mainboard/olpc/rev_a northbridge/amd/gx2
Author: stepan Date: 2007-05-04 21:09:01 +0200 (Fri, 04 May 2007) New Revision: 2632 Modified: trunk/LinuxBIOSv2/src/include/cpu/amd/gx2def.h trunk/LinuxBIOSv2/src/mainboard/amd/rumba/Config.lb trunk/LinuxBIOSv2/src/mainboard/olpc/btest/Config.lb trunk/LinuxBIOSv2/src/mainboard/olpc/btest/mainboard.c trunk/LinuxBIOSv2/src/mainboard/olpc/rev_a/Config.lb trunk/LinuxBIOSv2/src/northbridge/amd/gx2/chipsetinit.c trunk/LinuxBIOSv2/src/northbridge/amd/gx2/grphinit.c trunk/LinuxBIOSv2/src/northbridge/amd/gx2/northbridge.c Log: This repairs the other Geode mainboards so they'll build with the new Geode changes. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> Modified: trunk/LinuxBIOSv2/src/include/cpu/amd/gx2def.h =================================================================== --- trunk/LinuxBIOSv2/src/include/cpu/amd/gx2def.h 2007-05-04 19:05:36 UTC (rev 2631) +++ trunk/LinuxBIOSv2/src/include/cpu/amd/gx2def.h 2007-05-04 19:09:01 UTC (rev 2632) @@ -90,8 +90,6 @@ #define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* 5800xxxx */ /* South Bridge*/ #define SB_PORT 2 /* port of the SouthBridge */ -#define MSR_SB ((SB_PORT << 23) + MSR_PCI) /* 5100xxxx - address to the SouthBridge*/ -#define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift.*/ /**/ @@ -685,182 +683,9 @@ #define POST_INTR_SEG_JUMP (0x0F0) /* vector.asm*/ -/* I don't mind if somebody decides this needs to be in a seperate file. I don't see much point - * in it, either. - * RGM - */ -#define Cx5535_ID ( 0x002A100B) -#define Cx5536_ID ( 0x208F1022) - -/* Cs5535 as follows. */ -/* SB_GLIU*/ -/* port0 - GLIU*/ -/* port1 - GLPCI*/ -/* port2 - USB Controller #2*/ -/* port3 - ATA-5 Controller*/ -/* port4 - MDD*/ -/* port5 - AC97*/ -/* port6 - USB Controller #1*/ -/* port7 - GLCP*/ - - -/* SouthBridge Equates*/ -/* MSR_SB and SB_SHIFT are located in CPU.inc*/ -#define MSR_SB_USB2_MEM_DES ((1<<16) + MSR_SB + 0x25) /* Hack to make USB P4 work */ - -#define MSR_SB_GLIU ((9 << 14) + MSR_SB) /* 51024xxx or 510*xxxx - fake out just like GL0 on CPU. */ -#define MSR_SB_GLPCI (MSR_SB) /* 5100xxxx - don't go to the GLIU */ -#define MSR_SB_USB2 ((2 << SB_SHIFT) + MSR_SB) /* 5120xxxx */ -#define MSR_SB_ATA ((3 << SB_SHIFT) + MSR_SB) /* 5130xxxx */ -#define MSR_SB_MDD ((4 << SB_SHIFT) + MSR_SB) /* 5140xxxx, a.k.a. DIVIL = Diverse Integrated Logic device */ -#define MSR_SB_AC97 ((5 << SB_SHIFT) + MSR_SB) /* 5150xxxx */ -#define MSR_SB_USB1 ((6 << SB_SHIFT) + MSR_SB) /* 5160xxxx */ -#define MSR_SB_GLCP ((7 << SB_SHIFT) + MSR_SB) /* 5170xxxx */ - /* */ -/* GLIU*/ +/* SB LBAR IO + MEMORY MAP*/ /* */ -#define GLIU_SB_GLD_MSR_CAP ( MSR_SB_GLIU + 0x00) -#define GLIU_SB_GLD_MSR_CONF ( MSR_SB_GLIU + 0x01) -#define GLIU_SB_GLD_MSR_PM ( MSR_SB_GLIU + 0x04) - -/* */ -/* USB1*/ -/* */ -#define USB1_SB_GLD_MSR_CAP ( MSR_SB_USB1 + 0x00) -#define USB1_SB_GLD_MSR_CONF ( MSR_SB_USB1 + 0x01) -#define USB1_SB_GLD_MSR_PM ( MSR_SB_USB1 + 0x04) -/* */ -/* USB2*/ -/* */ - -#define USB2_SB_GLD_MSR_CAP ( MSR_SB_USB2 + 0x00) -#define USB2_SB_GLD_MSR_CONF ( MSR_SB_USB2 + 0x01) -#define USB2_SB_GLD_MSR_PM ( MSR_SB_USB2 + 0x04) -#define USB2_SB_GLD_MSR_OHCI_BASE ( MSR_SB_USB2 + 0x08) -#define USB2_SB_GLD_MSR_EHCI_BASE ( MSR_SB_USB2 + 0x09) -#define USB2_SB_GLD_MSR_DEVCTL_BASE ( MSR_SB_USB2 + 0x0A) -#define USB2_SB_GLD_MSR_UOC_BASE ( MSR_SB_USB2 + 0x0B) /* Option controller base */ - -/* */ -/* ATA*/ -/* */ -#define ATA_SB_GLD_MSR_CAP ( MSR_SB_ATA + 0x00) -#define ATA_SB_GLD_MSR_CONF ( MSR_SB_ATA + 0x01) -#define ATA_SB_GLD_MSR_ERR ( MSR_SB_ATA + 0x03) -#define ATA_SB_GLD_MSR_PM ( MSR_SB_ATA + 0x04) - -/* */ -/* AC97*/ -/* */ -#define AC97_SB_GLD_MSR_CAP ( MSR_SB_AC97 + 0x00) -#define AC97_SB_GLD_MSR_CONF ( MSR_SB_AC97 + 0x01) -#define AC97_SB_GLD_MSR_PM ( MSR_SB_AC97 + 0x04) - -/* */ -/* GLPCI*/ -/* */ -#define GLPCI_SB_GLD_MSR_CAP ( MSR_SB_GLPCI + 0x00) -#define GLPCI_SB_GLD_MSR_CONF ( MSR_SB_GLPCI + 0x01) -#define GLPCI_SB_GLD_MSR_PM ( MSR_SB_GLPCI + 0x04) -#define GLPCI_SB_CTRL ( MSR_SB_GLPCI + 0x10) -#define GLPCI_CRTL_PPIDE_SET ( 1 << 17) -/* */ -/* GLCP*/ -/* */ -#define GLCP_SB_GLD_MSR_CAP ( MSR_SB_GLCP + 0x00) -#define GLCP_SB_GLD_MSR_CONF ( MSR_SB_GLCP + 0x01) -#define GLCP_SB_GLD_MSR_PM ( MSR_SB_GLCP + 0x04) - -/* */ -/* MDD*/ -/* */ -#define MDD_SB_GLD_MSR_CAP ( MSR_SB_MDD + 0x00) -#define MDD_SB_GLD_MSR_CONF ( MSR_SB_MDD + 0x01) -#define MDD_SB_GLD_MSR_PM ( MSR_SB_MDD + 0x04) -#define LBAR_EN ( 0x01) -#define IO_MASK ( 0x1f) -#define MEM_MASK ( 0x0FFFFF) -#define MDD_LBAR_IRQ ( MSR_SB_MDD + 0x08) -#define MDD_LBAR_KEL1 ( MSR_SB_MDD + 0x09) -#define MDD_LBAR_KEL2 ( MSR_SB_MDD + 0x0A) -#define MDD_LBAR_SMB ( MSR_SB_MDD + 0x0B) -#define MDD_LBAR_GPIO ( MSR_SB_MDD + 0x0C) -#define MDD_LBAR_MFGPT ( MSR_SB_MDD + 0x0D) -#define MDD_LBAR_ACPI ( MSR_SB_MDD + 0x0E) -#define MDD_LBAR_PMS ( MSR_SB_MDD + 0x0F) - -#define MDD_LBAR_FLSH0 ( MSR_SB_MDD + 0x010) -#define MDD_LBAR_FLSH1 ( MSR_SB_MDD + 0x011) -#define MDD_LBAR_FLSH2 ( MSR_SB_MDD + 0x012) -#define MDD_LBAR_FLSH3 ( MSR_SB_MDD + 0x013) -#define MDD_LEG_IO ( MSR_SB_MDD + 0x014) -#define MDD_PIN_OPT ( MSR_SB_MDD + 0x015) -#define MDD_SOFT_IRQ ( MSR_SB_MDD + 0x016) -#define MDD_SOFT_RESET ( MSR_SB_MDD + 0x017) -#define MDD_NORF_CNTRL ( MSR_SB_MDD + 0x018) -#define MDD_NORF_T01 ( MSR_SB_MDD + 0x019) -#define MDD_NORF_T23 ( MSR_SB_MDD + 0x01A) -#define MDD_NANDF_DATA ( MSR_SB_MDD + 0x01B) -#define MDD_NADF_CNTL ( MSR_SB_MDD + 0x01C) -#define MDD_AC_DMA ( MSR_SB_MDD + 0x01E) -#define MDD_KEL_CNTRL ( MSR_SB_MDD + 0x01F) - -#define MDD_IRQM_YLOW ( MSR_SB_MDD + 0x020) -#define MDD_IRQM_YHIGH ( MSR_SB_MDD + 0x021) -#define MDD_IRQM_ZLOW ( MSR_SB_MDD + 0x022) -#define MDD_IRQM_ZHIGH ( MSR_SB_MDD + 0x023) -#define MDD_IRQM_PRIM ( MSR_SB_MDD + 0x024) -#define MDD_IRQM_LPC ( MSR_SB_MDD + 0x025) -#define MDD_IRQM_LXIRR ( MSR_SB_MDD + 0x026) -#define MDD_IRQM_HXIRR ( MSR_SB_MDD + 0x027) - -#define MDD_MFGPT_IRQ ( MSR_SB_MDD + 0x028) -#define MDD_MFGPT_NR ( MSR_SB_MDD + 0x029) -#define MDD_MFGPT_RES0 ( MSR_SB_MDD + 0x02A) -#define MDD_MFGPT_RES1 ( MSR_SB_MDD + 0x02B) - -#define MDD_FLOP_S3F2 ( MSR_SB_MDD + 0x030) -#define MDD_FLOP_S3F7 ( MSR_SB_MDD + 0x031) -#define MDD_FLOP_S372 ( MSR_SB_MDD + 0x032) -#define MDD_FLOP_S377 ( MSR_SB_MDD + 0x033) - -#define MDD_PIC_S ( MSR_SB_MDD + 0x034) -#define MDD_PIT_S ( MSR_SB_MDD + 0x036) -#define MDD_PIT_CNTRL ( MSR_SB_MDD + 0x037) - -#define MDD_UART1_MOD ( MSR_SB_MDD + 0x038) -#define MDD_UART1_DON ( MSR_SB_MDD + 0x039) -#define MDD_UART1_CONF ( MSR_SB_MDD + 0x03A) -#define MDD_UART2_MOD ( MSR_SB_MDD + 0x03C) -#define MDD_UART2_DON ( MSR_SB_MDD + 0x03D) -#define MDD_UART2_CONF ( MSR_SB_MDD + 0x03E) - -#define MDD_DMA_MAP ( MSR_SB_MDD + 0x040) -#define MDD_DMA_SHAD1 ( MSR_SB_MDD + 0x041) -#define MDD_DMA_SHAD2 ( MSR_SB_MDD + 0x042) -#define MDD_DMA_SHAD3 ( MSR_SB_MDD + 0x043) -#define MDD_DMA_SHAD4 ( MSR_SB_MDD + 0x044) -#define MDD_DMA_SHAD5 ( MSR_SB_MDD + 0x045) -#define MDD_DMA_SHAD6 ( MSR_SB_MDD + 0x046) -#define MDD_DMA_SHAD7 ( MSR_SB_MDD + 0x047) -#define MDD_DMA_SHAD8 ( MSR_SB_MDD + 0x048) -#define MDD_DMA_SHAD9 ( MSR_SB_MDD + 0x049) - -#define MDD_LPC_EADDR ( MSR_SB_MDD + 0x04C) -#define MDD_LPC_ESTAT ( MSR_SB_MDD + 0x04D) -#define MDD_LPC_SIRQ ( MSR_SB_MDD + 0x04E) -#define MDD_LPC_RES ( MSR_SB_MDD + 0x04F) - -#define MDD_PML_TMR ( MSR_SB_MDD + 0x050) -#define MDD_RTC_RAM_LO_CK ( MSR_SB_MDD + 0x054) -#define MDD_RTC_DOMA_IND ( MSR_SB_MDD + 0x055) -#define MDD_RTC_MONA_IND ( MSR_SB_MDD + 0x056) -#define MDD_RTC_CENTURY_OFFSET ( MSR_SB_MDD + 0x057) - -/* */ -/* LBAR IO + MEMORY MAP*/ -/* */ #define SMBUS_BASE ( 0x6000) #define GPIO_BASE ( 0x6100) #define MFGPT_BASE ( 0x6200) @@ -868,269 +693,4 @@ #define PMLogic_BASE ( 0x9D00) - -/* ***********************************************************/ -/* LBUS Device Equates - */ -/* ***********************************************************/ - -/* */ -/* SMBus*/ -/* */ - -#define SMBUS_SMBSDA ( SMBUS_BASE + 0x00) -#define SMBUS_SMBST ( SMBUS_BASE + 0x01) -#define SMBST_SLVSTP_SET ( 1 << 7) -#define SMBST_SDAST_SET ( 1 << 6) -#define SMBST_BER_SET ( 1 << 5) -#define SMBST_NEGACK_SET ( 1 << 4) -#define SMBST_STASTR_SET ( 1 << 3) -#define SMBST_NMATCH_SET ( 1 << 2) -#define SMBST_MASTER_SET ( 1 << 1) -#define SMBST_XMIT_SET ( 1 << 0) -#define SMBUS_SMBCST ( SMBUS_BASE + 0x02) -#define SMBCST_TGSCL_SET ( 1 << 5) -#define SMBCST_TSDA_SET ( 1 << 4) -#define SMBCST_GCMTCH_SET ( 1 << 3) -#define SMBCST_MATCH_SET ( 1 << 2) -#define SMBCST_BB_SET ( 1 << 1) -#define SMBCST_BUSY_SET ( 1 << 0) -#define SMBUS_SMBCTL1 ( SMBUS_BASE + 0x03) -#define SMBCTL1_STASTRE_SET ( 1 << 7) -#define SMBCTL1_NMINTE_SET ( 1 << 6) -#define SMBCTL1_GCMEN_SET ( 1 << 5) -#define SMBCTL1_RECACK_SET ( 1 << 4) -#define SMBCTL1_DMAEN_SET ( 1 << 3) -#define SMBCTL1_INTEN_SET ( 1 << 2) -#define SMBCTL1_STOP_SET ( 1 << 1) -#define SMBCTL1_START_SET ( 1 << 0) -#define SMBUS_SMBADDR ( SMBUS_BASE + 0x04) -#define SMBADDR_SAEN_SET ( 1 << 7) -#define SMBUS_SMBCTL2 ( SMBUS_BASE + 0x05) -#define SMBCTL2_SCLFRQ_SHIFT ( 1 << 1) -#define SMBCTL2_ENABLE_SET ( 1 << 0) - -/* */ -/* GPIO*/ -/* */ - -#define GPIOL_0_SET ( 1 << 0) -#define GPIOL_1_SET ( 1 << 1) -#define GPIOL_2_SET ( 1 << 2) -#define GPIOL_3_SET ( 1 << 3) -#define GPIOL_4_SET ( 1 << 4) -#define GPIOL_5_SET ( 1 << 5) -#define GPIOL_6_SET ( 1 << 6) -#define GPIOL_7_SET ( 1 << 7) -#define GPIOL_8_SET ( 1 << 8) -#define GPIOL_9_SET ( 1 << 9) -#define GPIOL_10_SET ( 1 << 10) -#define GPIOL_11_SET ( 1 << 11) -#define GPIOL_12_SET ( 1 << 12) -#define GPIOL_13_SET ( 1 << 13) -#define GPIOL_14_SET ( 1 << 14) -#define GPIOL_15_SET ( 1 << 15) - -#define GPIOL_0_CLEAR ( 1 << 16) -#define GPIOL_1_CLEAR ( 1 << 17) -#define GPIOL_2_CLEAR ( 1 << 18) -#define GPIOL_3_CLEAR ( 1 << 19) -#define GPIOL_4_CLEAR ( 1 << 20) -#define GPIOL_5_CLEAR ( 1 << 21) -#define GPIOL_6_CLEAR ( 1 << 22) -#define GPIOL_7_CLEAR ( 1 << 23) -#define GPIOL_8_CLEAR ( 1 << 24) -#define GPIOL_9_CLEAR ( 1 << 25) -#define GPIOL_10_CLEAR ( 1 << 26) -#define GPIOL_11_CLEAR ( 1 << 27) -#define GPIOL_12_CLEAR ( 1 << 28) -#define GPIOL_13_CLEAR ( 1 << 29) -#define GPIOL_14_CLEAR ( 1 << 30) -#define GPIOL_15_CLEAR ( 1 << 31) - -#define GPIOH_16_SET ( 1 << 0) -#define GPIOH_17_SET ( 1 << 1) -#define GPIOH_18_SET ( 1 << 2) -#define GPIOH_19_SET ( 1 << 3) -#define GPIOH_20_SET ( 1 << 4) -#define GPIOH_21_SET ( 1 << 5) -#define GPIOH_22_SET ( 1 << 6) -#define GPIOH_23_SET ( 1 << 7) -#define GPIOH_24_SET ( 1 << 8) -#define GPIOH_25_SET ( 1 << 9) -#define GPIOH_26_SET ( 1 << 10) -#define GPIOH_27_SET ( 1 << 11) -#define GPIOH_28_SET ( 1 << 12) -#define GPIOH_29_SET ( 1 << 13) -#define GPIOH_30_SET ( 1 << 14) -#define GPIOH_31_SET ( 1 << 15) - -#define GPIOH_16_CLEAR ( 1 << 16) -#define GPIOH_17_CLEAR ( 1 << 17) -#define GPIOH_18_CLEAR ( 1 << 18) -#define GPIOH_19_CLEAR ( 1 << 19) -#define GPIOH_20_CLEAR ( 1 << 20) -#define GPIOH_21_CLEAR ( 1 << 21) -#define GPIOH_22_CLEAR ( 1 << 22) -#define GPIOH_23_CLEAR ( 1 << 23) -#define GPIOH_24_CLEAR ( 1 << 24) -#define GPIOH_25_CLEAR ( 1 << 25) -#define GPIOH_26_CLEAR ( 1 << 26) -#define GPIOH_27_CLEAR ( 1 << 27) -#define GPIOH_28_CLEAR ( 1 << 28) -#define GPIOH_29_CLEAR ( 1 << 29) -#define GPIOH_30_CLEAR ( 1 << 30) -#define GPIOH_31_CLEAR ( 1 << 31) - - -/* GPIO LOW Bank Bit Registers*/ -#define GPIOL_OUTPUT_VALUE ( GPIO_BASE + 0x00) -#define GPIOL_OUTPUT_ENABLE ( GPIO_BASE + 0x04) -#define GPIOL_OUT_OPENDRAIN ( GPIO_BASE + 0x08) -#define GPIOL_OUTPUT_INVERT_ENABLE ( GPIO_BASE + 0x0C) -#define GPIOL_OUT_AUX1_SELECT ( GPIO_BASE + 0x10) -#define GPIOL_OUT_AUX2_SELECT ( GPIO_BASE + 0x14) -#define GPIOL_PULLUP_ENABLE ( GPIO_BASE + 0x18) -#define GPIOL_PULLDOWN_ENABLE ( GPIO_BASE + 0x1C) -#define GPIOL_INPUT_ENABLE ( GPIO_BASE + 0x20) -#define GPIOL_INPUT_INVERT_ENABLE ( GPIO_BASE + 0x24) -#define GPIOL_IN_FILTER_ENABLE ( GPIO_BASE + 0x28) -#define GPIOL_IN_EVENTCOUNT_ENABLE ( GPIO_BASE + 0x2C) -#define GPIOL_READ_BACK ( GPIO_BASE + 0x30) -#define GPIOL_IN_AUX1_SELECT ( GPIO_BASE + 0x34) -#define GPIOL_EVENTS_ENABLE ( GPIO_BASE + 0x38) -#define GPIOL_LOCK_ENABLE ( GPIO_BASE + 0x3C) -#define GPIOL_IN_POSEDGE_ENABLE ( GPIO_BASE + 0x40) -#define GPIOL_IN_NEGEDGE_ENABLE ( GPIO_BASE + 0x44) -#define GPIOL_IN_POSEDGE_STATUS ( GPIO_BASE + 0x48) -#define GPIOL_IN_NEGEDGE_STATUS ( GPIO_BASE + 0x4C) - -/* GPIO High Bank Bit Registers*/ -#define GPIOH_OUTPUT_VALUE ( GPIO_BASE + 0x80) -#define GPIOH_OUTPUT_ENABLE ( GPIO_BASE + 0x84) -#define GPIOH_OUT_OPENDRAIN ( GPIO_BASE + 0x88) -#define GPIOH_OUTPUT_INVERT_ENABLE ( GPIO_BASE + 0x8C) -#define GPIOH_OUT_AUX1_SELECT ( GPIO_BASE + 0x90) -#define GPIOH_OUT_AUX2_SELECT ( GPIO_BASE + 0x94) -#define GPIOH_PULLUP_ENABLE ( GPIO_BASE + 0x98) -#define GPIOH_PULLDOWN_ENABLE ( GPIO_BASE + 0x9C) -#define GPIOH_INPUT_ENABLE ( GPIO_BASE + 0x0A0) -#define GPIOH_INPUT_INVERT_ENABLE ( GPIO_BASE + 0x0A4) -#define GPIOH_IN_FILTER_ENABLE ( GPIO_BASE + 0x0A8) -#define GPIOH_IN_EVENTCOUNT_ENABLE ( GPIO_BASE + 0x0AC) -#define GPIOH_READ_BACK ( GPIO_BASE + 0x0B0) -#define GPIOH_IN_AUX1_SELECT ( GPIO_BASE + 0x0B4) -#define GPIOH_EVENTS_ENABLE ( GPIO_BASE + 0x0B8) -#define GPIOH_LOCK_ENABLE ( GPIO_BASE + 0x0BC) -#define GPIOH_IN_POSEDGE_ENABLE ( GPIO_BASE + 0x0C0) -#define GPIOH_IN_NEGEDGE_ENABLE ( GPIO_BASE + 0x0C4) -#define GPIOH_IN_POSEDGE_STATUS ( GPIO_BASE + 0x0C8) -#define GPIOH_IN_NEGEDGE_STATUS ( GPIO_BASE + 0x0CC) - -/* Input Conditioning Function Registers*/ -#define GPIO_00_FILTER_AMOUNT ( GPIO_BASE + 0x50) -#define GPIO_00_FILTER_COUNT ( GPIO_BASE + 0x52) -#define GPIO_00_EVENT_COUNT ( GPIO_BASE + 0x54) -#define GPIO_00_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x56) -#define GPIO_01_FILTER_AMOUNT ( GPIO_BASE + 0x58) -#define GPIO_01_FILTER_COUNT ( GPIO_BASE + 0x5A) -#define GPIO_01_EVENT_COUNT ( GPIO_BASE + 0x5C) -#define GPIO_01_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x5E) -#define GPIO_02_FILTER_AMOUNT ( GPIO_BASE + 0x60) -#define GPIO_02_FILTER_COUNT ( GPIO_BASE + 0x62) -#define GPIO_02_EVENT_COUNT ( GPIO_BASE + 0x64) -#define GPIO_02_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x66) -#define GPIO_03_FILTER_AMOUNT ( GPIO_BASE + 0x68) -#define GPIO_03_FILTER_COUNT ( GPIO_BASE + 0x6A) -#define GPIO_03_EVENT_COUNT ( GPIO_BASE + 0x6C) -#define GPIO_03_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x6E) -#define GPIO_04_FILTER_AMOUNT ( GPIO_BASE + 0x70) -#define GPIO_04_FILTER_COUNT ( GPIO_BASE + 0x72) -#define GPIO_04_EVENT_COUNT ( GPIO_BASE + 0x74) -#define GPIO_04_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x76) -#define GPIO_05_FILTER_AMOUNT ( GPIO_BASE + 0x78) -#define GPIO_05_FILTER_COUNT ( GPIO_BASE + 0x7A) -#define GPIO_05_EVENT_COUNT ( GPIO_BASE + 0x7C) -#define GPIO_05_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x7E) -#define GPIO_06_FILTER_AMOUNT ( GPIO_BASE + 0x0D0) -#define GPIO_06_FILTER_COUNT ( GPIO_BASE + 0x0D2) -#define GPIO_06_EVENT_COUNT ( GPIO_BASE + 0x0D4) -#define GPIO_06_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x0D6) -#define GPIO_07_FILTER_AMOUNT ( GPIO_BASE + 0x0D8) -#define GPIO_07_FILTER_COUNT ( GPIO_BASE + 0x0DA) -#define GPIO_07_EVENT_COUNT ( GPIO_BASE + 0x0DC) -#define GPIO_07_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x0DE) - -/* R/W GPIO Interrupt &PME Mapper Registers*/ -#define GPIO_MAPPER_X ( GPIO_BASE + 0x0E0) -#define GPIO_MAPPER_Y ( GPIO_BASE + 0x0E4) -#define GPIO_MAPPER_Z ( GPIO_BASE + 0x0E8) -#define GPIO_MAPPER_W ( GPIO_BASE + 0x0EC) -#define GPIO_FE_SELECT_0 ( GPIO_BASE + 0x0F0) -#define GPIO_FE_SELECT_1 ( GPIO_BASE + 0x0F1) -#define GPIO_FE_SELECT_2 ( GPIO_BASE + 0x0F2) -#define GPIO_FE_SELECT_3 ( GPIO_BASE + 0x0F3) -#define GPIO_FE_SELECT_4 ( GPIO_BASE + 0x0F4) -#define GPIO_FE_SELECT_5 ( GPIO_BASE + 0x0F5) -#define GPIO_FE_SELECT_6 ( GPIO_BASE + 0x0F6) -#define GPIO_FE_SELECT_7 ( GPIO_BASE + 0x0F7) - -/* Event Counter Decrement Registers*/ -#define GPIOL_IN_EVENT_DECREMENT ( GPIO_BASE + 0x0F8) -#define GPIOH_IN_EVENT_DECREMENT ( GPIO_BASE + 0x0FC) - -/* This is for 286reset compatibility. 0xCange to mat0xc 5535 virtualized stuff.*/ -#define FUNC0 ( 0x90) - - -/* sworley, PMC register*/ -#define PM_SSD ( PMLogic_BASE + 0x00) -#define PM_SCXA ( PMLogic_BASE + 0x04) -#define PM_SCYA ( PMLogic_BASE + 0x08) -#define PM_SODA ( PMLogic_BASE + 0x0C) -#define PM_SCLK ( PMLogic_BASE + 0x10) -#define PM_SED ( PMLogic_BASE + 0x14) -#define PM_SCXD ( PMLogic_BASE + 0x18) -#define PM_SCYD ( PMLogic_BASE + 0x1C) -#define PM_SIDD ( PMLogic_BASE + 0x20) -#define PM_WKD ( PMLogic_BASE + 0x30) -#define PM_WKXD ( PMLogic_BASE + 0x34) -#define PM_RD ( PMLogic_BASE + 0x38) -#define PM_WKXA ( PMLogic_BASE + 0x3C) -#define PM_FSD ( PMLogic_BASE + 0x40) -#define PM_TSD ( PMLogic_BASE + 0x44) -#define PM_PSD ( PMLogic_BASE + 0x48) -#define PM_NWKD ( PMLogic_BASE + 0x4C) -#define PM_AWKD ( PMLogic_BASE + 0x50) -#define PM_SSC ( PMLogic_BASE + 0x54) - - -/* FLASH device macros */ -#define FLASH_TYPE_NONE 0 /* No flash device installed */ -#define FLASH_TYPE_NAND 1 /* NAND device */ -#define FLASH_TYPE_NOR 2 /* NOR device */ - -#define FLASH_IF_MEM 1 /* Memory or memory-mapped I/O interface for Flash device */ -#define FLASH_IF_IO 2 /* I/O interface for Flash device */ - -/* Flash Memory Mask values */ -#define FLASH_MEM_DEFAULT 0x00000000 -#define FLASH_MEM_4K 0xFFFFF000 -#define FLASH_MEM_8K 0xFFFFE000 -#define FLASH_MEM_16K 0xFFFFC000 -#define FLASH_MEM_128K 0xFFFE0000 -#define FLASH_MEM_512K 0xFFFC0000 -#define FLASH_MEM_4M 0xFFC00000 -#define FLASH_MEM_8M 0xFF800000 -#define FLASH_MEM_16M 0xFF000000 - -/* Flash IO Mask values */ -#define FLASH_IO_DEFAULT 0x00000000 -#define FLASH_IO_16B 0x0000FFF0 -#define FLASH_IO_32B 0x0000FFE0 -#define FLASH_IO_64B 0x0000FFC0 -#define FLASH_IO_128B 0x0000FF80 -#define FLASH_IO_256B 0x0000FF00 - - - #endif /* CPU_AMD_GX2DEF_H */ Modified: trunk/LinuxBIOSv2/src/mainboard/amd/rumba/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/rumba/Config.lb 2007-05-04 19:05:36 UTC (rev 2631) +++ trunk/LinuxBIOSv2/src/mainboard/amd/rumba/Config.lb 2007-05-04 19:09:01 UTC (rev 2632) @@ -134,8 +134,6 @@ device pci 1.1 on end chip southbridge/amd/cs5536 register "lpc_serirq_enable" = "0x80" # enabled with default timing - register "lpc_irq" = "((1<<3)|(1<<4))" # IRQ 3 & 4 - register "enable_gpio0_inta" = "1" device pci d.0 on end # Realtek 8139 LAN device pci f.0 on end # ISA Bridge device pci f.2 on end # IDE Controller Modified: trunk/LinuxBIOSv2/src/mainboard/olpc/btest/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/olpc/btest/Config.lb 2007-05-04 19:05:36 UTC (rev 2631) +++ trunk/LinuxBIOSv2/src/mainboard/olpc/btest/Config.lb 2007-05-04 19:09:01 UTC (rev 2632) @@ -144,17 +144,17 @@ # Active(Quiet) mode. Save power.... # SIRQ Enable = Enabled # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK - register "lpc_irq" = "0x00001002" - register "lpc_serirq_enable" = "0xEFFD0080" - register "enable_gpio0_inta" = "1" - register "enable_ide_nand_flash" = "1" - register "enable_uarta" = "1" - register "enable_USBP4_host" = "1" - register "audio_irq" = "5" - register "usbf4_irq" = "10" - register "usbf5_irq" = "10" - register "usbf6_irq" = "0" - register "usbf7_irq" = "0" + #register "lpc_irq" = "0x00001002" + #register "lpc_serirq_enable" = "0xEFFD0080" + #register "enable_gpio0_inta" = "1" + #register "enable_ide_nand_flash" = "1" + #register "enable_uarta" = "1" + #register "enable_USBP4_host" = "1" + #register "audio_irq" = "5" + #register "usbf4_irq" = "10" + #register "usbf5_irq" = "10" + #register "usbf6_irq" = "0" + #register "usbf7_irq" = "0" device pci d.0 on end # Realtek 8139 LAN device pci f.0 on end # ISA Bridge device pci f.2 on end # IDE Controller Modified: trunk/LinuxBIOSv2/src/mainboard/olpc/btest/mainboard.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/olpc/btest/mainboard.c 2007-05-04 19:05:36 UTC (rev 2631) +++ trunk/LinuxBIOSv2/src/mainboard/olpc/btest/mainboard.c 2007-05-04 19:09:01 UTC (rev 2632) @@ -7,6 +7,7 @@ #include <pc80/mc146818rtc.h> #include "chip.h" #include "../southbridge/amd/cs5536/cs5536_smbus2.h" +#include <cpu/amd/vr.h> /* Borrowed from mc146818rtc.c */ Modified: trunk/LinuxBIOSv2/src/mainboard/olpc/rev_a/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/olpc/rev_a/Config.lb 2007-05-04 19:05:36 UTC (rev 2631) +++ trunk/LinuxBIOSv2/src/mainboard/olpc/rev_a/Config.lb 2007-05-04 19:09:01 UTC (rev 2632) @@ -144,17 +144,17 @@ # Active(Quiet) mode. Save power.... # SIRQ Enable = Enabled # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK - register "lpc_irq" = "0x00001002" - register "lpc_serirq_enable" = "0xEFFD0080" - register "enable_gpio0_inta" = "1" - register "enable_ide_nand_flash" = "1" - register "enable_uarta" = "1" - register "enable_USBP4_host" = "1" - register "audio_irq" = "5" - register "usbf4_irq" = "10" - register "usbf5_irq" = "10" - register "usbf6_irq" = "0" - register "usbf7_irq" = "0" + #register "lpc_irq" = "0x00001002" + #register "lpc_serirq_enable" = "0xEFFD0080" + #register "enable_gpio0_inta" = "1" + #register "enable_ide_nand_flash" = "1" + #register "enable_uarta" = "1" + #register "enable_USBP4_host" = "1" + #register "audio_irq" = "5" + #register "usbf4_irq" = "10" + #register "usbf5_irq" = "10" + #register "usbf6_irq" = "0" + #register "usbf7_irq" = "0" device pci d.0 on end # Realtek 8139 LAN device pci f.0 on end # ISA Bridge device pci f.2 on end # IDE Controller Modified: trunk/LinuxBIOSv2/src/northbridge/amd/gx2/chipsetinit.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/gx2/chipsetinit.c 2007-05-04 19:05:36 UTC (rev 2631) +++ trunk/LinuxBIOSv2/src/northbridge/amd/gx2/chipsetinit.c 2007-05-04 19:09:01 UTC (rev 2632) @@ -12,6 +12,7 @@ #include <cpu/amd/gx2def.h> #include <cpu/x86/msr.h> #include <cpu/x86/cache.h> +#include "../../../southbridge/amd/cs5536/cs5536.h" /* the structs in this file only set msr.lo. But ... that may not always be true */ Modified: trunk/LinuxBIOSv2/src/northbridge/amd/gx2/grphinit.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/gx2/grphinit.c 2007-05-04 19:05:36 UTC (rev 2631) +++ trunk/LinuxBIOSv2/src/northbridge/amd/gx2/grphinit.c 2007-05-04 19:09:01 UTC (rev 2632) @@ -4,31 +4,8 @@ #define VIDEO_MB 8 // MB of video memory -/* - * Write to a Virtual Register - * AX = Class/Index - * CX = data to write - */ -void vrWrite(uint16_t wClassIndex, uint16_t wData) -{ - outl(((uint32_t) VR_UNLOCK << 16) | wClassIndex, VRC_INDEX); - outw(wData, VRC_DATA); -} /* - * Read from a Virtual Register - * AX = Class/Index - * Returns a 16-bit word of data - */ -uint16_t vrRead(uint16_t wClassIndex) -{ - uint16_t wData; - outl(((uint32_t) VR_UNLOCK << 16) | wClassIndex, VRC_INDEX); - wData = inw(VRC_DATA); - return wData; -} - -/* * This function mirrors the Graphics_Init routine in GeodeROM. */ void graphics_init(void) Modified: trunk/LinuxBIOSv2/src/northbridge/amd/gx2/northbridge.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/gx2/northbridge.c 2007-05-04 19:05:36 UTC (rev 2631) +++ trunk/LinuxBIOSv2/src/northbridge/amd/gx2/northbridge.c 2007-05-04 19:09:01 UTC (rev 2632) @@ -13,6 +13,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/cache.h> #include <cpu/amd/vr.h> +#include "../../../southbridge/amd/cs5536/cs5536.h" #define VIDEO_MB 8 extern void graphics_init(void);
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