On Sat, Oct 27, 2012 at 02:48:34PM +0300, Eino-Pekka Kanto wrote:
Hello!
I burned coreboot to my Gigabyte 6bxe rev 1.9 motherboard, using SeaBIOS as payload. Floppy drive didn't work (marked as WIP), but otherwise it did support Voodoo 3dfx in AGP. 120Gb WD1200 drive also worked, but Toshiba XM-6402B drive didn't. I tested it with Lubuntu 8.04 CD-R (tested with that same drive in vendor BIOS and it worked). The drive opens and closes but SeaBIOS doesn't boot it.
SeaBIOS config: http://dpaste.com/818910/ Coreboot config: http://dpaste.com/818909/
Coreboot and SeaBIOS logs from serial port (without any drives):
[...]
No bootable device. Retrying in 60 seconds.
Ps. will there be floppy support soon for this motherboard?
Are you trying to boot from a floppy drive? It's not clear from your report.
SeaBIOS doesn't enable floppies on coreboot, because it has never been tested on real hardware. If you want to give it a test you could try applying this patch to the SeaBIOS code:
--- a/src/floppy.c +++ b/src/floppy.c @@ -136,7 +136,7 @@ floppy_setup(void) dprintf(3, "init floppy drives\n");
if (CONFIG_COREBOOT) { - // XXX - disable floppies on coreboot for now. + addFloppy(0, 4); } else { u8 type = inb_cmos(CMOS_FLOPPY_DRIVE_TYPE); if (type & 0xf0)
I really have no idea if it will work on real hardware. It certainly wont work with anything other than a 1.44Mbit 3.5" drive.
-Kevin
I tried to boot from floppy AND cd-rom for installing GNU/Linux but either doesn't work. I managed to install Arch Linux by writing extlinux bootloader and then netbooting from gpxe. But the main thin about this post is the cd-rom drive.
I will try the patch next time I rebuild my BIOS.
Here's log from serial port with only cd-rom drive with good cd-rom inside it and floppy drive wiithout any floppies.
coreboot- Sat Oct 27 10:04:47 EEST 2012 starting... Loading image. CBFS: Looking for 'fallback/coreboot_ram' CBFS: found. CBFS: loading stage fallback/coreboot_ram @ 0x100000 (278528 bytes), entry @ 0x100000 Jumping to image. POST: 0x80 POST: 0x39 coreboot- Sat Oct 27 10:04:47 EEST 2012 booting... POST: 0x40 clocks_per_usec: 451 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:07.0: enabled 1 PNP: 03f0.0: enabled 1 PNP: 03f0.1: enabled 1 PNP: 03f0.2: enabled 1 PNP: 03f0.3: enabled 1 PNP: 03f0.4: enabled 1 PNP: 03f0.5: enabled 1 PNP: 03f0.6: enabled 1 PNP: 03f0.7: enabled 1 PCI: 00:07.1: enabled 1 PCI: 00:07.2: enabled 1 PCI: 00:07.3: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:07.0: enabled 1 PNP: 03f0.0: enabled 1 PNP: 03f0.1: enabled 1 PNP: 03f0.2: enabled 1 PNP: 03f0.3: enabled 1 PNP: 03f0.4: enabled 1 PNP: 03f0.5: enabled 1 PNP: 03f0.6: enabled 1 PNP: 03f0.7: enabled 1 PCI: 00:07.1: enabled 1 PCI: 00:07.2: enabled 1 PCI: 00:07.3: enabled 1 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 PCI: 00:00.0 [8086/7190] ops PCI: 00:00.0 [8086/7190] enabled PCI: 00:01.0 [8086/7191] enabled PCI: 00:07.0 [8086/7110] bus ops PCI: 00:07.0 [8086/7110] enabled PCI: 00:07.1 [8086/7111] ops PCI: 00:07.1 [8086/7111] enabled PCI: 00:07.2 [8086/7112] ops PCI: 00:07.2 [8086/7112] enabled PCI: 00:07.3 [8086/7113] bus ops pwrmgt_enable: gpo default missing in devicetree.cb! PCI: 00:07.3 [8086/7113] enabled PCI: 00:09.0 [10b7/9055] enabled PCI: 00:0b.0 [10ec/8139] enabled POST: 0x25 do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 01 POST: 0x24 PCI: 01:00.0 [121a/0005] enabled POST: 0x25 PCI: pci_scan_bus returning with max=001 POST: 0x55 do_pci_scan_bridge returns max 1 scan_static_bus for PCI: 00:07.0 PNP: 03f0.0 enabled PNP: 03f0.1 enabled PNP: 03f0.2 enabled PNP: 03f0.3 enabled PNP: 03f0.4 enabled PNP: 03f0.5 enabled PNP: 03f0.6 enabled PNP: 03f0.7 enabled scan_static_bus for PCI: 00:07.0 done scan_static_bus for PCI: 00:07.3 scan_static_bus for PCI: 00:07.3 done PCI: pci_scan_bus returning with max=001 POST: 0x55 scan_static_bus for Root Device done done POST: 0x66 found VGA at PCI: 01:00.0 Setting up VGA for PCI: 01:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:07.0 read_resources bus 0 link: 0 PNP: 03f0.0 missing read_resources PNP: 03f0.3 missing read_resources PNP: 03f0.4 missing read_resources PNP: 03f0.6 missing read_resources PNP: 03f0.7 missing read_resources PCI: 00:07.0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffff flags 200 index 10 PCI: 01:00.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffff flags 1200 index 14 PCI: 01:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 18 PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:07.0 child on link 0 PNP: 03f0.0 PCI: 00:07.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:07.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2 PNP: 03f0.0 PNP: 03f0.0 resource base 3f0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 03f0.0 resource base 6 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.0 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 03f0.1 PNP: 03f0.1 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 03f0.1 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.2 PNP: 03f0.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 03f0.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 03f0.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 PNP: 03f0.3 PNP: 03f0.3 resource base 378 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 03f0.3 resource base 7 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.4 PNP: 03f0.5 PNP: 03f0.5 resource base 60 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 03f0.5 resource base 64 size 8 align 3 gran 3 limit 7ff flags c0000100 index 62 PNP: 03f0.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.6 PNP: 03f0.6 resource base c size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.7 PCI: 00:07.1 PCI: 00:07.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:07.2 PCI: 00:07.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:07.3 PCI: 00:07.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1 PCI: 00:07.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2 PCI: 00:09.0 PCI: 00:09.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 10 PCI: 00:09.0 resource base 0 size 80 align 7 gran 7 limit ffffffff flags 200 index 14 PCI: 00:09.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30 PCI: 00:0b.0 PCI: 00:0b.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 00:0b.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 14 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 01:00.0 18 * [0x0 - 0xff] io PCI: 00:01.0 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:01.0 1c * [0x0 - 0xfff] io PCI: 00:0b.0 10 * [0x1000 - 0x10ff] io PCI: 00:09.0 10 * [0x1400 - 0x147f] io PCI: 00:07.2 20 * [0x1480 - 0x149f] io PCI: 00:07.1 20 * [0x14a0 - 0x14af] io PCI_DOMAIN: 0000 compute_resources_io: base: 14b0 size: 14b0 align: 12 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 14 * [0x0 - 0x1ffffff] prefmem PCI: 00:01.0 compute_resources_prefmem: base: 2000000 size: 2000000 align: 25 gran: 20 limit: ffffffff done PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 10 * [0x0 - 0x1ffffff] mem PCI: 01:00.0 30 * [0x2000000 - 0x200ffff] mem PCI: 00:01.0 compute_resources_mem: base: 2010000 size: 2100000 align: 25 gran: 20 limit: ffffffff done PCI: 00:00.0 10 * [0x0 - 0xfffffff] prefmem PCI: 00:01.0 20 * [0x10000000 - 0x120fffff] mem PCI: 00:01.0 24 * [0x14000000 - 0x15ffffff] prefmem PCI: 00:09.0 30 * [0x16000000 - 0x1601ffff] mem PCI: 00:0b.0 14 * [0x16020000 - 0x160200ff] mem PCI: 00:09.0 14 * [0x16020100 - 0x1602017f] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 16020180 size: 16020180 align: 28 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 01:00.0 constrain_resources: PCI: 00:07.0 constrain_resources: PNP: 03f0.0 skipping PNP: 03f0.0@60 fixed resource, size=0! skipping PNP: 03f0.0@70 fixed resource, size=0! skipping PNP: 03f0.0@74 fixed resource, size=0! constrain_resources: PNP: 03f0.1 constrain_resources: PNP: 03f0.2 constrain_resources: PNP: 03f0.3 skipping PNP: 03f0.3@60 fixed resource, size=0! skipping PNP: 03f0.3@70 fixed resource, size=0! constrain_resources: PNP: 03f0.4 constrain_resources: PNP: 03f0.5 constrain_resources: PNP: 03f0.6 skipping PNP: 03f0.6@70 fixed resource, size=0! constrain_resources: PNP: 03f0.7 constrain_resources: PCI: 00:07.1 constrain_resources: PCI: 00:07.2 constrain_resources: PCI: 00:07.3 constrain_resources: PCI: 00:09.0 constrain_resources: PCI: 00:0b.0 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000e3ff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit ff7fffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:14b0 align:12 gran:0 limit:e3ff Assigned: PCI: 00:01.0 1c * [0x1000 - 0x1fff] io Assigned: PCI: 00:0b.0 10 * [0x2000 - 0x20ff] io Assigned: PCI: 00:09.0 10 * [0x2400 - 0x247f] io Assigned: PCI: 00:07.2 20 * [0x2480 - 0x249f] io Assigned: PCI: 00:07.1 20 * [0x24a0 - 0x24af] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 24b0 size: 14b0 align: 12 gran: 0 done PCI: 00:01.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:e3ff Assigned: PCI: 01:00.0 18 * [0x1000 - 0x10ff] io PCI: 00:01.0 allocate_resources_io: next_base: 1100 size: 1000 align: 12 gran: 12 done PCI_DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:16020180 align:28 gran:0 limit:ff7fffff Assigned: PCI: 00:00.0 10 * [0xe0000000 - 0xefffffff] prefmem Assigned: PCI: 00:01.0 20 * [0xf0000000 - 0xf20fffff] mem Assigned: PCI: 00:01.0 24 * [0xf4000000 - 0xf5ffffff] prefmem Assigned: PCI: 00:09.0 30 * [0xf6000000 - 0xf601ffff] mem Assigned: PCI: 00:0b.0 14 * [0xf6020000 - 0xf60200ff] mem Assigned: PCI: 00:09.0 14 * [0xf6020100 - 0xf602017f] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f6020180 size: 16020180 align: 28 gran: 0 done PCI: 00:01.0 allocate_resources_prefmem: base:f4000000 size:2000000 align:25 gran:20 limit:ff7fffff Assigned: PCI: 01:00.0 14 * [0xf4000000 - 0xf5ffffff] prefmem PCI: 00:01.0 allocate_resources_prefmem: next_base: f6000000 size: 2000000 align: 25 gran: 20 done PCI: 00:01.0 allocate_resources_mem: base:f0000000 size:2100000 align:25 gran:20 limit:ff7fffff Assigned: PCI: 01:00.0 10 * [0xf0000000 - 0xf1ffffff] mem Assigned: PCI: 01:00.0 30 * [0xf2000000 - 0xf200ffff] mem PCI: 00:01.0 allocate_resources_mem: next_base: f2010000 size: 2100000 align: 25 gran: 20 done Root Device assign_resources, bus 0 link: 0 Setting RAM size to 384 MB PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:00.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem PCI: 00:01.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io PCI: 00:01.0 24 <- [0x00f4000000 - 0x00f5ffffff] size 0x02000000 gran 0x14 bus 01 prefmem PCI: 00:01.0 20 <- [0x00f0000000 - 0x00f20fffff] size 0x02100000 gran 0x14 bus 01 mem PCI: 00:01.0 assign_resources, bus 1 link: 0 PCI: 01:00.0 10 <- [0x00f0000000 - 0x00f1ffffff] size 0x02000000 gran 0x19 mem PCI: 01:00.0 14 <- [0x00f4000000 - 0x00f5ffffff] size 0x02000000 gran 0x19 prefmem PCI: 01:00.0 18 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 01:00.0 30 <- [0x00f2000000 - 0x00f200ffff] size 0x00010000 gran 0x10 romem PCI: 00:01.0 assign_resources, bus 1 link: 0 PCI: 00:07.0 assign_resources, bus 0 link: 0 PNP: 03f0.0 missing set_resources PNP: 03f0.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 03f0.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 03f0.2 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io PNP: 03f0.2 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq ERROR: PNP: 03f0.2 74 drq size: 0x0000000001 not assigned ERROR: PNP: 03f0.2 75 drq size: 0x0000000001 not assigned PNP: 03f0.3 missing set_resources PNP: 03f0.5 60 <- [0x0000000060 - 0x0000000067] size 0x00000008 gran 0x03 io PNP: 03f0.5 62 <- [0x0000000064 - 0x000000006b] size 0x00000008 gran 0x03 io PNP: 03f0.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq PNP: 03f0.6 missing set_resources PCI: 00:07.0 assign_resources, bus 0 link: 0 PCI: 00:07.1 20 <- [0x00000024a0 - 0x00000024af] size 0x00000010 gran 0x04 io PCI: 00:07.2 20 <- [0x0000002480 - 0x000000249f] size 0x00000020 gran 0x05 io PCI: 00:09.0 10 <- [0x0000002400 - 0x000000247f] size 0x00000080 gran 0x07 io PCI: 00:09.0 14 <- [0x00f6020100 - 0x00f602017f] size 0x00000080 gran 0x07 mem PCI: 00:09.0 30 <- [0x00f6000000 - 0x00f601ffff] size 0x00020000 gran 0x11 romem PCI: 00:0b.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io PCI: 00:0b.0 14 <- [0x00f6020000 - 0x00f60200ff] size 0x00000100 gran 0x08 mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 1000 size 14b0 align 12 gran 0 limit e3ff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base e0000000 size 16020180 align 28 gran 0 limit ff7fffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a PCI_DOMAIN: 0000 resource base c0000 size 17f40000 align 0 gran 0 limit 0 flags e0004200 index b PCI: 00:00.0 PCI: 00:00.0 resource base e0000000 size 10000000 align 28 gran 28 limit ff7fffff flags 60001200 index 10 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 00:01.0 resource base 1000 size 1000 align 12 gran 12 limit e3ff flags 60080102 index 1c PCI: 00:01.0 resource base f4000000 size 2000000 align 25 gran 20 limit ff7fffff flags 60081202 index 24 PCI: 00:01.0 resource base f0000000 size 2100000 align 25 gran 20 limit ff7fffff flags 60080202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base f0000000 size 2000000 align 25 gran 25 limit ff7fffff flags 60000200 index 10 PCI: 01:00.0 resource base f4000000 size 2000000 align 25 gran 25 limit ff7fffff flags 60001200 index 14 PCI: 01:00.0 resource base 1000 size 100 align 8 gran 8 limit e3ff flags 60000100 index 18 PCI: 01:00.0 resource base f2000000 size 10000 align 16 gran 16 limit ff7fffff flags 60002200 index 30 PCI: 00:07.0 child on link 0 PNP: 03f0.0 PCI: 00:07.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:07.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2 PNP: 03f0.0 PNP: 03f0.0 resource base 3f0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 03f0.0 resource base 6 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.0 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 03f0.1 PNP: 03f0.1 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 03f0.1 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.2 PNP: 03f0.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 03f0.2 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 03f0.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 PNP: 03f0.3 PNP: 03f0.3 resource base 378 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 03f0.3 resource base 7 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.4 PNP: 03f0.5 PNP: 03f0.5 resource base 60 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 03f0.5 resource base 64 size 8 align 3 gran 3 limit 7ff flags e0000100 index 62 PNP: 03f0.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.6 PNP: 03f0.6 resource base c size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.7 PCI: 00:07.1 PCI: 00:07.1 resource base 24a0 size 10 align 4 gran 4 limit e3ff flags 60000100 index 20 PCI: 00:07.2 PCI: 00:07.2 resource base 2480 size 20 align 5 gran 5 limit e3ff flags 60000100 index 20 PCI: 00:07.3 PCI: 00:07.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1 PCI: 00:07.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2 PCI: 00:09.0 PCI: 00:09.0 resource base 2400 size 80 align 7 gran 7 limit e3ff flags 60000100 index 10 PCI: 00:09.0 resource base f6020100 size 80 align 7 gran 7 limit ff7fffff flags 60000200 index 14 PCI: 00:09.0 resource base f6000000 size 20000 align 17 gran 17 limit ff7fffff flags 60002200 index 30 PCI: 00:0b.0 PCI: 00:0b.0 resource base 2000 size 100 align 8 gran 8 limit e3ff flags 60000100 index 10 PCI: 00:0b.0 resource base f6020000 size 100 align 8 gran 8 limit ff7fffff flags 60000200 index 14 Done allocating resources. POST: 0x88 Enabling resources... PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 008b PCI: 00:01.0 cmd <- 07 PCI: 00:07.0 cmd <- 07 PCI: 00:07.1 cmd <- 01 PCI: 00:07.2 cmd <- 01 PCI: 00:07.3 cmd <- 01 PCI: 00:09.0 cmd <- 03 PCI: 00:0b.0 cmd <- 03 PCI: 01:00.0 cmd <- 03 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init Initializing CPU #0 CPU: vendor Intel device 652 CPU: family 06, model 05, stepping 02 microcode: sig=0x652 pf=0x1 revision=0x0 Microcode has no valid size field! Microcode has no valid size field! Microcode has no valid size field! Microcode has no valid size field! microcode: updated to revision 0x2a date=1999-05-12 Configuring L2 cache... rdmsr(IA32_PLATFORM_ID) = 400122c8:b404f945 L2 latency type = 0 Could not find key 3100 in latency table done. POST: 0x60 Enabling cache
Setting fixed MTRRs(0-88) Type: UC Setting fixed MTRRs(0-16) Type: WB Setting fixed MTRRs(24-88) Type: WB DONE fixed MTRRs call enable_fixed_mtrr() CPU physical address size: 36 bits Setting variable MTRR 0, base: 0MB, range: 256MB, type WB Setting variable MTRR 1, base: 256MB, range: 128MB, type WB Zero-sized MTRR range @0KB DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a
MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled
POST: 0x93 Disabling local apic...done. POST: 0x9b CPU #0 initialized PCI: 00:00.0 init Northbridge Init PCI: 00:07.0 init RTC Init PCI: 00:07.1 init IDE: Primary IDE interface: on IDE: Secondary IDE interface: on IDE: Access to legacy IDE ports: on IDE: Primary IDE interface, drive 0: UDMA/33: on IDE: Primary IDE interface, drive 1: UDMA/33: on IDE: Secondary IDE interface, drive 0: UDMA/33: on IDE: Secondary IDE interface, drive 1: UDMA/33: on PCI: 00:07.2 init PCI: 00:09.0 init CBFS: Looking for 'pci10b7,9055.rom' CBFS: Could not find file 'pci10b7,9055.rom'. Option ROM address for PCI: 00:09.0 = f6000000 PCI expansion ROM, signature 0x4b25, INIT size 0x5a00, data ptr 0x6769 Incorrect expansion ROM header signature 4b25 PCI: 00:0b.0 init CBFS: Looking for 'pci10ec,8139.rom' CBFS: Could not find file 'pci10ec,8139.rom'. PCI: 01:00.0 init CBFS: Looking for 'pci121a,0005.rom' CBFS: Could not find file 'pci121a,0005.rom'. Option ROM address for PCI: 01:00.0 = f2000000 PCI expansion ROM, signature 0xaa55, INIT size 0x8000, data ptr 0x7da4 PCI ROM image, vendor ID 121a, device ID 0005, PCI ROM image, Class Code 030000, Code Type 00 Copying VGA ROM Image from f2000000 to 0xc0000, 0x8000 bytes Real mode stub @00000600: 867 bytes Calling Option ROM... 0xb102: return 0x100 0xb102: return 0x100 0xb102: return 0x100 0xb102: return 0x100 ... Option ROM returned. Getting information about VESA mode 4117 framebuffer: 00000000 Setting VESA mode 4117 0xb102: return 0x100 PNP: 03f0.1 init PNP: 03f0.2 init PNP: 03f0.5 init Devices initialized Show all devs...After init. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:07.0: enabled 1 PNP: 03f0.0: enabled 1 PNP: 03f0.1: enabled 1 PNP: 03f0.2: enabled 1 PNP: 03f0.3: enabled 1 PNP: 03f0.4: enabled 1 PNP: 03f0.5: enabled 1 PNP: 03f0.6: enabled 1 PNP: 03f0.7: enabled 1 PCI: 00:07.1: enabled 1 PCI: 00:07.2: enabled 1 PCI: 00:07.3: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:0b.0: enabled 1 PCI: 01:00.0: enabled 1 CPU: 00: enabled 1 POST: 0x89 Re-Initializing CBMEM area to 0x17fe0000 Initializing CBMEM area to 0x17fe0000 (131072 bytes) Adding CBMEM entry as no. 1 Moving GDT to 17fe0200...ok High Tables Base is 17fe0000. POST: 0x9a Copying Interrupt Routing Table to 0x000f0000... done. Adding CBMEM entry as no. 2 Copying Interrupt Routing Table to 0x17fe0400... done. PIRQ table: 144 bytes. Adding CBMEM entry as no. 3 smbios_write_tables: 17fe1400 Root Device (GIGABYTE GA-6BXE Mainboard) APIC_CLUSTER: 0 (Intel 82443BX (440BX) Northbridge) APIC: 00 (Slot 1 CPU) PCI_DOMAIN: 0000 (Intel 82443BX (440BX) Northbridge) PCI: 00:00.0 (Intel 82443BX (440BX) Northbridge) PCI: 00:01.0 (Intel 82443BX (440BX) Northbridge) PCI: 00:07.0 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge) PNP: 03f0.0 (ITE IT8671F Super I/O) PNP: 03f0.1 (ITE IT8671F Super I/O) PNP: 03f0.2 (ITE IT8671F Super I/O) PNP: 03f0.3 (ITE IT8671F Super I/O) PNP: 03f0.4 (ITE IT8671F Super I/O) PNP: 03f0.5 (ITE IT8671F Super I/O) PNP: 03f0.6 (ITE IT8671F Super I/O) PNP: 03f0.7 (ITE IT8671F Super I/O) PCI: 00:07.1 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge) PCI: 00:07.2 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge) PCI: 00:07.3 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge) PCI: 00:09.0 () PCI: 00:0b.0 () PCI: 01:00.0 () CPU: 00 () SMBIOS tables: 258 bytes. POST: 0x9d Adding CBMEM entry as no. 4 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum cbe0 New low_table_end: 0x00000528 Now going to write high coreboot table at 0x17fe1c00 rom_table_end = 0x17fe1c00 Adjust low_table_end from 0x00000528 to 0x00001000 Adjust rom_table_end from 0x17fe1c00 to 0x17ff0000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-0000000017fdffff: RAM 3. 0000000017fe0000-0000000017ffffff: CONFIGURATION TABLES 4. 00000000ff800000-00000000ffffffff: RESERVED Wrote coreboot table at: 17fe1c00, 0x1c8 bytes, checksum 8c34 coreboot table: 480 bytes. POST: 0x9e POST: 0x9d Multiboot Information structure has been written. 0. FREE SPACE 17fe9c00 00016400 1. GDT 17fe0200 00000200 2. IRQ TABLE 17fe0400 00001000 3. SMBIOS 17fe1400 00000800 4. COREBOOT 17fe1c00 00008000 CBFS: Looking for 'fallback/payload' CBFS: found. Got a payload CPU0: stack from 00138000 to 00140000:Lowest stack address 0013faa8 Loading segment from rom address 0xfffdd378 code (compression=1) New segment dstaddr 0xe7990 memsize 0x18670 srcaddr 0xfffdd3b0 filesize 0xc49c (cleaned up) New segment addr 0xe7990 size 0x18670 offset 0xfffdd3b0 filesize 0xc49c Loading segment from rom address 0xfffdd394 Entry Point 0x00000000 Loading Segment: addr: 0x00000000000e7990 memsz: 0x0000000000018670 filesz: 0x000000000000c49c lb: [0x0000000000100000, 0x0000000000144000) Post relocation: addr: 0x00000000000e7990 memsz: 0x0000000000018670 filesz: 0x000000000000c49c using LZMA [ 0x000e7990, 00100000, 0x00100000) <- fffdd3b0 dest 000e7990, end 00100000, bouncebuffer 17f58000 Loaded segments 0xb102: return 0x100 Jumping to boot code at fc7e0 POST: 0xf8 entry = 0x000fc7e0 lb_start = 0x00100000 lb_size = 0x00044000 adjust = 0x17e9c000 buffer = 0x17f58000 elf_boot_notes = 0x00132964 adjusted_boot_notes = 0x17fce964 Start bios (version rel-1.7.1-0-g51755c3-20121027_100503-ibm-x31) Found mainboard GIGABYTE GA-6BXE Ram Size=0x17fe0000 (0x0000000000000000 high) Relocating low data from 0x000e81d0 to 0x000ef790 (size 2153) Relocating init from 0x000e8a39 to 0x17fc68e0 (size 38387) Found CBFS header at 0xfffffc90 CPU Mhz=450 Found 9 PCI devices (max PCI bus is 01) No apic - only the main cpu is present. Copying PIR from 0x17fe0400 to 0x000fdb60 Copying SMBIOS entry point from 0x17fe1400 to 0x000fdb40 Scan for VGA option rom Running option rom at c000:0003 Turning on vga text mode console SeaBIOS (version rel-1.7.1-0-g51755c3-20121027_100503-ibm-x31)
UHCI init on dev 00:07.2 (io=2480) Found 0 lpt ports Found 2 serial ports ATA controller 1 at 1f0/3f4/0 (irq 14 dev 39) ATA controller 2 at 170/374/0 (irq 15 dev 39) PS2 keyboard initialized All threads complete. Scan for option roms Press F12 for boot menu.
Space available for UMB: 000c8000-000ef000 Returned 65536 bytes of ZoneHigh e820 map has 6 items: 0: 0000000000000000 - 000000000009fc00 = 1 RAM 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 0000000017fe0000 = 1 RAM 4: 0000000017fe0000 - 0000000018000000 = 2 RESERVED 5: 00000000ff800000 - 0000000100000000 = 2 RESERVED enter handle_19: NULL Booting from Floppy... Boot failed: could not read the boot disk
enter handle_18: NULL Booting from Hard Disk... Boot failed: could not read the boot disk
enter handle_18: NULL No bootable device. Retrying in 60 seconds.
2012/10/28, Kevin O'Connor kevin@koconnor.net:
On Sat, Oct 27, 2012 at 02:48:34PM +0300, Eino-Pekka Kanto wrote:
Hello!
I burned coreboot to my Gigabyte 6bxe rev 1.9 motherboard, using SeaBIOS as payload. Floppy drive didn't work (marked as WIP), but otherwise it did support Voodoo 3dfx in AGP. 120Gb WD1200 drive also worked, but Toshiba XM-6402B drive didn't. I tested it with Lubuntu 8.04 CD-R (tested with that same drive in vendor BIOS and it worked). The drive opens and closes but SeaBIOS doesn't boot it.
SeaBIOS config: http://dpaste.com/818910/ Coreboot config: http://dpaste.com/818909/
Coreboot and SeaBIOS logs from serial port (without any drives):
[...]
No bootable device. Retrying in 60 seconds.
Ps. will there be floppy support soon for this motherboard?
Are you trying to boot from a floppy drive? It's not clear from your report.
SeaBIOS doesn't enable floppies on coreboot, because it has never been tested on real hardware. If you want to give it a test you could try applying this patch to the SeaBIOS code:
--- a/src/floppy.c +++ b/src/floppy.c @@ -136,7 +136,7 @@ floppy_setup(void) dprintf(3, "init floppy drives\n");
if (CONFIG_COREBOOT) {
// XXX - disable floppies on coreboot for now.
addFloppy(0, 4);I really have no idea if it will work on real hardware. It certainly wont work with anything other than a 1.44Mbit 3.5" drive.
-Kevin
-
Eino-Pekka Kanto -
Kevin O'Connor