Hi,
I've been trying to boot my epia-m9000 with coreboot-v2 (rev 3348) and filo-0.5 (rev 48).
I can not get the normal Linux VGA text console to work. I also don't see any VGA output from filo, nor via int 0x10 calls if I use "legacybios" as a payload. The monitor attached seems to think there is no signal present at all.
Interestingly, the machine boots into the OS with no problems. The hard drive has Fedora Core 9 installed on it. I instructed filo to use the FC9 grub file (MENULST_FILE = "hda1:/grub/grub.conf"). I was very impressed at how filo was able to boot the system seamlessly once it was given the grub config file.
Ironically, I can even start the X server, and get vga output with it. However, I still don't get VGA text output if I switch between the X server and a text console.
Here is what I did to get to this point.
* Use coreboot-v2 (rev 3348)
* Obtain the VGA option rom pci1106,3122.rom from: http://www.coreboot.org/viewvc/trunk/optionroms/?root=optionroms
* Change targets/via/epia-m/Config.lb to only have a single "fallback" image, and make enough room in the rom for the VGA bios. Specifically I changed lines to:
option ROM_SIZE=256*1024 - 57344 option FALLBACK_SIZE=ROM_SIZE
buildrom ./coreboot.rom ROM_SIZE "fallback"
* After every build, prepend the vga bios to the coreboot.rom to make the full 256KiB rom:
cat pci1106,3122.rom coreboot.rom > coreboot.final.rom
Again, the X server works, but I don't get normal bootup VGA text output. I've tried many different combinations with the vga bios without luck (using dd to extract vga bios, padding OptionsRom bios to 64K, adding explicit pci entry to mainboard Config.lb).
It's clear that the vga bios is running - the logs show lots of interaction with int15.
Any ideas?
-Kevin
================================================ 0
coreboot-2.0.0.0-Fallback Mon May 26 11:32:41 EDT 2008 starting... Enabling mainboard devices Enabling shadow ram vt8623 init starting Detecting Memory Number of Banks 04 Number of Rows 0d Priamry DRAM width08 No Columns 0a MA type e0 Bank 0 (*16 Mb) 10 No Physical Banks 01 Total Memory (*16 Mb) 10 CAS Supported 2 2.5 Cycle time at CL X (nS)60 Cycle time at CL X-0.5 (nS)75 Cycle time at CL X-1 (nS)00 Starting at CAS 2.5 We can do CAS 2 tRP 48 tRCD 48 tRAS 2a Low Bond 00 High Bond98 Setting DQS delay65vt8623 done 00:06 11 23 31 06 00 30 22 00 00 00 06 00 00 00 00 10:08 00 00 d0 00 00 00 00 00 00 00 00 00 00 00 00 20:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30:00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40:00 18 88 80 82 44 00 00 18 99 88 80 82 44 00 00 50:c8 de cf 88 e0 07 00 00 e0 00 10 10 10 10 00 00 60:02 ff 00 30 d6 32 01 34 42 2d 43 58 00 44 00 00 70:82 48 00 01 01 08 50 00 01 00 00 00 00 00 00 00 80:0f 65 00 00 80 00 00 00 02 00 00 00 00 00 00 00 90:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0:02 c0 20 00 07 02 00 1f 04 00 00 00 2f 02 04 00 b0:00 00 00 00 c0 00 00 00 aa 00 00 00 00 00 00 00 c0:01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0:00 dd 00 00 00 00 01 00 40 00 00 00 00 00 00 00 f0:00 00 00 00 00 00 03 13 00 00 00 00 00 00 00 00 AGP Doing MTRR init. Copying coreboot to RAM. Jumping to coreboot. coreboot-2.0.0.0-Fallback Mon May 26 11:32:41 EDT 2008 booting... clocks_per_usec: 1579 Enumerating buses... APIC_CLUSTER: 0 enabled Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [1106/3123] enabled PCI: 00:01.0 [1106/b091] enabled Disabling static device: PCI: 00:0a.0 Disabling static device: PCI: 00:0a.1 PCI: 00:0d.0 [1106/3044] enabled In vt8235_enable 1106 3038. PCI: 00:10.0 [1106/3038] enabled In vt8235_enable 1106 3038. PCI: 00:10.1 [1106/3038] enabled In vt8235_enable 1106 3038. PCI: 00:10.2 [1106/3038] enabled In vt8235_enable ffff ffff. Disabling static device: PCI: 00:10.3 In vt8235_enable 1106 3177. Initialising Devices Keyboard init... PCI: 00:11.0 [1106/3177] enabled In vt8235_enable 1106 0571. PCI: 00:11.1 [1106/0571] enabled In vt8235_enable 1106 3059. PCI: 00:11.5 [1106/3059] enabled In vt8235_enable 1106 3068. PCI: 00:11.6 [1106/3068] disabled In vt8235_enable 1106 3065. PCI: 00:12.0 [1106/3065] enabled PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [1106/3122] enabled PCI: pci_scan_bus returning with max=001 vt1211 enabling PNP devices. PNP: 002e.0 enabled vt1211 enabling PNP devices. PNP: 002e.1 enabled vt1211 enabling PNP devices. PNP: 002e.2 enabled vt1211 enabling PNP devices. PNP: 002e.3 enabled vt1211 enabling PNP devices. PNP: 002e.b enabled PCI: pci_scan_bus returning with max=001 done Allocating resources... Reading resources... Done reading resources. Setting resources... I would set ram size to 0x40000 Kbytes PCI: 00:0d.0 10 <- [0x00febfe000 - 0x00febfe7ff] size 0x00000800 gran 0x0b mem PCI: 00:0d.0 14 <- [0x0000001800 - 0x000000187f] size 0x00000080 gran 0x07 io PCI: 00:10.0 20 <- [0x0000001880 - 0x000000189f] size 0x00000020 gran 0x05 io PCI: 00:10.1 20 <- [0x00000018a0 - 0x00000018bf] size 0x00000020 gran 0x05 io PCI: 00:10.2 20 <- [0x00000018c0 - 0x00000018df] size 0x00000020 gran 0x05 io PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq PNP: 002e.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq PNP: 002e.1 74 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 drq PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq PNP: 002e.b 60 <- [0x000000ec00 - 0x000000ecff] size 0x00000100 gran 0x08 io PCI: 00:11.1 20 <- [0x00000018e0 - 0x00000018ef] size 0x00000010 gran 0x04 io PCI: 00:11.5 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:12.0 10 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io PCI: 00:12.0 14 <- [0x00febff000 - 0x00febff0ff] size 0x00000100 gran 0x08 mem Done setting resources. Done allocating resources. Enabling resources... PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 000f PCI: 00:01.0 cmd <- 07 PCI: 01:00.0 cmd <- 00 PCI: 00:0d.0 cmd <- 83 PCI: 00:10.0 subsystem <- 00/00 PCI: 00:10.0 cmd <- 01 PCI: 00:10.1 subsystem <- 00/00 PCI: 00:10.1 cmd <- 01 PCI: 00:10.2 subsystem <- 00/00 PCI: 00:10.2 cmd <- 01 PCI: 00:11.0 cmd <- 07 PNP: 002e.0 - enabling PNP: 002e.1 - enabling PNP: 002e.2 - enabling PNP: 002e.3 - enabling PNP: 002e.b - enabling PCI: 00:11.1 cmd <- 81 PCI: 00:11.5 subsystem <- 00/00 PCI: 00:11.5 cmd <- 01 PCI: 00:12.0 cmd <- 83 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init Initializing CPU #0 CPU: vendor Centaur device 67a CPU: family 06, model 07, stepping 0a WARNING: Using generic cpu ops Enabling cache
Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB Setting fixed MTRRs(24-88) Type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 128MB, type WB Setting variable MTRR 1, base: 128MB, range: 64MB, type WB Setting variable MTRR 2, base: 192MB, range: 32MB, type WB DONE variable MTRRs Clear out the extra MTRR's
MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled
Disabling local apic...done. CPU #0 Initialized PCI: 00:10.0 init PCI: 00:10.1 init PCI: 00:10.2 init PCI: 00:11.0 init vt8235 init RTC Init Invalid CMOS LB checksum pci_routing_fixup: dev is 00011c34 setting firewire Assigning IRQ 9 to 0:d.0 Readback = 9 setting usb Assigning IRQ 5 to 0:10.0 Readback = 5 Assigning IRQ 9 to 0:10.1 Readback = 9 Assigning IRQ 9 to 0:10.2 Readback = 9 Assigning IRQ 5 to 0:10.3 Readback = 5 setting vt8235 Assigning IRQ 5 to 0:11.1 Readback = 5 Assigning IRQ 9 to 0:11.5 Readback = 9 Assigning IRQ 9 to 0:11.6 Readback = 9 setting ethernet Assigning IRQ 5 to 0:12.0 Readback = 5 setting vga Assigning IRQ 5 to 1:0.0 Readback = 5 setting pci slot setting cardbus slot setting riser slot PNP: 002e.0 init PNP: 002e.1 init PNP: 002e.2 init PNP: 002e.3 init PNP: 002e.b init PCI: 00:11.1 init Enabling VIA IDE. ide_init: enabling compatibility IDE addresses enables in reg 0x42 0x9 enables in reg 0x42 read back as 0x9 enables in reg 0x40 0x8 enables in reg 0x40 read back as 0xb enables in reg 0x9 0x8a enables in reg 0x9 read back as 0x8a command in reg 0x4 0x81 command in reg 0x4 reads back as 0x7 PCI: 00:11.5 init PCI: 00:12.0 init Configuring VIA Rhine LAN PCI: 00:00.0 init VT8623 random fixup ... Frame buffer at d0000000 PCI: 00:01.0 init VT8623 AGP random fixup ... PCI: 00:0d.0 init PCI: 01:00.0 init VGA random fixup ... INSTALL REAL-MODE IDT DO THE VGA BIOS found VGA: vid=1106, did=3122 rom base, size: fffc0000 write_protect_vgabios bus/devfn = 0x100 biosint: INT# 0x15 biosint: eax 0x5f00 ebx 0x1ace4 ecx 0x19f8c edx 0x1ace4 biosint: ebp 0x19f54 esp 0xff2 edi 0xf804 esi 0x1ace4 biosint: ip 0x641c cs 0xc000 flags 0x46 biosint: INT# 0x1a biosint: eax 0xb108 ebx 0x10000 ecx 0x10000 edx 0x103d5 biosint: ebp 0x19f54 esp 0xfcc edi 0xf6 esi 0x1c01b biosint: ip 0x40f0 cs 0xc000 flags 0x46 0xb108: bus 0 devfn 0x0 reg 0xf6 val 0x3 biosint: INT# 0x15 biosint: eax 0x5f02 ebx 0x1ace4 ecx 0x9f01 edx 0x103d5 biosint: ebp 0x19f54 esp 0xfdc edi 0x44 esi 0x1c01b biosint: ip 0x6468 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112 biosint: ebp 0x19f54 esp 0xfa4 edi 0x44 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112 biosint: ebp 0x19f54 esp 0xfa4 edi 0x44 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x401 edx 0x10112 biosint: ebp 0x19f54 esp 0xf92 edi 0x44 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f0f ebx 0x1ace4 ecx 0x9f8c edx 0x103d5 biosint: ebp 0x19f54 esp 0xfee edi 0x44 esi 0x1ace4 biosint: ip 0x651b cs 0xc000 flags 0x7 biosint: INT# 0x15 biosint: eax 0x5f02 ebx 0x1ace4 ecx 0x9f01 edx 0x103d5 biosint: ebp 0x19f54 esp 0xfdc edi 0x44 esi 0x1ace4 biosint: ip 0x6468 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112 biosint: ebp 0x10fca esp 0xf8e edi 0xac51 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112 biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x101 edx 0x10112 biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x78c edx 0x10112 biosint: ebp 0x10fca esp 0xf88 edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112 biosint: ebp 0x10fca esp 0xf7e edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x700 edx 0x10112 biosint: ebp 0x10fca esp 0xf90 edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x701 edx 0x10112 biosint: ebp 0x10fca esp 0xf90 edi 0xb880 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f18 ebx 0x1ace4 ecx 0x9f01 edx 0x103d5 biosint: ebp 0x19f54 esp 0xfde edi 0x44 esi 0x1ace4 biosint: ip 0x6533 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf8c edi 0xac49 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x46 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x101 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x38c edx 0x10112 biosint: ebp 0x10fc8 esp 0xf86 edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf7c edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x300 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf8e edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0xc01 ecx 0x301 edx 0x10112 biosint: ebp 0x10fc8 esp 0xf8e edi 0xb840 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f06 ebx 0x18001 ecx 0x1 edx 0x0 biosint: ebp 0x10fd6 esp 0xfb4 edi 0x0 esi 0x146a7 biosint: ip 0x6479 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x0 edx 0x112 biosint: ebp 0x10fd6 esp 0xf88 edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x0 edx 0x112 biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x101 edx 0x112 biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x1 edx 0x112 biosint: ebp 0x10fd6 esp 0xf82 edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x0 edx 0x112 biosint: ebp 0x10fd6 esp 0xf78 edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x0 edx 0x112 biosint: ebp 0x10fd6 esp 0xf8a edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f01 ebx 0x10c01 ecx 0x1 edx 0x112 biosint: ebp 0x10fd6 esp 0xf8a edi 0x0 esi 0x1aacd biosint: ip 0x6448 cs 0xc000 flags 0x246 biosint: INT# 0x15 biosint: eax 0x5f08 ebx 0x18001 ecx 0x1 edx 0x0 biosint: ebp 0x10fd6 esp 0xfb4 edi 0x0 esi 0x146a7 biosint: ip 0x6485 cs 0xc000 flags 0x202 Devices initialized Copying IRQ routing tables to 0xf0000...done. Verifing copy of IRQ routing tables at 0xf0000...done Checking IRQ routing table consistency... check_pirq_routing_table() - irq_routing_table located at: 0x000f0000 done. ACPI: Writing ACPI tables at f0400... ACPI: * FACS ACPI: * DSDT @ 000f04aa Length 3f0 ACPI: * FADT ACPI: added table 1/8 Length now 40 ACPI: done. Moving GDT to 0x500...ok Adjust low_table_end from 0x00000530 to 0x00001000 Adjust rom_table_end from 0x000f0c00 to 0x00100000 Wrote coreboot table at: 00000530 - 00000c24 checksum 6e6a
Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3
rom_stream: 0xfffce000 - 0xffff0fff Found ELF candidate at offset 0 header_offset is 0 Try to load at offset 0x0 New segment addr 0x100000 size 0x412c0 offset 0xc0 filesize 0x13504 (cleaned up) New segment addr 0x100000 size 0x412c0 offset 0xc0 filesize 0x13504 New segment addr 0x1412c0 size 0x48 offset 0x135c4 filesize 0x48 (cleaned up) New segment addr 0x1412c0 size 0x48 offset 0x135c4 filesize 0x48 Dropping non PT_LOAD segment Dropping non PT_LOAD segment Loading Segment: addr: 0x0000000000100000 memsz: 0x00000000000412c0 filesz: 0x0000000000013504 Clearing Segment: addr: 0x0000000000113504 memsz: 0x000000000002ddbc Loading Segment: addr: 0x00000000001412c0 memsz: 0x0000000000000048 filesz: 0x0000000000000048 Jumping to boot code at 0x10ed28 FILO version 0.5.5 (kevin@morn.localdomain) Sat May 24 17:55:55 EDT 2008 menu: hda1:/grub/grub.conf hda: LBA 8455MB: WDC AC28400R Mounted EXT2 filesystem Found Linux version 2.6.25.3-18.fc9.i586 (mockbuild@) #1 SMP Tue May 13 04:32:36 EDT 2008 bzImage. Loading kernel... ok Loading initrd... ok Jumping to entry point... ================================================
The Epia-CN (C7+cn700+vt8237r) is having the exact same issue even though it is using a more recent VIA chipset. Epia-M9000 (C3 + CLE266 + vt8235). This lack of Console VGA issue was next on the list after I clear up some IRQ issues with the CN.
What are we missing for VIA chipsets with integrated video to bring up Console VGA?
Config.lb in targets/via/epia-cn has:
cat vgabios bochsbios coreboot.rom > coreboot.rom.final option ROM_SIZE=512*1024 - 64*1024 - 64*1024
Yet I get the same results with VGA if BOCHS is not included. BOCHS does not seem to have an effect on X sever and VGA.
cat vgabios coreboot.rom > coreboot.rom.final option ROM_SIZE=512*1024 - 64*1024
-Bari
Kevin O'Connor wrote:
Hi,
I've been trying to boot my epia-m9000 with coreboot-v2 (rev 3348) and filo-0.5 (rev 48).
I can not get the normal Linux VGA text console to work. I also don't see any VGA output from filo, nor via int 0x10 calls if I use "legacybios" as a payload. The monitor attached seems to think there is no signal present at all.
Interestingly, the machine boots into the OS with no problems. The hard drive has Fedora Core 9 installed on it. I instructed filo to use the FC9 grub file (MENULST_FILE = "hda1:/grub/grub.conf"). I was very impressed at how filo was able to boot the system seamlessly once it was given the grub config file.
Ironically, I can even start the X server, and get vga output with it. However, I still don't get VGA text output if I switch between the X server and a text console.
Here is what I did to get to this point.
Use coreboot-v2 (rev 3348)
Obtain the VGA option rom pci1106,3122.rom from: http://www.coreboot.org/viewvc/trunk/optionroms/?root=optionroms
Change targets/via/epia-m/Config.lb to only have a single "fallback" image, and make enough room in the rom for the VGA bios. Specifically I changed lines to:
option ROM_SIZE=256*1024 - 57344 option FALLBACK_SIZE=ROM_SIZE
buildrom ./coreboot.rom ROM_SIZE "fallback"
After every build, prepend the vga bios to the coreboot.rom to make the full 256KiB rom:
cat pci1106,3122.rom coreboot.rom > coreboot.final.rom
Again, the X server works, but I don't get normal bootup VGA text output. I've tried many different combinations with the vga bios without luck (using dd to extract vga bios, padding OptionsRom bios to 64K, adding explicit pci entry to mainboard Config.lb).
It's clear that the vga bios is running - the logs show lots of interaction with int15.
Any ideas?
On Tue, May 27, 2008 at 12:30 AM, bari bari@onelabs.com wrote:
The Epia-CN (C7+cn700+vt8237r) is having the exact same issue even though it is using a more recent VIA chipset. Epia-M9000 (C3 + CLE266 + vt8235). This lack of Console VGA issue was next on the list after I clear up some IRQ issues with the CN.
What are we missing for VIA chipsets with integrated video to bring up Console VGA?
I have no problem to bring up vga console, I remembered your last mail mentioned once you load vgabios and bochs bios you'll get vga work but have problem with usb, I admit that's a problem that the vga card's irq get misassigned.
Config.lb in targets/via/epia-cn has:
cat vgabios bochsbios coreboot.rom > coreboot.rom.final option ROM_SIZE=512*1024 - 64*1024 - 64*1024
Yet I get the same results with VGA if BOCHS is not included. BOCHS does not seem to have an effect on X sever and VGA.
If you do not include bochs, vgabios should bail out ;-)
cat vgabios coreboot.rom > coreboot.rom.final option ROM_SIZE=512*1024 - 64*1024
-Bari
I think epia-m is kind of different, I remember when I first learned linuxbios, I'm trying to boot the epia-m then and I have exactly the same problem. Th solution seems to be first set CONFIG_PCI_ROM_RUN=0 and CONFIG_CONSOLE_VGA=0 in Option.lb and build, then change the values to be 1 and rebuild without deleting the target directory. I cannot find the original post that presented this solution in the mailing list now, sorry.
-Aaron
aaron lwe wrote:
On Tue, May 27, 2008 at 12:30 AM, bari bari@onelabs.com wrote:
The Epia-CN (C7+cn700+vt8237r) is having the exact same issue even though it is using a more recent VIA chipset. Epia-M9000 (C3 + CLE266 + vt8235). This lack of Console VGA issue was next on the list after I clear up some IRQ issues with the CN.
What are we missing for VIA chipsets with integrated video to bring up Console VGA?
I have no problem to bring up vga console, I remembered your last mail mentioned once you load vgabios and bochs bios you'll get vga work but have problem with usb, I admit that's a problem that the vga card's irq get misassigned.
To clarify before when I load coreboot + vgabios I can get X to work, but no console vga.
If I stop X, I lose all video, there is no console vga.
I have not under any condition so far been able to get console vga on the C7 + CN700 + vt8237r.
I tried the patch for vga.c and it did not change the situation for me.
I also noticed that epia-cn coreboot + filo (with no vgabios) the network and usb work fine, with coreboot + filo + vgabios the network and usb don't work, no interrupts for usb or network, but X works fine up to 1024x768 16b, at 1280x1024 16b the screen gets very noisy with vertical jitter and ghosting.
I will try the vga.c patch with FILO + vgabios later and see if things change.
coreboot + FILO without VGABIOS:
ln@ln:~$ cat /proc/interrupts CPU0 0: 2743789 XT-PIC-XT timer 1: 12 XT-PIC-XT i8042 2: 0 XT-PIC-XT cascade 5: 24760 XT-PIC-XT uhci_hcd:usb1, uhci_hcd:usb2, eth1 8: 3 XT-PIC-XT rtc 10: 0 XT-PIC-XT VIA8237 11: 21918 XT-PIC-XT uhci_hcd:usb3, uhci_hcd:usb4 12: 1557 XT-PIC-XT i8042 14: 4004 XT-PIC-XT ide0
Everthing works!
using LAB or VGABIOS on CN a few seconds after boot;
cat /proc/interrupts 0: 789 XT-PIC-XT timer 1: 12 XT-PIC-XT i8042 2: 0 XT-PIC-XT cascade 5: 100000 XT-PIC-XT uhci_hcd:usb1, uhci_hcd:usb2 8: 3 XT-PIC-XT rtc 11: 100000 XT-PIC-XT uhci_hcd:usb3, uhci_hcd:usb4 12: 17 XT-PIC-XT i8042 14: 11 XT-PIC-XT ide0
No network, no USB.
The debug output will show the irq's 5 and 10 being set for usb and then disabled.
Debug output: http://pastebin.ca/1029293
Looks like the interrupt handlers are not being set.
Plugging in a usb drive gives this output:
usb 2-1: device descriptor read/64, error -71 usb 2-1: device descriptor read/64, error -71
-Bari
aaron lwe wrote:
Config.lb in targets/via/epia-cn has:
cat vgabios bochsbios coreboot.rom > coreboot.rom.final option ROM_SIZE=512*1024 - 64*1024 - 64*1024
Yet I get the same results with VGA if BOCHS is not included. BOCHS does not seem to have an effect on X sever and VGA.
If you do not include bochs, vgabios should bail out ;-)
With or without BOCHS I have not been able to get Console VGA.
When BOCHS is included or not included, X still works. It looks like X does not need BOCHS.
X does not work without the vgabios included.
I have not yet tried the unichrome drivers that appear to not need vgabios at all.
http://unichrome.sourceforge.net/
-Bari
To clarify before when I load coreboot + vgabios I can get X to work, but no console vga.
sorry I misunderstand you. well, I did get vga console work but X work rather worse, at most 640x480 resolution...
With or without BOCHS I have not been able to get Console VGA. When BOCHS is included or not included, X still works. It looks like X does not need BOCHS.
That's right, bochs bios has nothing to do with X, the sole purpose of bochs bios is to run vgabios, after vgabios finished, bochs bios is cleared, linux never see bochs bios, see vga.c for detail.
-Aaron
aaron lwe wrote:
To clarify before when I load coreboot + vgabios I can get X to work, but no console vga.
sorry I misunderstand you. well, I did get vga console work but X work rather worse, at most 640x480 resolution...
OK, so it looks like it is down to just irq issues.
Thanks!
-Bari
Hi,
On Mon, May 26, 2008 at 11:55:56AM -0400, Kevin O'Connor wrote:
Hi,
I've been trying to boot my epia-m9000 with coreboot-v2 (rev 3348) and filo-0.5 (rev 48).
I can not get the normal Linux VGA text console to work.
I found the issue with epia-m and vga. I am now succesfully booting my epia-m with filo and fc9 - everything seems to work the same as with the factory bios (except coreboot is faster).
The problem is related to the wiki site at:
http://www.coreboot.org/VIA_Epia-M%2C_MII_Build_Tutorial
It has an incorrect command for extracting the vga bios. When I use a correct command - for example:
dd if=/dev/mem of=video.bios.bin.4 bs=65536 count=1 skip=12
Then the extracted vga bios boots fine and enables vga console.
-Kevin
Kevin O'Connor wrote:
I found the issue with epia-m and vga. I am now succesfully booting my epia-m with filo and fc9 - everything seems to work the same as with the factory bios (except coreboot is faster).
The problem is related to the wiki site at:
http://www.coreboot.org/VIA_Epia-M%2C_MII_Build_Tutorial
It has an incorrect command for extracting the vga bios. When I use a correct command - for example:
dd if=/dev/mem of=video.bios.bin.4 bs=65536 count=1 skip=12
Then the extracted vga bios boots fine and enables vga console.
Is vga console working for you with just the use of the properly extracted vga BIOS or do you have to use BOCHS as well?
-Bari
Hi Bari,
On Wed, May 28, 2008 at 02:14:12AM -0500, bari wrote:
Kevin O'Connor wrote:
dd if=/dev/mem of=video.bios.bin.4 bs=65536 count=1 skip=12
Then the extracted vga bios boots fine and enables vga console.
Is vga console working for you with just the use of the properly extracted vga BIOS or do you have to use BOCHS as well?
I don't need bochs (nor legacybios) for me to init the vga on my epia-m. It all came up fine with just filo. (The epia-m vgabios.c file implements its own bios emulation handlers.)
-Kevin
-
aaron lwe -
bari -
Kevin O'Connor