New patch to review for coreboot: b76e507 Add support for RAM-less multi-processor init

[Kyösti Mälkki]

Kyösti Mälkki ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/454

-gerrit

commit b76e507f4d76e75df84a25b52b58e23ec029e6b0
Author: Kyösti Mälkki 
Date:   Wed Nov 23 20:59:57 2011 +0200

Add support for RAM-less multi-processor init

For a hyper-threading processor, enabling cache requires that both the
    BSP and AP CPU clear CR0.CD (Cache Disable) bit. For a Cache-As-Ram
    implementation, partial multi-processor initialisation precedes
    raminit and AP CPUs' 16bit entry must be run from ROM.

The AP CPU can only start execute real-mode code at a 4kB aligned
    address below 1MB. The protected mode entry code for AP is identical
    with the BSP code, which is already located at the top of bootblock.

This patch takes the simplest approach and aligns the bootblock
    16 bit entry at highest possible 4kB boundary below 1MB when
    Kconfig option SIPI_VECTOR_IN_ROM is set.

Change-Id: I82e4edbf208c9ba863f51a64e50cd92871c528ef
    Signed-off-by: Kyösti Mälkki 
---
 src/arch/x86/Kconfig                   |    7 +++++++
 src/arch/x86/init/ldscript_failover.lb |   13 ++++++++-----
 2 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index e71d0f3..9e8e82f 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -8,6 +8,13 @@ config AP_IN_SIPI_WAIT
    default n
    depends on ARCH_X86

+# Aligns 16bit entry code in bootblock so that hyper-threading CPUs
+# can boot AP CPUs to enable their shared caches.
+config SIPI_VECTOR_IN_ROM
+	bool
+	default n
+	depends on ARCH_X86
+
 config ROMBASE
    hex
    default 0xffff0000
diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb
index 83e5eb3..6f7d6fa 100644
--- a/src/arch/x86/init/ldscript_failover.lb
+++ b/src/arch/x86/init/ldscript_failover.lb
@@ -29,17 +29,19 @@ MEMORY {
 TARGET(binary)
 SECTIONS
 {
-	/* Align .rom to next 4 byte boundary so no pad byte appears
-	 * between _rom and _start.
+	/* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs
+	 * with Startup IPI message without RAM. Align .rom to next 4 byte
+	 * boundary anyway, so no pad byte appears between _rom and _start.
     */
    .bogus ROMLOC_MIN : {
-		. = ALIGN(4);
-		ROMLOC = .;
+		. = CONFIG_SIPI_VECTOR_IN_ROM ?	ALIGN(4096) : ALIGN(4);
+		ROMLOC = . ;
    } >rom = 0xff

/* This section might be better named .setup */
    .rom ROMLOC : {
    	_rom = .;
+		ap_sipi_vector = .;
    	*(.rom.text);
    	*(.rom.data);
    	*(.rom.data.*);
@@ -51,7 +53,8 @@ SECTIONS
     * may cause the total size of a section to change when the start
     * address gets applied.
     */
-	ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16);
+	ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) -
+		(CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0);

/DISCARD/ : {
    	*(.comment)