This brings us to compiling with warnings, no errors. (!) It does not link of course!
The code needs lots of cleanup and formatting, which I think should wait for another commit. I would like to get this in as it is very close to the v2 code and hence further changes will be more clearly delineated.
Stefan I think I got the mainboard makefile wrong; can you look?
I am going to finish up bringing mcp55 files over but then move to a SimNOW supported mainboard. SimNOW is too useful not to use. Marc or Jordan, what is the *simplest* SimNOW mobo I can use to start testing if I get that far?
thanks
ron
On 10.08.2008 04:36, ron minnich wrote:
This brings us to compiling with warnings, no errors. (!) It does not link of course!
The code needs lots of cleanup and formatting, which I think should wait for another commit. I would like to get this in as it is very close to the v2 code and hence further changes will be more clearly delineated.
Could you repost this patch after your mcp55 patch has been committed? It's a bit tedious to review ever-growing megapatches which have been partially reviewed before. And 2600 lines are beyond what a human can review in a few minutes. (To all those who doubt my statement: If you can do it, you're super-human ;-))
Regards, Carl-Daniel
This patch is for k8north changes.
Includes ht support and other bits.
Compiles (once the next few patches are in)
ron
On 10.08.2008 23:24, ron minnich wrote:
This patch is for k8north changes.
Includes ht support and other bits.
Compiles (once the next few patches are in)
Add new config variables for the k8 north and, in some cases, all SMP platforms.
Add HT support.
Clean up raminit a bit more
Fix Makefile
Signed-off-by: Ronald G. Minnich rminnich@gmail.com
[k8north.diff]
Would you mind reposting the unmerged bits of this patch? Thanks!
Regards, Carl-Daniel
On Sun, Aug 10, 2008 at 4:09 PM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
On 10.08.2008 23:24, ron minnich wrote:
This patch is for k8north changes.
Includes ht support and other bits.
Compiles (once the next few patches are in)
Add new config variables for the k8 north and, in some cases, all SMP platforms.
Add HT support.
Clean up raminit a bit more
Fix Makefile
Signed-off-by: Ronald G. Minnich rminnich@gmail.com
[k8north.diff]
Would you mind reposting the unmerged bits of this patch? Thanks!
here you go
ron
On 11.08.2008 01:15, ron minnich wrote:
On Sun, Aug 10, 2008 at 4:09 PM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
On 10.08.2008 23:24, ron minnich wrote:
This patch is for k8north changes.
Includes ht support and other bits.
Compiles (once the next few patches are in)
Add new config variables for the k8 north and, in some cases, all SMP platforms.
Add HT support.
Clean up raminit a bit more
Fix Makefile
Signed-off-by: Ronald G. Minnich rminnich@gmail.com
[k8north.diff]
Would you mind reposting the unmerged bits of this patch? Thanks!
here you go
Thanks.
Add new config variables for the k8 north and, in some cases, all SMP platforms.
That one (arch/x86/Kconfig) is missing from your patch. Care to post it as an extra patch? I remember that I was unhappy with that one from a first glance.
Add HT support.
Incoherent HT support. Coherent is already committed. I'll review that separately.
Clean up raminit a bit more.
The raminit cleanup is Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net It would be cool if you could address the one comment in the review below.
Fix Makefile
I'm not really happy about it. Can you comment it out instead and add another comment saying "Does not work. Someone please fix the makefile."? With that change, the Makefile workaround is Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Regards, Carl-Daniel
Signed-off-by: Ronald G. Minnich rminnich@gmail.com
Index: northbridge/amd/k8/raminit.c
--- northbridge/amd/k8/raminit.c (revision 730) +++ northbridge/amd/k8/raminit.c (working copy) @@ -41,6 +41,7 @@ #include <device/pci.h> #include <mc146818rtc.h> #include <lib.h> +#include "stage1.h"
#ifndef QRANK_DIMM_SUPPORT #define QRANK_DIMM_SUPPORT 0 @@ -52,19 +53,14 @@
/* now THIS is a kludge but ... it will do for now until we work this out. */
Remove the "kludge" comment. It applied to the pci conf stuff you removed.
-extern const struct pci_bus_operations pci_cf8_conf1; -static void hard_reset(void); +void hard_reset(void);
-#define pci_read_config32(bus, dev, where) pci_cf8_conf1.read32(NULL, bus, dev, where) -#define pci_write_config32(bus, dev, where, what) pci_cf8_conf1.write32(NULL, bus, dev, where, what)
static int controller_present(const struct mem_controller *ctrl) {
return pci_read_config32(0, ctrl->f0, 0) == 0x11001022;
return pci_read_config32(ctrl->f0, 0) == 0x11001022;}
-static void sdram_set_registers(const struct mem_controller *ctrl) +void sdram_set_registers(const struct mem_controller *ctrl) { static struct rmap rm[] = { /* Careful set limit registers before base registers which contain the enables */ @@ -550,8 +546,8 @@ static void hw_enable_ecc(const struct mem_controller *ctrl) { u32 dcl, nbcap, opt = 1;
- nbcap = pci_read_config32(0, ctrl->f3, NORTHBRIDGE_CAP);
- dcl = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_LOW);
- nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
- dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl &= ~DCL_DimmEccEn; if (nbcap & NBCAP_ECC) { dcl |= DCL_DimmEccEn;
@@ -559,14 +555,14 @@ if (get_option(&opt, "ECC_memory") || opt) { dcl &= ~DCL_DimmEccEn; }
- pci_write_config32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
- pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
}
static int is_dual_channel(const struct mem_controller *ctrl) { u32 dcl;
- dcl = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_LOW);
- dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); return dcl & DCL_128BitEn;
}
@@ -578,7 +574,7 @@ */ #warning "FIXME: Implement a better test for Opterons" u32 nbcap;
- nbcap = pci_read_config32(0, ctrl->f3, NORTHBRIDGE_CAP);
- nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); return !!(nbcap & NBCAP_128Bit);
}
@@ -589,7 +585,7 @@ * This function must be called after spd_handle_unbuffered_dimms. */ u32 dcl;
- dcl = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_LOW);
- dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); return !(dcl & DCL_UnBufDimm);
}
@@ -598,14 +594,14 @@ /* Calculate the log base 2 size of a DIMM in bits */ struct dimm_size sz; int value, low;
- sz.side1 = 0;
- /* no memset per now and we might want non-zero values */
- sz.per_rank = 0;
- sz.side1; sz.side2 = 0; sz.rows = 0; sz.col = 0;
-#if QRANK_DIMM_SUPPORT == 1
- sz.bank = 0; sz.rank = 0;
-#endif
- /* Note it might be easier to use byte 31 here, it has the DIMM size as
- a multiple of 4MB. The way we do it now we can size both
- sides of an assymetric dimm.
@@ -721,25 +717,25 @@ base1 &= ~0x001ffffe;
/* Set the appropriate DIMM base address register */
- pci_write_config32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0);
- pci_write_config32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1);
- pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0);
- pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1);
#if QRANK_DIMM_SUPPORT == 1 if(sz.rank == 4) {
pci_write_config32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0);pci_write_config32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0);pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1);#endif
/* Enable the memory clocks for this DIMM */ if (base0) {
dch = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_HIGH);
dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);#if QRANK_DIMM_SUPPORT == 1 if(sz.rank == 4) { dch |= DCH_MEMCLK_EN0 << (index + 2); } #endif
pci_write_config32(0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);}
@@ -755,7 +751,7 @@ u32 map; u32 dch;
- map = pci_read_config32(0, ctrl->f2, DRAM_BANK_ADDR_MAP);
- map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); map &= ~(0xf << (index * 4));
#if QRANK_DIMM_SUPPORT == 1 if(sz.rank == 4) { @@ -784,7 +780,7 @@ } }
- pci_write_config32(0, ctrl->f2, DRAM_BANK_ADDR_MAP, map);
- pci_write_config32(ctrl->f2, DRAM_BANK_ADDR_MAP, map);
}
@@ -831,8 +827,8 @@ limit_reg = 0x44 + index; base_reg = 0x40 + index; for(device = PCI_BDF(0, 0x18, 1); device <= PCI_BDF(0, 0x1f, 1); device += PCI_BDF(0, 1, 0)) {
pci_write_config32(0, device, limit_reg, limit);pci_write_config32(0, device, base_reg, base);
pci_write_config32(device, limit_reg, limit);pci_write_config32(device, base_reg, base);}
@@ -917,7 +913,7 @@ unsigned cs_mode; u32 value;
value = pci_read_config32(0, ctrl->f2, DRAM_CSBASE + (index << 2));
value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));@@ -933,7 +929,7 @@ return 0; }
value = pci_read_config32(0, ctrl->f2, DRAM_BANK_ADDR_MAP);
value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); cs_mode =( value >> ((index>>1)*4)) & 0xf; if(cs_mode == 0 ) continue; if(common_cs_mode == 0) {@@ -986,13 +982,13 @@ for(index = 0; index < 8; index++) { u32 value;
value = pci_read_config32(0, ctrl->f2, DRAM_CSBASE + (index << 2));
value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
pci_write_config32(0, ctrl->f2, DRAM_CSBASE + (index << 2), csbase);pci_write_config32(0, ctrl->f2, DRAM_CSMASK + (index << 2), csmask);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (index << 2), csbase);pci_write_config32(ctrl->f2, DRAM_CSMASK + (index << 2), csmask);@@ -1017,7 +1013,7 @@ candidate = 0; for(index = 0; index < 8; index++) { u32 value;
value = pci_read_config32(0, ctrl->f2, DRAM_CSBASE + (index << 2));
value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2)); /* Is it enabled? */ if (!(value & 1)) {@@ -1059,9 +1055,9 @@ csmask |= 0xfe00; /* For now don't optimize */
/* Write the new base register */
pci_write_config32(0, ctrl->f2, DRAM_CSBASE + (candidate << 2), csbase);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (candidate << 2), csbase);
pci_write_config32(0, ctrl->f2, DRAM_CSMASK + (candidate << 2), csmask);
pci_write_config32(ctrl->f2, DRAM_CSMASK + (candidate << 2), csmask);@@ -1078,10 +1074,10 @@ u32 limit, base; unsigned index; index = node_id << 3;
base = pci_read_config32(0, ctrl->f1, 0x40 + index);
base = pci_read_config32(ctrl->f1, 0x40 + index);
limit = pci_read_config32(0, ctrl->f1, 0x44 + index);
limit = pci_read_config32(ctrl->f1, 0x44 + index); end_k = ((limit + 0x00010000) & 0xffff0000) >> 2;@@ -1112,8 +1108,8 @@ static long disable_dimm(const struct mem_controller *ctrl, unsigned index, long dimm_mask) { printk(BIOS_DEBUG, "disabling dimm 0x%x\n", index);
- pci_write_config32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0);
- pci_write_config32(0, ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0);
- pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0);
- pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0); dimm_mask &= ~(1 << index); return dimm_mask;
} @@ -1149,7 +1145,7 @@ die("Mixed buffered and registered dimms not supported"); }
- dcl = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_LOW);
- dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl &= ~DCL_UnBufDimm; if (unbuffered) { if ((has_dualch) && (!is_cpu_pre_d0())) {
@@ -1165,7 +1161,7 @@ dcl |= DCL_UnBufDimm; } }
- pci_write_config32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
- pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); if (is_registered(ctrl)) { printk(BIOS_DEBUG, "Registered\n"); } else {
@@ -1233,7 +1229,7 @@ goto single_channel; } /* If the cpu is not capable of doing dual channels don't do dual channels */
- nbcap = pci_read_config32(0, ctrl->f3, NORTHBRIDGE_CAP);
- nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); if (!(nbcap & NBCAP_128Bit)) { goto single_channel; }
@@ -1265,10 +1261,10 @@ } printk(BIOS_SPEW, "Enabling dual channel memory\n"); u32 dcl;
- dcl = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_LOW);
- dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl &= ~DCL_32ByteEn; dcl |= DCL_128BitEn;
- pci_write_config32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
- pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); return dimm_mask; single_channel: dimm_mask &= ~((1 << (DIMM_SOCKETS *2)) - (1 << DIMM_SOCKETS));
@@ -1389,7 +1385,7 @@ [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ };
- value = pci_read_config32(0, ctrl->f3, NORTHBRIDGE_CAP);
value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
@@ -1540,7 +1536,7 @@ result.param = get_mem_param(min_cycle_time);
/* Update DRAM Config High with our selected memory speed */
- value = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_HIGH);
- value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); value &= ~(DCH_MEMCLK_MASK << DCH_MEMCLK_SHIFT);
#if 0 /* Improves DQS centering by correcting for case when core speed multiplier and MEMCLK speed @@ -1554,14 +1550,14 @@ #endif
value |= result.param->dch_memclk;
- pci_write_config32(0, ctrl->f2, DRAM_CONFIG_HIGH, value);
pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value);
static const unsigned latencies[] = { DTL_CL_2, DTL_CL_2_5, DTL_CL_3 }; /* Update DRAM Timing Low with our selected cas latency */
- value = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
- value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT); value |= latencies[min_latency - 2] << DTL_TCL_SHIFT;
- pci_write_config32(0, ctrl->f2, DRAM_TIMING_LOW, value);
pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value);
result.dimm_mask = dimm_mask; return result;
@@ -1590,14 +1586,14 @@ return 0; }
- dtl = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
- dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); old_clocks = ((dtl >> DTL_TRC_SHIFT) & DTL_TRC_MASK) + DTL_TRC_BASE; if (old_clocks > clocks) { clocks = old_clocks; } dtl &= ~(DTL_TRC_MASK << DTL_TRC_SHIFT); dtl |= ((clocks - DTL_TRC_BASE) << DTL_TRC_SHIFT);
- pci_write_config32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
- pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); return 1;
}
@@ -1618,14 +1614,14 @@ if (clocks > DTL_TRFC_MAX) { return 0; }
- dtl = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
- dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); old_clocks = ((dtl >> DTL_TRFC_SHIFT) & DTL_TRFC_MASK) + DTL_TRFC_BASE; if (old_clocks > clocks) { clocks = old_clocks; } dtl &= ~(DTL_TRFC_MASK << DTL_TRFC_SHIFT); dtl |= ((clocks - DTL_TRFC_BASE) << DTL_TRFC_SHIFT);
- pci_write_config32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
- pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); return 1;
}
@@ -1644,14 +1640,14 @@ if (clocks > DTL_TRCD_MAX) { return 0; }
- dtl = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
- dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); old_clocks = ((dtl >> DTL_TRCD_SHIFT) & DTL_TRCD_MASK) + DTL_TRCD_BASE; if (old_clocks > clocks) { clocks = old_clocks; } dtl &= ~(DTL_TRCD_MASK << DTL_TRCD_SHIFT); dtl |= ((clocks - DTL_TRCD_BASE) << DTL_TRCD_SHIFT);
- pci_write_config32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
- pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); return 1;
}
@@ -1669,14 +1665,14 @@ if (clocks > DTL_TRRD_MAX) { return 0; }
- dtl = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
- dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); old_clocks = ((dtl >> DTL_TRRD_SHIFT) & DTL_TRRD_MASK) + DTL_TRRD_BASE; if (old_clocks > clocks) { clocks = old_clocks; } dtl &= ~(DTL_TRRD_MASK << DTL_TRRD_SHIFT); dtl |= ((clocks - DTL_TRRD_BASE) << DTL_TRRD_SHIFT);
- pci_write_config32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
- pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); return 1;
}
@@ -1694,14 +1690,14 @@ if (clocks > DTL_TRAS_MAX) { return 0; }
- dtl = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
- dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE; if (old_clocks > clocks) { clocks = old_clocks; } dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT); dtl |= ((clocks - DTL_TRAS_BASE) << DTL_TRAS_SHIFT);
- pci_write_config32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
- pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); return 1;
}
@@ -1719,34 +1715,34 @@ if (clocks > DTL_TRP_MAX) { return 0; }
- dtl = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
- dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); old_clocks = ((dtl >> DTL_TRP_SHIFT) & DTL_TRP_MASK) + DTL_TRP_BASE; if (old_clocks > clocks) { clocks = old_clocks; } dtl &= ~(DTL_TRP_MASK << DTL_TRP_SHIFT); dtl |= ((clocks - DTL_TRP_BASE) << DTL_TRP_SHIFT);
- pci_write_config32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
- pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); return 1;
}
static void set_Twr(const struct mem_controller *ctrl, const struct mem_param *param) { u32 dtl;
- dtl = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
- dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); dtl &= ~(DTL_TWR_MASK << DTL_TWR_SHIFT); dtl |= (param->dtl_twr - DTL_TWR_BASE) << DTL_TWR_SHIFT;
- pci_write_config32(0, ctrl->f2, DRAM_TIMING_LOW, dtl);
- pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
}
static void init_Tref(const struct mem_controller *ctrl, const struct mem_param *param) { u32 dth;
- dth = pci_read_config32(0, ctrl->f2, DRAM_TIMING_HIGH);
- dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH); dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT); dth |= (param->dch_tref4k << DTH_TREF_SHIFT);
- pci_write_config32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
- pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
}
static int update_dimm_Tref(const struct mem_controller *ctrl, const struct mem_param *param, int i) @@ -1763,7 +1759,7 @@ tref = param->dch_tref4k; }
- dth = pci_read_config32(0, ctrl->f2, DRAM_TIMING_HIGH);
- dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH); old_tref = (dth >> DTH_TREF_SHIFT) & DTH_TREF_MASK; if ((value == 12) && (old_tref == param->dch_tref4k)) { tref = param->dch_tref4k;
@@ -1772,7 +1768,7 @@ } dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT); dth |= (tref << DTH_TREF_SHIFT);
- pci_write_config32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
- pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth); return 1;
}
@@ -1803,12 +1799,12 @@ dimm |= 1<<(DCL_x4DIMM_SHIFT+i+2); } #endif
- dcl = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_LOW);
- dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl &= ~dimm; if (value == 4) { dcl |= dimm; }
- pci_write_config32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
- pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); return 1;
}
@@ -1821,9 +1817,9 @@ return -1; } if (value != 2) {
dcl = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_LOW);
dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
pci_write_config32(0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);} @@ -1835,7 +1831,7 @@ dimms = 0; for(index = 0; index < 8; index += 2) { u32 csbase;
csbase = pci_read_config32(0, ctrl->f2, (DRAM_CSBASE + (index << 2)));
csbase = pci_read_config32(ctrl->f2, (DRAM_CSBASE + (index << 2)));@@ -1847,10 +1843,10 @@ { u32 dth;
- dth = pci_read_config32(0, ctrl->f2, DRAM_TIMING_HIGH);
- dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH); dth &= ~(DTH_TWTR_MASK << DTH_TWTR_SHIFT); dth |= ((param->dtl_twtr - DTH_TWTR_BASE) << DTH_TWTR_SHIFT);
- pci_write_config32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
- pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
}
static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param *param) @@ -1858,10 +1854,10 @@ u32 dth, dtl; unsigned latency; unsigned clocks;
- int lat, mtype;
int lat = 0, mtype;
clocks = 0;
- dtl = pci_read_config32(0, ctrl->f2, DRAM_TIMING_LOW);
dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); latency = (dtl >> DTL_TCL_SHIFT) & DTL_TCL_MASK;
if (is_opteron(ctrl)) {
@@ -1891,10 +1887,10 @@ die("Unknown Trwt\n"); }
- dth = pci_read_config32(0, ctrl->f2, DRAM_TIMING_HIGH);
- dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH); dth &= ~(DTH_TRWT_MASK << DTH_TRWT_SHIFT); dth |= ((clocks - DTH_TRWT_BASE) << DTH_TRWT_SHIFT);
- pci_write_config32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
- pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth); return;
}
@@ -1908,10 +1904,10 @@ } else { clocks = 1; }
- dth = pci_read_config32(0, ctrl->f2, DRAM_TIMING_HIGH);
- dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH); dth &= ~(DTH_TWCL_MASK << DTH_TWCL_SHIFT); dth |= ((clocks - DTH_TWCL_BASE) << DTH_TWCL_SHIFT);
- pci_write_config32(0, ctrl->f2, DRAM_TIMING_HIGH, dth);
- pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
}
@@ -1942,7 +1938,7 @@ die("Unknown rdpreamble for this nr of slots"); }
- dch = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_HIGH);
- dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); dch &= ~(DCH_RDPREAMBLE_MASK << DCH_RDPREAMBLE_SHIFT); rdpreamble = param->rdpreamble[i];
@@ -1951,7 +1947,7 @@ }
dch |= (rdpreamble - DCH_RDPREAMBLE_BASE) << DCH_RDPREAMBLE_SHIFT;
- pci_write_config32(0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
- pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
}
static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param) @@ -1962,7 +1958,7 @@
dimms = count_dimms(ctrl);
- dch = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_HIGH);
- dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); dch &= ~(DCH_ASYNC_LAT_MASK << DCH_ASYNC_LAT_SHIFT); async_lat = 0; if (is_registered(ctrl)) {
@@ -1989,18 +1985,18 @@ } } dch |= ((async_lat - DCH_ASYNC_LAT_BASE) << DCH_ASYNC_LAT_SHIFT);
- pci_write_config32(0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
- pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
}
static void set_idle_cycle_limit(const struct mem_controller *ctrl, const struct mem_param *param) { u32 dch; /* AMD says to Hardcode this */
- dch = pci_read_config32(0, ctrl->f2, DRAM_CONFIG_HIGH);
- dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); dch &= ~(DCH_IDLE_LIMIT_MASK << DCH_IDLE_LIMIT_SHIFT); dch |= DCH_IDLE_LIMIT_16 << DCH_IDLE_LIMIT_SHIFT; dch |= DCH_DYN_IDLE_CTR_EN;
- pci_write_config32(0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
- pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
}
static long spd_set_dram_timing(const struct mem_controller *ctrl, const struct mem_param *param, long dimm_mask) @@ -2050,8 +2046,10 @@ return dimm_mask; }
-static void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) +void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) {
- void activate_spd_rom(const struct mem_controller *ctrl);
- struct spd_set_memclk_result result; const struct mem_param *param; long dimm_mask;
@@ -2106,22 +2104,22 @@ carry_over = (4*1024*1024) - hole_startk;
for(ii=controllers - 1;ii>i;ii--) {
base = pci_read_config32(0, ctrl[0].f1, 0x40 + (ii << 3));
base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { continue; }
limit = pci_read_config32(0, ctrl[0].f1, 0x44 + (ii << 3));
limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3)); for(j = 0; j < controllers; j++) {
pci_write_config32(0, ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2));pci_write_config32(0, ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2));
pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2));pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2)); } }
limit = pci_read_config32(0, ctrl[0].f1, 0x44 + (i << 3));
limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3)); for(j = 0; j < controllers; j++) {
pci_write_config32(0, ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2));
pci_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2)); } dev = ctrl[i].f1;
base = pci_read_config32(0, dev, 0x40 + (i << 3));
base = pci_read_config32(dev, 0x40 + (i << 3)); basek = (base & 0xffff0000) >> 2; if(basek == hole_startk) { //don't need set memhole here, because hole off set will be 0, overflow@@ -2129,7 +2127,7 @@ base &= 0x0000ffff; base |= (4*1024*1024)<<2; for(j = 0; j < controllers; j++) {
pci_write_config32(0, ctrl[j].f1, 0x40 + (i<<3), base);
pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base); } }@@ -2139,7 +2137,7 @@ (((basek + carry_over) >> 6) & 0x0000ff00) + /* enable */ 1;
pci_write_config32(0, dev, 0xf0, hoist);
pci_write_config32(dev, 0xf0, hoist);}
return carry_over;@@ -2163,7 +2161,7 @@ for(i=0; i<controllers; i++) { u32 base; unsigned base_k;
base = pci_read_config32(0, ctrl[0].f1, 0x40 + (i << 3));
base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { continue; }@@ -2183,11 +2181,11 @@ for(i=0; i<controllers; i++) { u32 base, limit; unsigned base_k, limit_k;
base = pci_read_config32(0, ctrl[0].f1, 0x40 + (i << 3));
base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { continue; }
limit = pci_read_config32(0, ctrl[0].f1, 0x44 + (i << 3));
limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3)); base_k = (base & 0xffff0000) >> 2; limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2; if ((base_k <= hole_startk) && (limit_k > hole_startk)) {@@ -2204,10 +2202,10 @@ #endif
#define TIMEOUT_LOOPS 300000 -static void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo) +void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo) { int i;
- void memreset(int controllers, const struct mem_controller *ctrl); /* Error if I don't have memory */ if (memory_end_k(ctrl, controllers) == 0) { die("No memory\n");
@@ -2218,17 +2216,17 @@ u32 dch; if (!controller_present(ctrl + i)) continue;
dch = pci_read_config32(0, ctrl[i].f2, DRAM_CONFIG_HIGH);
dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
pci_write_config32(0, ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
dcl = pci_read_config32(0, ctrl[i].f2, DRAM_CONFIG_LOW);
dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); dcl |= DCL_DisInRcvrs;
pci_write_config32(0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);@@ -2242,31 +2240,31 @@ if (!controller_present(ctrl + i)) continue; /* Skip everything if I don't have any memory on this controller */
dch = pci_read_config32(0, ctrl[i].f2, DRAM_CONFIG_HIGH);
dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);if (!(dch & DCH_MEMCLK_VALID)) { continue; }
/* Toggle DisDqsHys to get it working */
dcl = pci_read_config32(0, ctrl[i].f2, DRAM_CONFIG_LOW);
dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
mnc = pci_read_config32(0, ctrl[i].f3, MCA_NB_CONFIG);
mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG); mnc |= MNC_ECC_EN; if (dcl & DCL_128BitEn) { mnc |= MNC_CHIPKILL_EN; }
pci_write_config32(0, ctrl[i].f3, MCA_NB_CONFIG, mnc);
pci_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc);
pci_write_config32(0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
pci_write_config32(0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);} for(i = 0; i < controllers; i++) {
@@ -2274,7 +2272,7 @@ if (!controller_present(ctrl + i)) continue; /* Skip everything if I don't have any memory on this controller */
dch = pci_read_config32(0, ctrl[i].f2, DRAM_CONFIG_HIGH);
dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);@@ -2283,7 +2281,7 @@
int loops = 0; do {
dcl = pci_read_config32(0, ctrl[i].f2, DRAM_CONFIG_LOW);
dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); loops += 1; if ((loops & 1023) == 0) { printk(BIOS_DEBUG, ".");@@ -2297,9 +2295,9 @@ if (!is_cpu_pre_c0()) { /* Wait until it is safe to touch memory */ dcl &= ~(DCL_MemClrStatus | DCL_DramEnable);
pci_write_config32(0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); do {
dcl = pci_read_config32(0, ctrl[i].f2, DRAM_CONFIG_LOW);
dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); } while(((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) );@@ -2324,11 +2322,11 @@
}
-static void set_sysinfo_in_ram(unsigned val) +void set_sysinfo_in_ram(unsigned val) { }
-static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const u16 *spd_addr) +void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const u16 *spd_addr) { int i; int j;
Index: northbridge/amd/k8/Makefile
--- northbridge/amd/k8/Makefile (revision 730) +++ northbridge/amd/k8/Makefile (working copy) @@ -21,6 +21,4 @@
ifeq ($(CONFIG_NORTHBRIDGE_AMD_K8),y)
-STAGE2_CHIPSET_SRC += $(src)/northbridge/amd/k8/raminit.c
endif
the k8 north makefile and raminit.c are committed rev 736.
Current status: Index: southbridge/nvidia/mcp55/mcp55_smbus.h Index: northbridge/amd/k8/incoherent_ht.c Index: arch/x86/Kconfig
ron
On 11.08.2008 02:18, ron minnich wrote:
the k8 north makefile and raminit.c are committed rev 736.
Current status: Index: southbridge/nvidia/mcp55/mcp55_smbus.h
I believe that one was never posted.
Index: northbridge/amd/k8/incoherent_ht.c
Too late at night for me to review. Sorry. Reading a few thousand lines of code intensely wore me out.
Index: arch/x86/Kconfig
Review sent a few seconds ago.
Regards, Carl-Daniel
On Sun, Aug 10, 2008 at 5:30 PM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
On 11.08.2008 02:18, ron minnich wrote:
the k8 north makefile and raminit.c are committed rev 736.
Current status: Index: southbridge/nvidia/mcp55/mcp55_smbus.h
I believe that one was never posted.
attached.
New arch/x86/Kconfig attached. I responded to all the comments save this one:
+config K8_SCAN_PCI_BUS
hexdefault 0 if CPU_AMD_K8helpWhether to scan the PCI bus on startup
Since when do we not scan the PCI bus by default?
+config K8_ALLOCATE_IO_RANGE
hexdefault 0 if CPU_AMD_K8helpWhether to allocate IO space on startup
Same question here.
Stage 1 again. Let's keep in mind, the rules in stage1 vary by mainboard for good reasons in most cases. I don't want to get into this at this time, this code has been this way for years on v2.
thanks
ron
On 11.08.2008 06:11, ron minnich wrote:
On Sun, Aug 10, 2008 at 5:30 PM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
On 11.08.2008 02:18, ron minnich wrote:
the k8 north makefile and raminit.c are committed rev 736.
Current status: Index: southbridge/nvidia/mcp55/mcp55_smbus.h
I believe that one was never posted.
attached.
New arch/x86/Kconfig attached. I responded to all the comments save this one:
+config K8_SCAN_PCI_BUS
hexdefault 0 if CPU_AMD_K8helpWhether to scan the PCI bus on startupSince when do we not scan the PCI bus by default?
+config K8_ALLOCATE_IO_RANGE
hexdefault 0 if CPU_AMD_K8helpWhether to allocate IO space on startupSame question here.
Stage 1 again. Let's keep in mind, the rules in stage1 vary by mainboard for good reasons in most cases. I don't want to get into this at this time, this code has been this way for years on v2.
New config variables for K8.
Signed-off-by: Ronald G. Minnich rminnich@gmail.com
Index: arch/x86/Kconfig
Agreed. I tripped on the "on startup" phrase. Your change to "in stage1" is perfect. Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Move code to a .c file -- now there's an idea!
Signed-off-by: Ronald G. Minnich rminnich@gmail.com
Index: southbridge/nvidia/mcp55/mcp55_smbus.h
Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Regards, Carl-Daniel
On 10.08.2008 23:24, ron minnich wrote:
x86 Kconfig changes
Index: arch/x86/Kconfig
--- arch/x86/Kconfig (revision 730) +++ arch/x86/Kconfig (working copy) @@ -56,6 +56,56 @@ arch/x86/Makefile for more hints on possible values. It is usually set in mainboard/*/Kconfig.
+config K8_REV_F_SUPPORT
- hex
- default 0 if CPU_AMD_K8
- help
Whether to include rev F support -- this includes a different type of dram.
80 column limit? Also, what's the different type of DRAM?
+config K8_SCAN_PCI_BUS
- hex
- default 0 if CPU_AMD_K8
- help
Whether to scan the PCI bus on startup
Since when do we not scan the PCI bus by default?
+config K8_ALLOCATE_IO_RANGE
- hex
- default 0 if CPU_AMD_K8
- help
Whether to allocate IO space on startup
Same question here.
+config K8_ALLOCATE_MMIO_RANGE
- hex
- default 0 if CPU_AMD_K8
- help
Whether to allocate MMIO space on startup. Comment from code:Do we need allocate MMIO? Currently we direct last 64M to southbridge link (sblink) only,We can not lose access to last 4M range to ROM.+config LOGICAL_CPUS
- hex
- default 1
- help
How many logical CPUs there are. Fix me.+config MAX_PHYSICAL_CPUS
- hex
- default 1
- help
Max number of physical CPUs (sockets)+config MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
- hex
- default 0 if CPU_AMD_K8
- help
Config with 4 CPUs even if more are installed+config CROSS_BAR_47_56
- hex
- default 0 if CPU_AMD_K8
- help
Configure for the type of crossbar on the mainboard.config OPTION_TABLE boolean help @@ -93,3 +143,42 @@ default 0x8000 if CPU_AMD_K8 help This option sets the size of the area used for CAR.
+# variables related to AMD Hypertranspost.
HypertranspoRt.
+config HT_CHAIN_UNITID_BASE
- hex
- default 0 if CPU_AMD_K8
- help
Hypertransport unit ID base value. Mainboard-dependent.+config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20 if CPU_AMD_K8
- help
Unit id of the end of hypertransport chain (usually the real SB); if it is < than HT_CHAIN_UNITID_BASE, it can be 0
80 columns?
+config SB_HT_CHAIN_UNITID_OFFSET_ONLY
- hex
default 1 if CPU_AMD_K8helpDetermines (I don't understand; ask YHLU) if only offset SB hypertransport chain+config SB_HT_CHAIN_ON_BUS0
- hex
default 0 if CPU_AMD_K8helpMake SB hypertransport chain sit on bus 0, if it is 1, will put sb ht chain on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0
80 columns.
+config K8_HT_FREQ_1G_SUPPORT
- hex
- default 1 if CPU_AMD_K8
- help
1 Ghz. support. Opteron E0 or later can support 1G HT, but still depends on mainboard+config HT_FREQ_800Mhz
All caps PLEASE: ;-)
- hex
- default 1 if CPU_AMD_K8
- help
Can we run HT at 1 Ghz.
Help text doesn't match config name.
Regards, Carl-Daniel
This patch is for include/ to add k8 includes.
ron
On 10.08.2008 23:25, ron minnich wrote:
This patch is for include/ to add k8 includes.
ron
Add defines for K8
Signed-off-by: Ronald G. Minnich rminnich@gmail.com
Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Regards, Carl-Daniel
On Sun, Aug 10, 2008 at 2:45 PM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
On 10.08.2008 23:25, ron minnich wrote:
This patch is for include/ to add k8 includes.
ron
Add defines for K8
Signed-off-by: Ronald G. Minnich rminnich@gmail.com
Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Committed revision 732.
Ühel kenal päeval, P, 2008-08-10 kell 15:03, kirjutas ron minnich:
On Sun, Aug 10, 2008 at 2:45 PM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
On 10.08.2008 23:25, ron minnich wrote:
This patch is for include/ to add k8 includes.
ron
Add defines for K8
Signed-off-by: Ronald G. Minnich rminnich@gmail.com
Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Committed revision 732.
This broke the build of all GeodeLX targets, because the define of PCI_DEVICE_ID_AMD_LXBRIDGE lost a newline before it and got to the same line as PCI_DEVICE_ID_AMD_VIPER_7412 - including in the reviewed attachment. Not a big deal, I've committed a trivial fix with a self-ack in r737 as follows:
Author: mraudsepp mraudsepp@f3766cd6-281f-0410-b1cd-43a5c92072e9 Date: Mon Aug 11 13:23:40 2008 +0000
Trivial: Add a missing newline in front of PCI_DEVICE_ID_AMD_LXBRIDGE define, lost in r732
Fixes geodelx target builds, compile-tested on DBE62
Signed-off-by: Mart Raudsepp mart.raudsepp@artecdesign.ee Acked-by: Mart Raudsepp mart.raudsepp@artecdesign.ee
git-svn-id: svn://coreboot.org/repository/coreboot-v3@737 f3766cd6-281f-0410-b1cd-43a5c92072e9
diff --git a/include/device/pci_ids.h b/include/device/pci_ids.h index b65c3d2..4136fd0 100644 --- a/include/device/pci_ids.h +++ b/include/device/pci_ids.h @@ -191,7 +191,8 @@ #define PCI_DEVICE_ID_AMD_AES 0x2082 #define PCI_DEVICE_ID_AMD_761_0 0x700E #define PCI_DEVICE_ID_AMD_761_1 0x700F -#define PCI_DEVICE_ID_AMD_VIPER_7412 0x7412#define PCI_DEVICE_ID_AMD_LXBRIDGE 0x2080 +#define PCI_DEVICE_ID_AMD_VIPER_7412 0x7412 +#define PCI_DEVICE_ID_AMD_LXBRIDGE 0x2080 #define PCI_DEVICE_ID_AMD_CS5536_ISA 0x2090 #define PCI_DEVICE_ID_AMD_CS5536_FLASH 0x2091 #define PCI_DEVICE_ID_AMD_CS5536_A0_IDE 0x2092
On 11.08.2008 15:29, Mart Raudsepp wrote:
Ühel kenal päeval, P, 2008-08-10 kell 15:03, kirjutas ron minnich:
On Sun, Aug 10, 2008 at 2:45 PM, Carl-Daniel Hailfinger wrote:
On 10.08.2008 23:25, ron minnich wrote:
This patch is for include/ to add k8 includes.
ron
Add defines for K8
Signed-off-by: Ronald G. Minnich rminnich@gmail.com
Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Committed revision 732.
This broke the build of all GeodeLX targets, because the define of PCI_DEVICE_ID_AMD_LXBRIDGE lost a newline before it and got to the same line as PCI_DEVICE_ID_AMD_VIPER_7412 - including in the reviewed attachment.
My apologies. I try to review as well as possible and it seems I overlooked that.
Thanks for fixing this!
Regards, Carl-Daniel
Thanks Mart, sorry for the mistake. I will now do a geode build if I change common files from now on.
That's one thing that is still better in v2 -- it's very easy to "build all targets" without a reconfig operation (we designed it that way :-)
ron
mainboard patched.
ron
On 10.08.2008 23:27, ron minnich wrote:
Add more support so mainboard and other bits build correctly.
Signed-off-by: Ronald G. Minnich rminnich@gmail.com
One comment below, otherwise Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Index: mainboard/gigabyte/m57sli/initram.c
--- mainboard/gigabyte/m57sli/initram.c (revision 730) +++ mainboard/gigabyte/m57sli/initram.c (working copy) @@ -29,6 +29,7 @@ #include <string.h> #include <msr.h> #include <io.h> +#include <cpu.h> #include <amd/k8/k8.h> #include <spd.h>
Index: mainboard/gigabyte/m57sli/stage1.c
--- mainboard/gigabyte/m57sli/stage1.c (revision 730) +++ mainboard/gigabyte/m57sli/stage1.c (working copy) @@ -23,12 +23,29 @@ #include <lib.h> #include <console.h> #include <device/device.h> +#include <cpu.h> +#include <amd/k8/k8.h> +#include <amd/k8/sysconf.h> #include <device/pci.h> #include <string.h> #include <msr.h> #include <io.h> #include <arch/x86/msr.h>
+void memreset_setup(void) +{ +}
+void memreset(int controllers, const struct mem_controller *ctrl) +{ +}
+void activate_spd_rom(const struct mem_controller *ctrl) +{
- /* nothing to do */
+}
void hardware_stage1(void) { post_code(POST_START_OF_MAIN); Index: mainboard/gigabyte/m57sli/Makefile =================================================================== --- mainboard/gigabyte/m57sli/Makefile (revision 730) +++ mainboard/gigabyte/m57sli/Makefile (working copy) @@ -21,10 +21,12 @@
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o \ $(obj)/mainboard/$(MAINBOARDDIR)/option_table.c \
$(obj)/southbridge/nvidia/mcp55/stage1_smbus.o
$(obj)/southbridge/nvidia/mcp55/stage1_smbus.o \$(obj)/mainboard/$(MAINBOARDDIR)/initram.o \$(obj)/northbridge/amd/k8/raminit.o \$(obj)/northbridge/amd/k8/coherent_ht.o \$(obj)/northbridge/amd/k8/incoherent_ht.o-INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c
Is that INITRAM_SRC removal intentional? If yes, OK. If not, please fix.
STAGE2_MAINBOARD_SRC =
$(obj)/coreboot.vpd:
Regards, Carl-Daniel
On Sun, Aug 10, 2008 at 2:49 PM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote: rthbridge/amd/k8/incoherent_ht.o
-INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c
Is that INITRAM_SRC removal intentional? If yes, OK. If not, please fix.
I put it back as INITRAM_SRC=
Something is not working and files I put there did not get built. I welcome a fix, I put a comment in the Makefile as to what is needed. Committed revision 733.
ron
move C code to a .c file -- this has been shown at times to save space
ron
On 10.08.2008 23:28, ron minnich wrote:
move C code to a .c file -- this has been shown at times to save space
ron
You forgot to run svn add. The new file is missing.
If it's just a code move: Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Regards, Carl-Daniel
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Carl-Daniel Hailfinger -
Mart Raudsepp -
ron minnich