Hello Alex,
I would like to thank you for the help. We were able to track down the problem with the
native and legacy SATA IDE mode.
Coreboot code helped in the process.
Stay in touch. :-)
Best Regards,
Zoran
-----Original Message-----
From: Alexandru Gagniuc [mailto:mr.nuke.me@gmail.com]
Sent: Monday, February 09, 2015 8:37 AM
To: coreboot(a)coreboot.org
Cc: Stojsavljevic, Zoran; Patrick Georgi; Marc Jones; 'Berth-Olof Bergman'
Subject: Re: [coreboot] Bay trail and SATA legacy IDE mode
On Monday, February 09, 2015 07:05:04 AM Stojsavljevic, Zoran wrote:
But still... I have some limited knowledge of Coreboot
from 15 months
ago, and I am trying to understand if Coreboot x86 code has some
influence on the SATA IDE mode. From what I am reading... There is a possibility!
Check src/soc/intel/baytrail/sata.c on how the registers are configured based on
devicetree.cb
if (!config->sata_ahci) {
/* Set legacy or native decoding mode */
if (config->ide_legacy_combined) {
The silicon is BYT SoC, ATOM. The boot time to OS
bootloader is around 300
ms.
My best understanding how this enumeration works for
SATA is that all SATA
are put in default AHCI mode. But some people (As Berth) must have SATA
interfaces in IDE mode.
register "sata_ahci" = "0"
register "ide_legacy_combined" = "1"
Alex
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