Re: [coreboot] Microcode problem with Braswell CPU

[Alexander Böcken]

Hello Zoran,

read_microcode_rev() returns 0,
msr.lo is 0xFFE68430,
msr.hi is 0

These values are all good, as far as I can tell.
However, I had to dump these as post codes, because printk is not available in this early
stage in bootblock.

Microcode problem with Braswell CPU

[Zoran Stojsavljevic]

Hello Alex,

Thank you for notifying us with the data. Appreciated.

I did some stuff with BYT-I and BYT-M. I would expect, if you run FSP on
BYT-I Stepping D0, to see for CPUID 0x30679, and for MCU to see 0x901,
0x903 and maybe more. If you run BYT-M Stepping C0, to see for CPUID
0x30678 and MCU 0x322, 0x324 or 0x325 (if I recall correctly).

If you see for BSW MCU 0x0, something is fishy. You do not have either any
MCU to update with, or the new one (which you probably collected from the
public site):
http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-s…

*Intel® Pentium® and Celeron® Processor N3000 Product Families and Intel®
Atom™ x5-Z8300 Processor *(formerly Braswell, Compliant with FSP v1.1
Specification)

   - Windows* release version 001 >
  
<http://www.intel.com/content/www/us/en/embedded/software/fsp/pentium-celeron-n3000-atom-x5-z8300-fsp-windows-download.html>
   - Linux* release version 001 >
  
<http://www.intel.com/content/www/us/en/embedded/software/fsp/pentium-celeron-n3000-atom-x5-z8300-fsp-linux-download.html>
   - Release notes >
  
<http://www.intel.com/content/www/us/en/embedded/software/fsp/pentium-celeron-n3000-atom-x5-z8300-fsp-release-notes.html>
   - Readme >
  
<http://www.intel.com/content/www/us/en/embedded/software/fsp/pentium-celeron-n3000-atom-x5-z8300-fsp-readme.html>

...is somehow not reachable by Coreboot/Romstage.

So, I have here the following questions:
[1] Does Coreboot has FSP 1.1 spec. implemented for BSW already (5 APIs
calls, not 3)?
[2] Dids you download the latest BSW MCU (for which BSW), and how big the
latest BSW MCU update is?
===> Please, look into:
http://review.coreboot.org/gitweb?p=coreboot.git;a=commitdiff;h=01a56f4ea0f…
And pay attention to the following:
http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/soc/intel/fsp…

Just trying to help.

Please, Werner (Zeh), any other clues you (maybe) have for Alex?

Thank you,
Zoran
_______

On Fri, Apr 29, 2016 at 11:54 AM, Alexander Böcken <
Alexander.Boecken(a)junger-audio.com&gt; wrote:

  Hello Zoran,

 read_microcode_rev() returns 0,
 msr.lo is 0xFFE68430,
 msr.hi is 0

 These values are all good, as far as I can tell.
 However, I had to dump these as post codes, because printk is not
 available in this early stage in bootblock.