[commit] r5372 - in trunk/src: cpu/amd/car cpu/via/car mainboard/asrock/939a785gmh mainboard/digitallogic/msm586seg mainboard/gigabyte/ga_2761gxdk mainboard/jetway/j7f24 mainboard/via/epia mainboar...
Author: stepan Date: Wed Apr 7 17:40:26 2010 New Revision: 5372 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5372
Log: - copy_and_run() gets the same calling convention on AMD and on all the others. - some vx800 Kconfig fixes - remove warnings... Signed-off-by: Stefan Reinauer stepan@coresystems.de Acked-by: Stefan Reinauer stepan@coresystems.de
Modified: trunk/src/cpu/amd/car/copy_and_run.c trunk/src/cpu/amd/car/post_cache_as_ram.c trunk/src/cpu/via/car/cache_as_ram.lds trunk/src/mainboard/asrock/939a785gmh/romstage.c trunk/src/mainboard/digitallogic/msm586seg/mainboard.c trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c trunk/src/mainboard/jetway/j7f24/romstage.c trunk/src/mainboard/via/epia-m700/fadt.c trunk/src/mainboard/via/epia-m700/romstage.c trunk/src/mainboard/via/epia-m700/wakeup.c trunk/src/mainboard/via/epia/romstage.c trunk/src/northbridge/via/vx800/northbridge.c trunk/src/northbridge/via/vx800/pci_rawops.h trunk/src/northbridge/via/vx800/vx800_ide.c trunk/src/northbridge/via/vx800/vx800_lpc.c
Modified: trunk/src/cpu/amd/car/copy_and_run.c ============================================================================== --- trunk/src/cpu/amd/car/copy_and_run.c Wed Apr 7 17:32:52 2010 (r5371) +++ trunk/src/cpu/amd/car/copy_and_run.c Wed Apr 7 17:40:26 2010 (r5372) @@ -1,17 +1,30 @@ -/* by yhlu 6.2005 - moved from nrv2v.c and some lines from crt0.S - 2006/05/02 - stepan: move nrv2b to an extra file. -*/ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */
void cbfs_and_run_core(const char *filename, unsigned ebp);
-static void copy_and_run(void) +static void copy_and_run(unsigned cpu_reset) { - cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram", 0); + cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram", cpu_reset); }
#if CONFIG_AP_CODE_IN_CAR == 1 - static void copy_and_run_ap_code_in_car(unsigned ret_addr) { cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ap", ret_addr);
Modified: trunk/src/cpu/amd/car/post_cache_as_ram.c ============================================================================== --- trunk/src/cpu/amd/car/post_cache_as_ram.c Wed Apr 7 17:32:52 2010 (r5371) +++ trunk/src/cpu/amd/car/post_cache_as_ram.c Wed Apr 7 17:40:26 2010 (r5372) @@ -112,7 +112,7 @@ // wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c #endif /*copy and execute coreboot_ram */ - copy_and_run(); + copy_and_run(0); /* We will not return */
print_debug("should not be here -\n");
Modified: trunk/src/cpu/via/car/cache_as_ram.lds ============================================================================== --- trunk/src/cpu/via/car/cache_as_ram.lds Wed Apr 7 17:32:52 2010 (r5371) +++ trunk/src/cpu/via/car/cache_as_ram.lds Wed Apr 7 17:40:26 2010 (r5372) @@ -27,5 +27,4 @@ . = ALIGN(16); _einit = .; } - }
Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/romstage.c Wed Apr 7 17:32:52 2010 (r5371) +++ trunk/src/mainboard/asrock/939a785gmh/romstage.c Wed Apr 7 17:40:26 2010 (r5372) @@ -102,7 +102,7 @@
#include "northbridge/amd/amdk8/early_ht.c"
-void sio_init(void) +static void sio_init(void) { u8 reg;
Modified: trunk/src/mainboard/digitallogic/msm586seg/mainboard.c ============================================================================== --- trunk/src/mainboard/digitallogic/msm586seg/mainboard.c Wed Apr 7 17:32:52 2010 (r5371) +++ trunk/src/mainboard/digitallogic/msm586seg/mainboard.c Wed Apr 7 17:40:26 2010 (r5372) @@ -7,12 +7,10 @@ #include "chip.h"
-static void irqdump() +static void irqdump(void) { volatile unsigned char *irq; void *mmcr; - - int i; int irqlist[] = {0xd00, 0xd02, 0xd03, 0xd04, 0xd08, 0xd0a, 0xd14, 0xd18, 0xd1a, 0xd1b, 0xd1c, @@ -34,8 +32,9 @@ /* TODO: finish up mmcr struct in sc520.h, and; - set ADDDECTL (now done in raminit.c in cpu/amd/sc520 */ -static void enable_dev(struct device *dev) { - volatile struct mmcrpic *pic = MMCRPIC; +static void enable_dev(struct device *dev) +{ + //volatile struct mmcrpic *pic = MMCRPIC; volatile struct mmcr *mmcr = MMCRDEFAULT;
/* msm586seg has this register set to a weird value. @@ -72,15 +71,11 @@ mmcr->pic.gp10imap = 0x9; mmcr->pic.gp9imap = 0x4;
- - - - irqdump(); printk(BIOS_ERR, "uart 1 ctl is 0x%x\n", *(unsigned char *) 0xfffefcc0);
printk(BIOS_ERR, "0xc20 ctl is 0x%x\n", *(unsigned short *) 0xfffefc20); - printk(BIOS_ERR, "0xc22 0x%x\n", *(unsigned short *) 0xfffefc22b); + printk(BIOS_ERR, "0xc22 0x%x\n", *(unsigned short *) 0xfffefc22);
/* The following block has NOT proven sufficient to get * the VGA hardware to talk to us @@ -124,7 +119,7 @@ /* still not interrupts. */ /* their IRQ table is wrong. Just hardwire it */ { - char pciints[4] = {15, 15, 15, 15}; + unsigned char pciints[4] = {15, 15, 15, 15}; pci_assign_irqs(0, 12, pciints); } /* the assigned failed but we just noticed -- there is no @@ -133,6 +128,7 @@ /* follow fuctory here */ mmcr->dmacontrol.extchanmapa = 0x3210; } + struct chip_operations mainboard_ops = { CHIP_NAME("DIGITAL-LOGIC MSM586SEG Mainboard") .enable_dev = enable_dev
Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Wed Apr 7 17:32:52 2010 (r5371) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Wed Apr 7 17:40:26 2010 (r5372) @@ -146,8 +146,6 @@
static void sio_setup(void) { - - unsigned value; uint32_t dword; uint8_t byte;
@@ -175,7 +173,8 @@ #endif };
- struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset = 0; unsigned bsp_apicid = 0;
Modified: trunk/src/mainboard/jetway/j7f24/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/j7f24/romstage.c Wed Apr 7 17:32:52 2010 (r5371) +++ trunk/src/mainboard/jetway/j7f24/romstage.c Wed Apr 7 17:40:26 2010 (r5372) @@ -44,10 +44,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP1) #endif
-static void memreset_setup(void) -{ -} - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); @@ -93,9 +89,6 @@
static void main(unsigned long bist) { - unsigned long x; - device_t dev; - /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
Modified: trunk/src/mainboard/via/epia-m700/fadt.c ============================================================================== --- trunk/src/mainboard/via/epia-m700/fadt.c Wed Apr 7 17:32:52 2010 (r5371) +++ trunk/src/mainboard/via/epia-m700/fadt.c Wed Apr 7 17:40:26 2010 (r5372) @@ -36,8 +36,8 @@ memcpy(header->asl_compiler_id, "LXB", 8); header->asl_compiler_revision = 0;
- fadt->firmware_ctrl = facs; - fadt->dsdt = dsdt; + fadt->firmware_ctrl = (u32)facs; + fadt->dsdt = (u32)dsdt; fadt->preferred_pm_profile = 0; fadt->sci_int = 0x9;
@@ -105,9 +105,9 @@ fadt->reset_reg.addrh = 0x0;
fadt->reset_value = 0; - fadt->x_firmware_ctl_l = facs; + fadt->x_firmware_ctl_l = (u32)facs; fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = dsdt; + fadt->x_dsdt_l = (u32)dsdt; fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = 1;
Modified: trunk/src/mainboard/via/epia-m700/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-m700/romstage.c Wed Apr 7 17:32:52 2010 (r5371) +++ trunk/src/mainboard/via/epia-m700/romstage.c Wed Apr 7 17:40:26 2010 (r5372) @@ -41,7 +41,6 @@ #include "pc80/udelay_io.c" #include "lib/delay.c" #include <string.h> -#include "cpu/x86/lapic/boot_cpu.c"
/* This file contains the board-special SI value for raminit.c. */ #include "driving_clk_phase_data.c" @@ -59,18 +58,6 @@ * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list: * http://www.coreboot.org/pipermail/coreboot/2008-January/028787.html. */ -void jason_tsc_count_car(void) -{ -#if 0 - unsigned long long start; - asm volatile ("rdtsc" : "=A" (start)); - start >>= 20; - print_emerg("jason_tsc_count_car= "); - print_emerg_hex32((unsigned long) start); - print_emerg("\n"); -#endif -} - int acpi_is_wakeup_early_via_vx800(void) { device_t dev; @@ -431,8 +418,6 @@ * g) Rx73h = 32h */
- jason_tsc_count_car(); - pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBA, PCI_DEVICE_ID_VIA_VX855_IDE); pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBE, @@ -462,7 +447,6 @@ * written, then this must be a CPU restart (result of OS reboot cmd), * so we need a real "cold boot". */ - jason_tsc_count_car(); if ((boot_mode != 3) && (pci_read_config8(PCI_DEV(0, 0, 3), 0x80) != 0)) { outb(6, 0xcf9); @@ -471,7 +455,6 @@ /* x86 cold boot I/O cmd. */ /* These 2 lines are the same with epia-cn port. */ enable_smbus(); - jason_tsc_count_car();
/* This fix does help vx800!, but vx855 doesn't need this. */ /* smbus_fixup(&ctrl); */ @@ -564,8 +547,6 @@ /* This line is the same with cx700 port. */ enable_shadow_ram();
- jason_tsc_count_car(); - /* * For coreboot most time of S3 resume is the same as normal boot, * so some memory area under 1M become dirty, so before this happen, @@ -801,7 +782,6 @@ print_debug("\n"); #endif
- jason_tsc_count_car(); /* Copy and execute coreboot_ram. */ copy_and_run(new_cpu_reset); /* We will not return. */
Modified: trunk/src/mainboard/via/epia-m700/wakeup.c ============================================================================== --- trunk/src/mainboard/via/epia-m700/wakeup.c Wed Apr 7 17:32:52 2010 (r5371) +++ trunk/src/mainboard/via/epia-m700/wakeup.c Wed Apr 7 17:40:26 2010 (r5372) @@ -111,9 +111,7 @@
void acpi_jump_wake(u32 vector) { - u32 tmp, dwEip; - u16 tmpvector; - u8 Data; + u32 dwEip; struct Xgt_desc_struct *wake_thunk16_Xgt_desc;
printk(BIOS_DEBUG, "IN ACPI JUMP WAKE TO %x\n", vector);
Modified: trunk/src/mainboard/via/epia/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia/romstage.c Wed Apr 7 17:32:52 2010 (r5371) +++ trunk/src/mainboard/via/epia/romstage.c Wed Apr 7 17:40:26 2010 (r5372) @@ -75,7 +75,7 @@ pci_write_config8(dev, 0x63, shadowreg); }
-void main(unsigned long bist) +static void main(unsigned long bist) { if (bist == 0) { early_mtrr_init();
Modified: trunk/src/northbridge/via/vx800/northbridge.c ============================================================================== --- trunk/src/northbridge/via/vx800/northbridge.c Wed Apr 7 17:32:52 2010 (r5371) +++ trunk/src/northbridge/via/vx800/northbridge.c Wed Apr 7 17:40:26 2010 (r5372) @@ -142,7 +142,6 @@ * this register's value multiply 64 * 1024 * 1024 */ for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { - unsigned char reg; rambits = pci_read_config8(mc_dev, ramregs[i]); if (rambits != 0) break; @@ -179,7 +178,7 @@ assign_resources(&dev->link[0]); }
-static const struct device_operations pci_domain_ops = { +static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, .enable_resources = enable_childrens_resources, @@ -196,7 +195,7 @@ { }
-static const struct device_operations cpu_bus_ops = { +static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_noop, .set_resources = cpu_bus_noop, .enable_resources = cpu_bus_noop,
Modified: trunk/src/northbridge/via/vx800/pci_rawops.h ============================================================================== --- trunk/src/northbridge/via/vx800/pci_rawops.h Wed Apr 7 17:32:52 2010 (r5371) +++ trunk/src/northbridge/via/vx800/pci_rawops.h Wed Apr 7 17:40:26 2010 (r5372) @@ -26,243 +26,260 @@ (((SEGBUS) & 0xFFF) << 20) | \ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x07) << 12)) -struct VIA_PCI_REG_INIT_TABLE { + +struct VIA_PCI_REG_INIT_TABLE { u8 ChipRevisionStart; u8 ChipRevisionEnd; u8 Bus; u8 Device; u8 Function; - u32 Register; + u32 Register; u8 Mask; u8 Value; }; -typedef unsigned device_t_raw; /* pci and pci_mmio need to have different ways to have dev */ +typedef unsigned device_t_raw; /* pci and pci_mmio need to have different ways to have dev */
/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, * We don't need to set %fs, and %gs anymore * Before that We need to use %gs, and leave %fs to other RAM access */ - uint8_t pci_io_rawread_config8(device_t_raw dev, unsigned where) +u8 pci_io_rawread_config8(device_t_raw dev, unsigned where) { unsigned addr; -#if PCI_IO_CFG_EXT == 0 - addr = (dev>>4) | where; +#if CONFIG_PCI_IO_CFG_EXT == 0 + addr = (dev >> 4) | where; #else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0 + addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16); //seg == 0 #endif outl(0x80000000 | (addr & ~3), 0xCF8); return inb(0xCFC + (addr & 3)); }
-#if MMCONF_SUPPORT - uint8_t pci_mmio_rawread_config8(device_t_raw dev, unsigned where) +#if CONFIG_MMCONF_SUPPORT +u8 pci_mmio_rawread_config8(device_t_raw dev, unsigned where) { - unsigned addr; - addr = dev | where; - return read8x(addr); + unsigned addr; + addr = dev | where; + return read8x(addr); } #endif - uint8_t pci_rawread_config8(device_t_raw dev, unsigned where) +u8 pci_rawread_config8(device_t_raw dev, unsigned where) { -#if MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT return pci_mmio_rawread_config8(dev, where); #else return pci_io_rawread_config8(dev, where); #endif }
- uint16_t pci_io_rawread_config16(device_t_raw dev, unsigned where) +u16 pci_io_rawread_config16(device_t_raw dev, unsigned where) { unsigned addr; -#if PCI_IO_CFG_EXT == 0 - addr = (dev>>4) | where; +#if CONFIG_PCI_IO_CFG_EXT == 0 + addr = (dev >> 4) | where; #else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); + addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16); #endif outl(0x80000000 | (addr & ~3), 0xCF8); return inw(0xCFC + (addr & 2)); }
-#if MMCONF_SUPPORT - uint16_t pci_mmio_rawread_config16(device_t_raw dev, unsigned where) +#if CONFIG_MMCONF_SUPPORT +u16 pci_mmio_rawread_config16(device_t_raw dev, unsigned where) { - unsigned addr; - addr = dev | where; - return read16x(addr); + unsigned addr; + addr = dev | where; + return read16x(addr); } #endif
- uint16_t pci_rawread_config16(device_t_raw dev, unsigned where) +u16 pci_rawread_config16(device_t_raw dev, unsigned where) { -#if MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT return pci_mmio_rawread_config16(dev, where); #else - return pci_io_rawread_config16(dev, where); + return pci_io_rawread_config16(dev, where); #endif }
- - uint32_t pci_io_rawread_config32(device_t_raw dev, unsigned where) +u32 pci_io_rawread_config32(device_t_raw dev, unsigned where) { unsigned addr; -#if PCI_IO_CFG_EXT == 0 - addr = (dev>>4) | where; +#if CONFIG_PCI_IO_CFG_EXT == 0 + addr = (dev >> 4) | where; #else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); + addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16); #endif outl(0x80000000 | (addr & ~3), 0xCF8); return inl(0xCFC); }
-#if MMCONF_SUPPORT - uint32_t pci_mmio_rawread_config32(device_t_raw dev, unsigned where) +#if CONFIG_MMCONF_SUPPORT +u32 pci_mmio_rawread_config32(device_t_raw dev, unsigned where) { - unsigned addr; - addr = dev | where; - return read32x(addr); + unsigned addr; + addr = dev | where; + return read32x(addr); } #endif
- uint32_t pci_rawread_config32(device_t_raw dev, unsigned where) +u32 pci_rawread_config32(device_t_raw dev, unsigned where) { -#if MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT return pci_mmio_rawread_config32(dev, where); #else - return pci_io_rawread_config32(dev, where); + return pci_io_rawread_config32(dev, where); #endif }
- void pci_io_rawwrite_config8(device_t_raw dev, unsigned where, uint8_t value) +void pci_io_rawwrite_config8(device_t_raw dev, unsigned where, u8 value) { unsigned addr; -#if PCI_IO_CFG_EXT == 0 - addr = (dev>>4) | where; +#if CONFIG_PCI_IO_CFG_EXT == 0 + addr = (dev >> 4) | where; #else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); + addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16); #endif outl(0x80000000 | (addr & ~3), 0xCF8); outb(value, 0xCFC + (addr & 3)); }
-#if MMCONF_SUPPORT - void pci_mmio_rawwrite_config8(device_t_raw dev, unsigned where, uint8_t value) +#if CONFIG_MMCONF_SUPPORT +void pci_mmio_rawwrite_config8(device_t_raw dev, unsigned where, u8 value) { - unsigned addr; - addr = dev | where; - write8x(addr, value); + unsigned addr; + addr = dev | where; + write8x(addr, value); } #endif
- void pci_rawwrite_config8(device_t_raw dev, unsigned where, uint8_t value) +void pci_rawwrite_config8(device_t_raw dev, unsigned where, u8 value) { -#if MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT pci_mmio_rawwrite_config8(dev, where, value); #else - pci_io_rawwrite_config8(dev, where, value); + pci_io_rawwrite_config8(dev, where, value); #endif }
- - void pci_io_rawwrite_config16(device_t_raw dev, unsigned where, uint16_t value) +void pci_io_rawwrite_config16(device_t_raw dev, unsigned where, u16 value) { - unsigned addr; -#if PCI_IO_CFG_EXT == 0 - addr = (dev>>4) | where; + unsigned addr; +#if CONFIG_PCI_IO_CFG_EXT == 0 + addr = (dev >> 4) | where; #else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); + addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16); #endif - outl(0x80000000 | (addr & ~3), 0xCF8); - outw(value, 0xCFC + (addr & 2)); + outl(0x80000000 | (addr & ~3), 0xCF8); + outw(value, 0xCFC + (addr & 2)); }
-#if MMCONF_SUPPORT - void pci_mmio_rawwrite_config16(device_t_raw dev, unsigned where, uint16_t value) +#if CONFIG_MMCONF_SUPPORT +void pci_mmio_rawwrite_config16(device_t_raw dev, unsigned where, + u16 value) { - unsigned addr; - addr = dev | where; - write16x(addr, value); + unsigned addr; + addr = dev | where; + write16x(addr, value); } #endif
- void pci_rawwrite_config16(device_t_raw dev, unsigned where, uint16_t value) +void pci_rawwrite_config16(device_t_raw dev, unsigned where, u16 value) { -#if MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT pci_mmio_rawwrite_config16(dev, where, value); #else pci_io_rawwrite_config16(dev, where, value); #endif }
- - void pci_io_rawwrite_config32(device_t_raw dev, unsigned where, uint32_t value) +void pci_io_rawwrite_config32(device_t_raw dev, unsigned where, u32 value) { unsigned addr; -#if PCI_IO_CFG_EXT == 0 - addr = (dev>>4) | where; +#if CONFIG_PCI_IO_CFG_EXT == 0 + addr = (dev >> 4) | where; #else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); + addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16); #endif outl(0x80000000 | (addr & ~3), 0xCF8); outl(value, 0xCFC); }
-#if MMCONF_SUPPORT - void pci_mmio_rawwrite_config32(device_t_raw dev, unsigned where, uint32_t value) +#if CONFIG_MMCONF_SUPPORT +void pci_mmio_rawwrite_config32(device_t_raw dev, unsigned where, + u32 value) { - unsigned addr; - addr = dev | where; - write32x(addr, value); + unsigned addr; + addr = dev | where; + write32x(addr, value); } #endif
- void pci_rawwrite_config32(device_t_raw dev, unsigned where, uint32_t value) +void pci_rawwrite_config32(device_t_raw dev, unsigned where, u32 value) { -#if MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT pci_mmio_rawwrite_config32(dev, where, value); #else - pci_io_rawwrite_config32(dev, where, value); + pci_io_rawwrite_config32(dev, where, value); #endif }
- -void pci_rawmodify_config8(device_t_raw dev, unsigned where, u8 orval,u8 mask) -{ u8 data=pci_rawread_config8(dev,where); - data&=(~mask); - data|=orval; - pci_rawwrite_config8(dev,where,data); +void pci_rawmodify_config8(device_t_raw dev, unsigned where, u8 orval, u8 mask) +{ + u8 data = pci_rawread_config8(dev, where); + data &= (~mask); + data |= orval; + pci_rawwrite_config8(dev, where, data); } -void pci_rawmodify_config16(device_t_raw dev, unsigned where, uint16_t orval,uint16_t mask) -{ uint16_t data=pci_rawread_config16(dev,where); - data&=(~mask); - data|=orval; - pci_rawwrite_config16(dev,where,data); + +void pci_rawmodify_config16(device_t_raw dev, unsigned where, u16 orval, u16 mask) +{ + u16 data = pci_rawread_config16(dev, where); + data &= (~mask); + data |= orval; + pci_rawwrite_config16(dev, where, data); } -void pci_rawmodify_config32(device_t_raw dev, unsigned where, uint32_t orval,uint32_t mask) -{ uint32_t data=pci_rawread_config32(dev,where); - data&=(~mask); - data|=orval; - pci_rawwrite_config32(dev,where,data); + +void pci_rawmodify_config32(device_t_raw dev, unsigned where, u32 orval, u32 mask) +{ + u32 data = pci_rawread_config32(dev, where); + data &= (~mask); + data |= orval; + pci_rawwrite_config32(dev, where, data); }
-void io_rawmodify_config8(u16 where, uint8_t orval,uint8_t mask) +void io_rawmodify_config8(u16 where, u8 orval, u8 mask) { - u8 data=inb(where); - data&=(~mask); - data|=orval; - outb(data,where); + u8 data = inb(where); + data &= (~mask); + data |= orval; + outb(data, where); }
-void via_pci_inittable(u8 chipversion,struct VIA_PCI_REG_INIT_TABLE* initdata) +void via_pci_inittable(u8 chipversion, + struct VIA_PCI_REG_INIT_TABLE *initdata) { - u8 i=0; + u8 i = 0; device_t_raw devbxdxfx; - for(i=0;;i++) { - if((initdata[i].Mask==0)&&(initdata[i].Value==0)&&(initdata[i].Bus==0)&&(initdata[i].ChipRevisionEnd==0xff)&&(initdata[i].ChipRevisionStart==0)&&(initdata[i].Device==0)&&(initdata[i].Function==0)&&(initdata[i].Register==0)) - break; - if((chipversion>=initdata[i].ChipRevisionStart)&&(chipversion<=initdata[i].ChipRevisionEnd)){ - devbxdxfx=PCI_RAWDEV(initdata[i].Bus,initdata[i].Device,initdata[i].Function); - pci_rawmodify_config8(devbxdxfx, initdata[i].Register,initdata[i].Value,initdata[i].Mask); - } + for (i = 0;; i++) { + if ((initdata[i].Mask == 0) && (initdata[i].Value == 0) + && (initdata[i].Bus == 0) + && (initdata[i].ChipRevisionEnd == 0xff) + && (initdata[i].ChipRevisionStart == 0) + && (initdata[i].Device == 0) + && (initdata[i].Function == 0) + && (initdata[i].Register == 0)) + break; + if ((chipversion >= initdata[i].ChipRevisionStart) + && (chipversion <= initdata[i].ChipRevisionEnd)) { + devbxdxfx = + PCI_RAWDEV(initdata[i].Bus, initdata[i].Device, + initdata[i].Function); + pci_rawmodify_config8(devbxdxfx, + initdata[i].Register, + initdata[i].Value, + initdata[i].Mask); + } } } #endif
Modified: trunk/src/northbridge/via/vx800/vx800_ide.c ============================================================================== --- trunk/src/northbridge/via/vx800/vx800_ide.c Wed Apr 7 17:32:52 2010 (r5371) +++ trunk/src/northbridge/via/vx800/vx800_ide.c Wed Apr 7 17:40:26 2010 (r5372) @@ -26,7 +26,7 @@ #include <arch/io.h> #include "vx800.h"
-static const idedevicepcitable[16 * 12] = { +static const u8 idedevicepcitable[16 * 12] = { /* 0x02, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x00, 0x00, 0xA8, 0xA8, 0xF0, 0x00, 0x00, 0xB6,
Modified: trunk/src/northbridge/via/vx800/vx800_lpc.c ============================================================================== --- trunk/src/northbridge/via/vx800/vx800_lpc.c Wed Apr 7 17:32:52 2010 (r5371) +++ trunk/src/northbridge/via/vx800/vx800_lpc.c Wed Apr 7 17:40:26 2010 (r5372) @@ -104,7 +104,7 @@ printk(BIOS_SPEW, "%s: DONE\n", __FUNCTION__); }
-void setup_pm(device_t dev) +static void setup_pm(device_t dev) { u16 tmp; /* Debounce LID and PWRBTN# Inputs for 16ms. */ @@ -198,7 +198,7 @@ */ }
-void S3_ps2_kb_ms_wakeup(struct device *dev) +static void S3_ps2_kb_ms_wakeup(struct device *dev) { u8 enables; enables = pci_read_config8(dev, 0x51); @@ -222,12 +222,12 @@
}
-void S3_usb_wakeup(struct device *dev) +static void S3_usb_wakeup(struct device *dev) { outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x4000, VX800_ACPI_IO_BASE + 0x22); //SCI on USB PME }
-void S3_lid_wakeup(struct device *dev) +static void S3_lid_wakeup(struct device *dev) { outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x800, VX800_ACPI_IO_BASE + 0x22); //SCI on LID PME } @@ -301,7 +301,7 @@
/* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this device has a resource to set - so set a dummy one */ -void vx800_read_resources(device_t dev) +static void vx800_read_resources(device_t dev) {
struct resource *resource; @@ -312,10 +312,9 @@ IORESOURCE_STORED; resource->size = 2; resource->base = 0x2e; - }
-void vx800_set_resources(device_t dev) +static void vx800_set_resources(device_t dev) { struct resource *resource; resource = find_resource(dev, 1); @@ -323,7 +322,7 @@ pci_dev_set_resources(dev); }
-void vx800_enable_resources(device_t dev) +static void vx800_enable_resources(device_t dev) { /* vx800 is not a pci bridge and has no resources of its own (other than standard PC i/o addresses). however it does control the isa bus and so
-
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