potentially wrong uses of ifdef/if defined - coreboot

18 Apr 2011


      Hi
as you probably know, we are using a slightly modified Kconfig that 
emits #define CONFIG_FOO 0 for all unset bools in our Kconfig files in 
order to avoid nasty checks a la
#if defined(CONFIG_FOO) && CONFIG_FOO
However, this modification to Kconfig was incomplete, and so only some 
but not all config defines got set correctly.
I fixed this bug in r6511 but unfortunately there is a whole lot of code 
that still uses the old method, sometimes assuming that a value has been 
set in Kconfig by checking
#if defined(CONFIG_FOO)
These cases will cause the preprocessor to make the wrong choice and 
compile the code in, even though the variable is not set in Kconfig.
So I did a quick grep over the source code to determine our usage of 
ifdef, ifndef and if defined.
All these occurences might need fixing, but certainly not all of them do.
Can someone help with going through these and figuring out which ones 
need changing and which ones don't?
Any help is highly appreciated.
Example 1:
#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && 
CONFIG_PCI_OPTION_ROM_RUN_YABEL
can be written as
#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
Example 2:
#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL
needs to be written as
#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
Example 3:
#ifndef CONFIG_TTYS0_BASE
is not a bool value, and hence does not have to be changed.
Here's the list:
./src/arch/x86/include/bootblock_common.h:#ifdef CONFIG_BOOTBLOCK_CPU_INIT
./src/arch/x86/include/bootblock_common.h:#ifdef 
CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
./src/arch/x86/include/bootblock_common.h:#ifdef 
CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
./src/devices/oprom/x86emu/debug.h:#ifdef CONFIG_DEFAULT_CONSOLE_LOGLEVEL
./src/devices/oprom/yabel/compat/functions.c:#ifdef 
CONFIG_YABEL_VIRTMEM_LOCATION
./src/devices/oprom/yabel/device.c:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL
./src/devices/oprom/yabel/device.c:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL
./src/devices/oprom/yabel/device.h:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL
./src/devices/oprom/yabel/device.h:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL
./src/devices/oprom/yabel/interrupt.c:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL
./src/devices/oprom/yabel/interrupt.c:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL
./src/devices/oprom/yabel/interrupt.c:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL
./src/devices/oprom/yabel/interrupt.c:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL
./src/devices/oprom/yabel/interrupt.c:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL
./src/devices/oprom/yabel/interrupt.c:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL
./src/devices/oprom/yabel/interrupt.c:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL
./src/devices/oprom/yabel/io.c:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL
./src/devices/oprom/yabel/io.c:#ifdef CONFIG_ARCH_X86
./src/devices/oprom/yabel/io.c:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL
./src/devices/oprom/yabel/io.c:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL
./src/devices/oprom/yabel/mem.c:#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL
./src/devices/pciexp_device.c:#ifdef CONFIG_PCIE_TUNING
./src/devices/pciexp_device.c:#ifdef CONFIG_PCIE_TUNING
./src/drivers/ati/ragexl/atyfb.h:#ifdef CONFIG_PMAC_PBOOK
./src/lib/jpeg.c:#ifdef CONFIG_PPC
./src/northbridge/via/cn700/raminit.c:#ifdef CONFIG_DEBUG_RAM_SETUP
./src/northbridge/via/vx800/early_smbus.c:#ifdef CONFIG_DEBUG_SMBUS
./src/pc80/i8254.c:#ifdef CONFIG_UDELAY_TIMER2
./src/southbridge/amd/sb700/early_setup.c:#ifdef 
CONFIG_SOUTHBRIDGE_AMD_SP5100
./src/southbridge/amd/sb700/early_setup.c:#ifdef 
CONFIG_SOUTHBRIDGE_AMD_SP5100
./src/southbridge/amd/sb700/early_setup.c:#ifdef 
CONFIG_SOUTHBRIDGE_AMD_SP5100
./src/southbridge/amd/sb700/early_setup.c:#ifdef 
CONFIG_SOUTHBRIDGE_AMD_SP5100
./src/southbridge/amd/sb700/lpc.c:#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100
./src/southbridge/amd/sb700/sata.c:#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100
./src/arch/x86/include/arch/pirq_routing.h:#ifndef CONFIG_IRQ_SLOT_COUNT
./src/boot/selfboot.c:#ifndef CONFIG_BIG_ENDIAN
./src/cpu/amd/model_gx2/syspreinit.c:#ifndef CONFIG_CACHE_AS_RAM
./src/cpu/amd/model_lx/syspreinit.c:#ifndef CONFIG_CACHE_AS_RAM
./src/cpu/x86/mtrr/mtrr.c:#ifndef CONFIG_VAR_MTRR_HOLE
./src/devices/oprom/yabel/device.c:#ifndef CONFIG_PCI_OPTION_ROM_RUN_YABEL
./src/devices/oprom/yabel/device.c:#ifndef CONFIG_PCI_OPTION_ROM_RUN_YABEL
./src/devices/oprom/yabel/device.c:#ifndef CONFIG_PCI_OPTION_ROM_RUN_YABEL
./src/devices/oprom/yabel/device.c:#ifndef CONFIG_PCI_OPTION_ROM_RUN_YABEL
./src/include/uart8250.h:#ifndef CONFIG_TTYS0_BASE
./src/include/uart8250.h:#ifndef CONFIG_TTYS0_BAUD
./src/include/uart8250.h:#ifndef CONFIG_TTYS0_DIV
./src/include/uart8250.h:#ifndef CONFIG_TTYS0_LCS
./src/lib/version.c:#ifndef CONFIG_MAINBOARD_VENDOR
./src/lib/version.c:#ifndef CONFIG_MAINBOARD_PART_NUMBER
./src/northbridge/amd/amdk8/coherent_ht.c:#ifndef 
CONFIG_K8_HT_FREQ_1G_SUPPORT
./src/northbridge/amd/amdk8/coherent_ht.c:#ifndef 
CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
./src/northbridge/amd/amdk8/coherent_ht.c:#ifndef CONFIG_ENABLE_APIC_EXT_ID
./src/pc80/mc146818rtc_early.c:#ifndef CONFIG_MAX_REBOOT_CNT
./src/southbridge/amd/amd8111/acpi.c:#ifndef 
CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
./src/southbridge/amd/cimx_wrapper/sb800/bootblock.c:#ifndef 
CONFIG_TTYS0_DIV
./src/southbridge/amd/rs780/early_setup.c:#ifndef 
CONFIG_NORTHBRIDGE_AMD_AMDFAM10
./src/southbridge/amd/sb600/sm.c:#ifndef 
CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
./src/southbridge/amd/sb700/sm.c:#ifndef 
CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
./src/southbridge/amd/sb800/sm.c:#ifndef 
CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
./src/southbridge/intel/esb6300/lpc.c:#ifndef 
CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
./src/southbridge/intel/i3100/lpc.c:#ifndef 
CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
./src/southbridge/intel/i82801cx/lpc.c:#ifndef 
CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
./src/southbridge/intel/i82801dx/i82801dx.h:#ifndef 
CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
./src/southbridge/intel/i82801ex/lpc.c:#ifndef 
CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
./src/southbridge/intel/i82801gx/i82801gx.h:#ifndef 
CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
./src/southbridge/nvidia/ck804/lpc.c:#ifndef 
CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
./src/southbridge/nvidia/mcp55/lpc.c:#ifndef 
CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
./src/southbridge/sis/sis966/lpc.c:#ifndef 
CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
./src/southbridge/via/vt8237r/vt8237r.h:#ifndef 
CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
./src/arch/x86/boot/coreboot_table.c:#if defined(CONFIG_BOOTSPLASH) && 
CONFIG_BOOTSPLASH && CONFIG_COREBOOT_KEEP_FRAMEBUFFER
./src/arch/x86/include/arch/interrupt.h:#if 
defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && 
CONFIG_PCI_OPTION_ROM_RUN_REALMODE
./src/arch/x86/include/bootblock_common.h: 
(defined(CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT) || 
defined(CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT))
./src/arch/x86/lib/exception.c:#if defined(CONFIG_GDB_STUB) && 
CONFIG_GDB_STUB == 1
./src/arch/x86/lib/ioapic.c:#if defined(CONFIG_EPIA_VT8237R_INIT) && 
CONFIG_EPIA_VT8237R_INIT
./src/console/post.c:#if !defined(CONFIG_NO_POST) || CONFIG_NO_POST==0
./src/cpu/amd/car/cache_as_ram.inc:#if defined(CONFIG_XIP_ROM_SIZE) && 
defined(CONFIG_XIP_ROM_BASE)
./src/cpu/amd/car/cache_as_ram.inc:#if defined(CONFIG_TINY_BOOTBLOCK) && 
CONFIG_TINY_BOOTBLOCK
./src/cpu/intel/car/cache_as_ram.inc:#if defined(CONFIG_XIP_ROM_SIZE) && 
defined(CONFIG_XIP_ROM_BASE)
./src/cpu/intel/car/cache_as_ram.inc:#if defined(CONFIG_TINY_BOOTBLOCK) 
&& CONFIG_TINY_BOOTBLOCK
./src/cpu/intel/model_106cx/cache_as_ram.inc:#if 
defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
./src/cpu/intel/model_106cx/cache_as_ram.inc:#if 
defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
./src/cpu/intel/model_106cx/cache_as_ram.inc:#if 
defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
./src/cpu/intel/model_6ex/cache_as_ram.inc:#if 
defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
./src/cpu/intel/model_6ex/cache_as_ram.inc:#if 
defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
./src/cpu/intel/model_6ex/cache_as_ram.inc:#if defined(CONFIG_USBDEBUG) 
&& (CONFIG_USBDEBUG == 1)
./src/cpu/intel/model_6fx/cache_as_ram.inc:#if 
defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
./src/cpu/intel/model_6fx/cache_as_ram.inc:#if 
defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
./src/cpu/intel/model_6fx/cache_as_ram.inc:#if defined(CONFIG_USBDEBUG) 
&& (CONFIG_USBDEBUG == 1)
./src/cpu/via/car/cache_as_ram.inc:#if defined(CONFIG_TINY_BOOTBLOCK) && 
CONFIG_TINY_BOOTBLOCK
./src/cpu/x86/lapic/lapic_cpu_init.c:#if !defined 
(CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX)
./src/cpu/x86/lapic/lapic_cpu_init.c:#if !defined 
(CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX)
./src/cpu/x86/mtrr/earlymtrr.c:#if !defined(CONFIG_CACHE_AS_RAM) || 
(CONFIG_CACHE_AS_RAM == 0)
./src/cpu/x86/mtrr/earlymtrr.c:#if defined(CONFIG_XIP_ROM_SIZE)
./src/devices/oprom/x86.c:#if defined(CONFIG_GEODE_VSA) && CONFIG_GEODE_VSA
./src/devices/oprom/yabel/biosemu.c:#if defined(CONFIG_X86EMU_DEBUG_JMP) 
&& CONFIG_X86EMU_DEBUG_JMP
./src/devices/oprom/yabel/biosemu.c:#if 
defined(CONFIG_X86EMU_DEBUG_TRACE) && CONFIG_X86EMU_DEBUG_TRACE
./src/devices/oprom/yabel/biosemu.c:#if defined(CONFIG_X86EMU_DEBUG_PNP) 
&& CONFIG_X86EMU_DEBUG_PNP
./src/devices/oprom/yabel/biosemu.c:#if 
defined(CONFIG_X86EMU_DEBUG_DISK) && CONFIG_X86EMU_DEBUG_DISK
./src/devices/oprom/yabel/biosemu.c:#if defined(CONFIG_X86EMU_DEBUG_PMM) 
&& CONFIG_X86EMU_DEBUG_PMM
./src/devices/oprom/yabel/biosemu.c:#if defined(CONFIG_X86EMU_DEBUG_VBE) 
&& CONFIG_X86EMU_DEBUG_VBE
./src/devices/oprom/yabel/biosemu.c:#if 
defined(CONFIG_X86EMU_DEBUG_INT10) && CONFIG_X86EMU_DEBUG_INT10
./src/devices/oprom/yabel/biosemu.c:#if 
defined(CONFIG_X86EMU_DEBUG_INTERRUPTS) && CONFIG_X86EMU_DEBUG_INTERRUPTS
./src/devices/oprom/yabel/biosemu.c:#if 
defined(CONFIG_X86EMU_DEBUG_CHECK_VMEM_ACCESS) && 
CONFIG_X86EMU_DEBUG_CHECK_VMEM_ACCESS
./src/devices/oprom/yabel/biosemu.c:#if defined(CONFIG_X86EMU_DEBUG_MEM) 
&& CONFIG_X86EMU_DEBUG_MEM
./src/devices/oprom/yabel/biosemu.c:#if defined(CONFIG_X86EMU_DEBUG_IO) 
&& CONFIG_X86EMU_DEBUG_IO
./src/devices/oprom/yabel/biosemu.c:#if defined(CONFIG_X86EMU_DEBUG) && 
CONFIG_X86EMU_DEBUG
./src/devices/oprom/yabel/compat/functions.c:#if 
!defined(CONFIG_YABEL_DIRECTHW) || (!CONFIG_YABEL_DIRECTHW)
./src/devices/oprom/yabel/debug.h:#if defined(CONFIG_X86EMU_DEBUG) && 
CONFIG_X86EMU_DEBUG
./src/devices/oprom/yabel/device.c:#if defined(CONFIG_X86EMU_DEBUG) && 
CONFIG_X86EMU_DEBUG
./src/devices/oprom/yabel/device.c:#if defined(CONFIG_X86EMU_DEBUG) && 
CONFIG_X86EMU_DEBUG
./src/devices/oprom/yabel/device.c:#if defined(CONFIG_X86EMU_DEBUG) && 
CONFIG_X86EMU_DEBUG
./src/devices/oprom/yabel/interrupt.c:#if 
defined(CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES) && 
CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES==1
./src/devices/oprom/yabel/interrupt.c:#if 
defined(CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES) && 
CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES==1
./src/devices/oprom/yabel/io.c:#if defined(CONFIG_YABEL_DIRECTHW) && 
(CONFIG_YABEL_DIRECTHW == 1)
./src/devices/oprom/yabel/io.c:#if 
defined(CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES) && 
CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES==1
./src/devices/oprom/yabel/mem.c:#if !defined(CONFIG_YABEL_DIRECTHW) || 
(!CONFIG_YABEL_DIRECTHW)
./src/devices/pci_rom.c:#if defined(CONFIG_BOARD_EMULATION_QEMU_X86) && 
CONFIG_BOARD_EMULATION_QEMU_X86
./src/include/assert.h:#if defined(__PRE_RAM__) && !CONFIG_CACHE_AS_RAM
./src/include/cpu/cpu.h:#if !defined(CONFIG_WAIT_BEFORE_CPUS_INIT) || 
CONFIG_WAIT_BEFORE_CPUS_INIT==0
./src/include/cpu/x86/mtrr.h:#if defined(CONFIG_XIP_ROM_SIZE) && 
!defined(CONFIG_XIP_ROM_BASE)
./src/include/cpu/x86/mtrr.h:#if defined(CONFIG_XIP_ROM_BASE) && 
!defined(CONFIG_XIP_ROM_SIZE)
./src/include/cpu/x86/mtrr.h:#if !defined(CONFIG_RAMTOP)
./src/include/cpu/x86/mtrr.h:# error "CONFIG_RAMTOP not defined"
./src/include/cpu/x86/mtrr.h:#if defined(CONFIG_XIP_ROM_SIZE) && 
((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
./src/include/cpu/x86/mtrr.h:#if defined(CONFIG_XIP_ROM_SIZE) && 
((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0)
./src/include/cpu/x86/mtrr.h:#if defined(CONFIG_XIP_ROM_SIZE)
./src/include/cpu/x86/mtrr.h:# if defined(CONFIG_TINY_BOOTBLOCK) && 
CONFIG_TINY_BOOTBLOCK
./src/include/lib.h:#if defined(CONFIG_CPU_AMD_LX) && CONFIG_CPU_AMD_LX
./src/lib/fallback_boot.c:#if defined(CONFIG_BOOTSPLASH) && 
CONFIG_BOOTSPLASH && !CONFIG_COREBOOT_KEEP_FRAMEBUFFER
./src/lib/uart8250.c:#if CONFIG_USE_OPTION_TABLE && !defined(__SMM__)
./src/lib/version.c:#error CONFIG_MAINBOARD_VENDOR not defined
./src/lib/version.c:#error  CONFIG_MAINBOARD_PART_NUMBER not defined
./src/mainboard/kontron/986lcd-m/mainboard.c:#if 
defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
./src/mainboard/kontron/986lcd-m/mainboard.c:#if 
defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
./src/mainboard/kontron/986lcd-m/mainboard.c:#if 
defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
./src/northbridge/amd/amdk8/f.h:#if ((CONFIG_MEM_TRAIN_SEQ != 1) && 
defined(__PRE_RAM__)) || \
./src/northbridge/amd/amdk8/f.h:    ((CONFIG_MEM_TRAIN_SEQ == 1) && 
!defined(__PRE_RAM__))
./src/northbridge/amd/amdk8/raminit.h:#if defined(__PRE_RAM__) && 
CONFIG_RAMINIT_SYSINFO
./src/northbridge/amd/amdk8/raminit_f.c:#if 
!defined(CONFIG_INTERLEAVE_CHIP_SELECTS) || 
(CONFIG_INTERLEAVE_CHIP_SELECTS == 0)
./src/northbridge/amd/amdk8/raminit_f.c:#if defined(CONFIG_MAX_MEM_CLOCK)
./src/northbridge/amd/amdk8/raminit_f.c:#if defined(CONFIG_ECC_MEMORY) 
&& (CONFIG_ECC_MEMORY == 0)
./src/northbridge/intel/i82830/smihandler.c:#if 
defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && 
CONFIG_PCI_OPTION_ROM_RUN_YABEL && !CONFIG_YABEL_DIRECTHW
./src/northbridge/intel/i82830/vga.c:#if 
defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
./src/northbridge/intel/i82830/vga.c:#if 
defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
./src/northbridge/intel/i945/raminit.c:#if 
defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
./src/northbridge/intel/i945/raminit.c:#if 
defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
./src/northbridge/intel/i945/raminit.c:#elif 
defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
./src/northbridge/intel/i945/raminit.c:#if 
defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
./src/northbridge/intel/i945/raminit.c:#elif 
defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
./src/northbridge/intel/i945/raminit.c:#if 
defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
./src/northbridge/intel/i945/raminit.c:#elif 
defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
./src/northbridge/intel/i945/raminit.c:#if 
defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
./src/northbridge/intel/i945/raminit.c:#elif 
defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
./src/southbridge/ti/pci1x2x/pci1x2x.c:#if 
(!defined(CONFIG_TI_PCMCIA_CARDBUS_CMDR) || \
./src/southbridge/ti/pci1x2x/pci1x2x.c:     
!defined(CONFIG_TI_PCMCIA_CARDBUS_CLSR) || \
./src/southbridge/ti/pci1x2x/pci1x2x.c:     
!defined(CONFIG_TI_PCMCIA_CARDBUS_CLTR) || \
./src/southbridge/ti/pci1x2x/pci1x2x.c:     
!defined(CONFIG_TI_PCMCIA_CARDBUS_BCR) || \
./src/southbridge/ti/pci1x2x/pci1x2x.c:     
!defined(CONFIG_TI_PCMCIA_CARDBUS_SCR) || \
./src/southbridge/ti/pci1x2x/pci1x2x.c:     
!defined(CONFIG_TI_PCMCIA_CARDBUS_MRR))
./src/southbridge/via/k8t890/early_car.c:#if 
defined(CONFIG_SOUTHBRIDGE_VIA_K8M800)
./src/southbridge/via/k8t890/early_car.c:#elif 
defined(CONFIG_SOUTHBRIDGE_VIA_K8T800)
./src/southbridge/via/k8t890/early_car.c:#elif 
defined(CONFIG_SOUTHBRIDGE_VIA_K8T800PRO)
./src/southbridge/via/k8t890/early_car.c:#elif 
defined(CONFIG_SOUTHBRIDGE_VIA_K8M890)
./src/southbridge/via/k8t890/early_car.c:#elif 
defined(CONFIG_SOUTHBRIDGE_VIA_K8T890)
./src/southbridge/via/vt8237r/lpc.c:  #if 
defined(CONFIG_SOUTHBRIDGE_VIA_K8T800)
./src/superio/ite/it8716f/it8716f.h:#if 
defined(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) && 
CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
./src/superio/ite/it8716f/superio.c:#if 
!defined(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) || 
!CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL