Asus M2A-VM

[Carl-Daniel Hailfinger]

Hi all,

my Asus M2A-VM (690G/SB600) is working and boots to memtest and FILO.

Memtest works fine over serial (well, I only ran memtest until it
reached 15%).
FILO can load the kernel, but I didn't have time to enable serial output
for my kernel.

Thanks to Zheng Bao for adding support for my 690G graphics.

I'll post a patch soon. Right now, there are a few more bugs to fix. The
ncHT fixup is already known, a clean patch will come tomorrow.

On a first boot, I get an endless loop of

drive detection fail,trying...

until I press the reset button. After that, it boots fine. That message
is in the SB600 code. I will enable some debugging that was disabled in
revision 3785.

Another curiosity is that my power button has become ineffective. It
simply initiates a reboot instead of switching off the machine after 4
seconds. That happens only with the FILO payload.

Regards,
Carl-Daniel

[Carl-Daniel Hailfinger]

On 17.12.2008 04:39, Carl-Daniel Hailfinger wrote:
> Hi all,
>
> my Asus M2A-VM (690G/SB600) is working and boots to memtest and FILO.
>
> Memtest works fine over serial (well, I only ran memtest until it
> reached 15%).
> FILO can load the kernel, but I didn't have time to enable serial output
> for my kernel.
>
> Thanks to Zheng Bao for adding support for my 690G graphics.
>
> I'll post a patch soon. Right now, there are a few more bugs to fix. The
> ncHT fixup is already known, a clean patch will come tomorrow.
>
> On a first boot, I get an endless loop of
>
> drive detection fail,trying...
>
> until I press the reset button. After that, it boots fine. That message
> is in the SB600 code. I will enable some debugging that was disabled in
> revision 3785.
>
> Another curiosity is that my power button has become ineffective. It
> simply initiates a reboot instead of switching off the machine after 4
> seconds. That happens only with the FILO payload.

Oh, and it does not find more than 2 GB of RAM. I'll try to debug that
as well.

Right now, I'm happy that it gets to FILO and can load a kernel.

The interrupts are probably wrong. I need to check that.

Regards,
Carl-Daniel

[Peter Stuge]

Carl-Daniel Hailfinger wrote:
> my Asus M2A-VM (690G/SB600) is working and boots to memtest and FILO.

Nice progress! Looking forward to hearing more.

//Peter

[Carl-Daniel Hailfinger]

On 17.12.2008 16:11, Peter Stuge wrote:
> Carl-Daniel Hailfinger wrote:
> > my Asus M2A-VM (690G/SB600) is working and boots to memtest and FILO.
>
> Nice progress! Looking forward to hearing more.

The kernel hangs on SATA detection. That's expected, though, because
SATA setup is incomplete (only first port) and does not take care of
quirks of early revisions. I have a patch to set up all 4 SATA ports,
but the quirk fixups still need to be implemented.
And I'm hitting slightly unexpected behaviour during SATA PHY setup.
I'll give more info once I have access to my logs again.

Regards,
Carl-Daniel

[Bao, Zheng]

....
Adjust rom_table_end from 0x000f34d0 to 0x00100000
uma_memory_start=0x78000000, uma_memory_size=0x8000000 Wrote coreboot
table at: 00000530 - 00000778  checksum 5730 ..

Based on your bootlog, coreboot correctly detects your memory
size(uma_memory_start+ uma_memory_size). When does it report 2G memory?

Zheng

-----Original Message-----
From: [e-mail]
[mailto:[e-mail]] On Behalf Of Carl-Daniel
Hailfinger
Sent: Wednesday, December 17, 2008 12:14 PM
To: Coreboot
Subject: Re: [coreboot] Asus M2A-VM

On 17.12.2008 04:39, Carl-Daniel Hailfinger wrote:
> Hi all,
>
> my Asus M2A-VM (690G/SB600) is working and boots to memtest and FILO.
>
> Memtest works fine over serial (well, I only ran memtest until it
> reached 15%).
> FILO can load the kernel, but I didn't have time to enable serial

output
> for my kernel.
>
> Thanks to Zheng Bao for adding support for my 690G graphics.
>
> I'll post a patch soon. Right now, there are a few more bugs to fix.

The
> ncHT fixup is already known, a clean patch will come tomorrow.
>
> On a first boot, I get an endless loop of
>
> drive detection fail,trying...
>
> until I press the reset button. After that, it boots fine. That

message
> is in the SB600 code. I will enable some debugging that was disabled

in
> revision 3785.
>
> Another curiosity is that my power button has become ineffective. It
> simply initiates a reboot instead of switching off the machine after 4
> seconds. That happens only with the FILO payload.

Oh, and it does not find more than 2 GB of RAM. I'll try to debug that
as well.

Right now, I'm happy that it gets to FILO and can load a kernel.

The interrupts are probably wrong. I need to check that.

Regards,
Carl-Daniel

[Bao, Zheng]

I traced back coreboot_table.c.

I replace the add_mainboard_resources() with it used to be, that is,
lb_add_memory_range(). Then the e820 is right and SATA DMA also works .
I really don't know why it happens. I will keep dig it. If you guys have
any idea, please let us know.

Zheng

-----Original Message-----
From: [e-mail]
[mailto:[e-mail]] On Behalf Of Carl-Daniel
Hailfinger
Sent: Thursday, December 18, 2008 12:02 AM
To: Coreboot
Subject: Re: [coreboot] Asus M2A-VM

On 17.12.2008 16:11, Peter Stuge wrote:
> Carl-Daniel Hailfinger wrote:
> > my Asus M2A-VM (690G/SB600) is working and boots to memtest and FILO.
>
> Nice progress! Looking forward to hearing more.

The kernel hangs on SATA detection. That's expected, though, because
SATA setup is incomplete (only first port) and does not take care of
quirks of early revisions. I have a patch to set up all 4 SATA ports,
but the quirk fixups still need to be implemented.
And I'm hitting slightly unexpected behaviour during SATA PHY setup.
I'll give more info once I have access to my logs again.

Regards,
Carl-Daniel

Asus M2A-VM (patch for this issue)

[Bao, Zheng]

The prototype of lb_add_memory_range is
    void lb_add_memory_range(struct lb_memory *mem,
       uint32_t type, uint64_t start, uint64_t size),
whose 3rd and 4th arguments are 64bits ones. When the gcc meets this
function, it has no idea about the arguments. Sometimes it assumes they
are 32bits ones. When the linker starts to play her role, there are not
enough spaces for 2 64bits arguments. Then the tables are not correct.
Then the DMA of SATA doesn't know the spaces is reserved. Then ...

some trailing white spaces are also deleted.

This patch doesn't seem to be a long term one. Each board that has its
own memory settings should add this. If you guys have a better way to
declare the prototype, please feel free to replace it.

Zheng

Signed-off-by: Zheng Bao

Index: src/mainboard/amd/pistachio/mainboard.c
===================================================================
--- src/mainboard/amd/pistachio/mainboard.c	(revision 237)
+++ src/mainboard/amd/pistachio/mainboard.c	(working copy)
@@ -324,15 +324,18 @@
    set_thermal_config();
 }

-int add_mainboard_resources(struct lb_memory *mem)
+extern void lb_add_memory_range(struct lb_memory *mem,
+	uint32_t type, uint64_t start, uint64_t size);
+
+void add_mainboard_resources(struct lb_memory *mem)
 {
    /* UMA is removed from system memory in the northbridge code,
but
     * in some circumstances we want the memory mentioned as
reserved.
     */
-#if (CONFIG_GFXUMA == 1) 
-	printk_info("uma_memory_start=0x%x, uma_memory_size=0x%x \n", 
+#if (CONFIG_GFXUMA == 1)
+	printk_info("uma_memory_start=0x%x, uma_memory_size=0x%x \n",
    uma_memory_start, uma_memory_size);
-	lb_add_memory_range(mem, LB_MEM_RESERVED, 
+	lb_add_memory_range(mem, LB_MEM_RESERVED,
    	uma_memory_start, uma_memory_size);
 #endif
 }
Index: src/mainboard/amd/dbm690t/mainboard.c
===================================================================
--- src/mainboard/amd/dbm690t/mainboard.c	(revision 237)
+++ src/mainboard/amd/dbm690t/mainboard.c	(working copy)
@@ -243,16 +243,19 @@
    get_ide_dma66();
    set_thermal_config();
 }
- 
-int add_mainboard_resources(struct lb_memory *mem)
+
+extern void lb_add_memory_range(struct lb_memory *mem,
+	uint32_t type, uint64_t start, uint64_t size);
+
+void add_mainboard_resources(struct lb_memory *mem)
 {
    /* UMA is removed from system memory in the northbridge code,
but
     * in some circumstances we want the memory mentioned as
reserved.
     */
-#if (CONFIG_GFXUMA == 1) 
-	printk_info("uma_memory_start=0x%x, uma_memory_size=0x%x \n", 
+#if (CONFIG_GFXUMA == 1)
+	printk_info("uma_memory_start=0x%x, uma_memory_size=0x%x \n",
    uma_memory_start, uma_memory_size);
-	lb_add_memory_range(mem, LB_MEM_RESERVED, 
+	lb_add_memory_range(mem, LB_MEM_RESERVED,
    	uma_memory_start, uma_memory_size);
 #endif
 }

-----Original Message-----
From: [e-mail]
[mailto:[e-mail]] On Behalf Of Bao, Zheng
Sent: Thursday, December 18, 2008 1:18 PM
To: Carl-Daniel Hailfinger; Coreboot
Subject: Re: [coreboot] Asus M2A-VM

I traced back coreboot_table.c.

I replace the add_mainboard_resources() with it used to be, that is,
lb_add_memory_range(). Then the e820 is right and SATA DMA also works .
I really don't know why it happens. I will keep dig it. If you guys have
any idea, please let us know.

Zheng

-----Original Message-----
From: [e-mail]
[mailto:[e-mail]] On Behalf Of Carl-Daniel
Hailfinger
Sent: Thursday, December 18, 2008 12:02 AM
To: Coreboot
Subject: Re: [coreboot] Asus M2A-VM

On 17.12.2008 16:11, Peter Stuge wrote:
> Carl-Daniel Hailfinger wrote:
> > my Asus M2A-VM (690G/SB600) is working and boots to memtest and FILO.
>
> Nice progress! Looking forward to hearing more.

The kernel hangs on SATA detection. That's expected, though, because
SATA setup is incomplete (only first port) and does not take care of
quirks of early revisions. I have a patch to set up all 4 SATA ports,
but the quirk fixups still need to be implemented.
And I'm hitting slightly unexpected behaviour during SATA PHY setup.
I'll give more info once I have access to my logs again.

Regards,
Carl-Daniel

Asus M2A-VM (patch for this issue)

[Bao, Zheng]

If the previous patch is adopted, we also need to change the return
value of add_mainboard_resources.

Do we?

Zheng

Index: src/arch/i386/boot/coreboot_table.h
===================================================================
--- src/arch/i386/boot/coreboot_table.h	(revision 237)
+++ src/arch/i386/boot/coreboot_table.h	(working copy)
@@ -27,6 +27,6 @@
 extern struct cmos_option_table option_table;

/* defined by mainboard.c if the mainboard requires extra resources */
-int add_mainboard_resources(struct lb_memory *mem);
+void add_mainboard_resources(struct lb_memory *mem);

#endif /* COREBOOT_TABLE_H */

-----Original Message-----
From: [e-mail]
[mailto:[e-mail]] On Behalf Of Bao, Zheng
Sent: Thursday, December 18, 2008 4:05 PM
To: Carl-Daniel Hailfinger; Coreboot
Subject: Re: [coreboot] Asus M2A-VM (patch for this issue)

The prototype of lb_add_memory_range is
    void lb_add_memory_range(struct lb_memory *mem,
       uint32_t type, uint64_t start, uint64_t size),
whose 3rd and 4th arguments are 64bits ones. When the gcc meets this
function, it has no idea about the arguments. Sometimes it assumes they
are 32bits ones. When the linker starts to play her role, there are not
enough spaces for 2 64bits arguments. Then the tables are not correct.
Then the DMA of SATA doesn't know the spaces is reserved. Then ...

some trailing white spaces are also deleted.

This patch doesn't seem to be a long term one. Each board that has its
own memory settings should add this. If you guys have a better way to
declare the prototype, please feel free to replace it.

Zheng

Signed-off-by: Zheng Bao

Index: src/mainboard/amd/pistachio/mainboard.c
===================================================================
--- src/mainboard/amd/pistachio/mainboard.c	(revision 237)
+++ src/mainboard/amd/pistachio/mainboard.c	(working copy)
@@ -324,15 +324,18 @@
    set_thermal_config();
 }

-int add_mainboard_resources(struct lb_memory *mem)
+extern void lb_add_memory_range(struct lb_memory *mem,
+	uint32_t type, uint64_t start, uint64_t size);
+
+void add_mainboard_resources(struct lb_memory *mem)
 {
    /* UMA is removed from system memory in the northbridge code,
but
     * in some circumstances we want the memory mentioned as
reserved.
     */
-#if (CONFIG_GFXUMA == 1) 
-	printk_info("uma_memory_start=0x%x, uma_memory_size=0x%x \n", 
+#if (CONFIG_GFXUMA == 1)
+	printk_info("uma_memory_start=0x%x, uma_memory_size=0x%x \n",
    uma_memory_start, uma_memory_size);
-	lb_add_memory_range(mem, LB_MEM_RESERVED, 
+	lb_add_memory_range(mem, LB_MEM_RESERVED,
    	uma_memory_start, uma_memory_size);
 #endif
 }
Index: src/mainboard/amd/dbm690t/mainboard.c
===================================================================
--- src/mainboard/amd/dbm690t/mainboard.c	(revision 237)
+++ src/mainboard/amd/dbm690t/mainboard.c	(working copy)
@@ -243,16 +243,19 @@
    get_ide_dma66();
    set_thermal_config();
 }
- 
-int add_mainboard_resources(struct lb_memory *mem)
+
+extern void lb_add_memory_range(struct lb_memory *mem,
+	uint32_t type, uint64_t start, uint64_t size);
+
+void add_mainboard_resources(struct lb_memory *mem)
 {
    /* UMA is removed from system memory in the northbridge code,
but
     * in some circumstances we want the memory mentioned as
reserved.
     */
-#if (CONFIG_GFXUMA == 1) 
-	printk_info("uma_memory_start=0x%x, uma_memory_size=0x%x \n", 
+#if (CONFIG_GFXUMA == 1)
+	printk_info("uma_memory_start=0x%x, uma_memory_size=0x%x \n",
    uma_memory_start, uma_memory_size);
-	lb_add_memory_range(mem, LB_MEM_RESERVED, 
+	lb_add_memory_range(mem, LB_MEM_RESERVED,
    	uma_memory_start, uma_memory_size);
 #endif
 }

-----Original Message-----
From: [e-mail]
[mailto:[e-mail]] On Behalf Of Bao, Zheng
Sent: Thursday, December 18, 2008 1:18 PM
To: Carl-Daniel Hailfinger; Coreboot
Subject: Re: [coreboot] Asus M2A-VM

I traced back coreboot_table.c.

I replace the add_mainboard_resources() with it used to be, that is,
lb_add_memory_range(). Then the e820 is right and SATA DMA also works .
I really don't know why it happens. I will keep dig it. If you guys have
any idea, please let us know.

Zheng

-----Original Message-----
From: [e-mail]
[mailto:[e-mail]] On Behalf Of Carl-Daniel
Hailfinger
Sent: Thursday, December 18, 2008 12:02 AM
To: Coreboot
Subject: Re: [coreboot] Asus M2A-VM

On 17.12.2008 16:11, Peter Stuge wrote:
> Carl-Daniel Hailfinger wrote:
> > my Asus M2A-VM (690G/SB600) is working and boots to memtest and FILO.
>
> Nice progress! Looking forward to hearing more.

The kernel hangs on SATA detection. That's expected, though, because
SATA setup is incomplete (only first port) and does not take care of
quirks of early revisions. I have a patch to set up all 4 SATA ports,
but the quirk fixups still need to be implemented.
And I'm hitting slightly unexpected behaviour during SATA PHY setup.
I'll give more info once I have access to my logs again.

Regards,
Carl-Daniel

[Carl-Daniel Hailfinger]

On 17.12.2008 04:39, Carl-Daniel Hailfinger wrote:
> Hi all,
>
> my Asus M2A-VM (690G/SB600) is working and boots to memtest and FILO.

New status:
Working:
- memtest86 works for 2 GB RAM
- FILO works and loads a Linux kernel
- Linux boots
- SATA disks work under Linux
- Network works under Linux
- Power button works
- Software poweroff works
Untested:
- VGA analog/DVI because I have no monitor available right now
- USB (later)
- SeaBIOS
Probably not working, must retest:
- 4 GB RAM
Not working:
- SATA multicount transfers (detected as unsupported by Linux)
- Powernow ("invalid freq entries 1000000 kHz vs. 800000 kHz")

Patch against AMD DBM690T follows. Most parts of the patch (those for
generic code) have been submitted already.

Signed-off-by: Carl-Daniel Hailfinger

Index: LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_early_setup.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_early_setup.c	(Revision 3837)
+++ LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_early_setup.c	(Arbeitskopie)
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008 Carl-Daniel Hailfinger
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -175,8 +176,9 @@
    /*
     * About HT, it has been done in enumerate_ht_chain().
     */
-	device_t k8_f0;
+	device_t k8_f0, rs690_f0;
    u32 reg;
+	u8 reg8;
    u8 k8_ht_freq;

k8_f0 = PCI_DEV(0, 0x18, 0);
@@ -195,7 +197,22 @@
    ************************/
    reg = pci_read_config32(k8_f0, 0x88);
    k8_ht_freq = (reg & 0xf00) >> 8;
-	printk_info("rs690_ht_init k8_ht_freq=%x.\n", k8_ht_freq);
+	printk_spew("rs690_htinit k8_ht_freq=%x.\n", k8_ht_freq);
+	rs690_f0 = PCI_DEV(0, 0, 0);
+	reg8 = pci_read_config8(rs690_f0, 0x9c);
+	printk_spew("rs690_htinit NB_CFG_Q_F1000_800=%x\n", reg8);
+	/* For 1000 MHz HT, NB_CFG_Q_F1000_800 bit 0 MUST be set.
+	 * For any other HT frequency, NB_CFG_Q_F1000_800 bit 0 MUST NOT be set.
+	 */
+	if (((k8_ht_freq == 0x6) || (k8_ht_freq == 0xf)) && (!(reg8 & 0x1))) {
+		printk_info("rs690_htinit setting bit 0 in NB_CFG_Q_F1000_800 to use 1 GHz HT\n");
+		reg8 |= 0x1;
+		pci_write_config8(rs690_f0, 0x9c, reg8);
+	} else if ((k8_ht_freq != 0x6) && (k8_ht_freq != 0xf) && (reg8 & 0x1)) {
+		printk_info("rs690_htinit clearing bit 0 in NB_CFG_Q_F1000_800 to not use 1 GHz HT\n");
+		reg8 &= ~0x1;
+		pci_write_config8(rs690_f0, 0x9c, reg8);
+	}
 }

/*******************************************************
@@ -462,7 +479,6 @@
    	break;
    }

-	rs690_htinit();
    k8_optimization();
    rs690_por_init(nb_dev);
 }
Index: LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/sb600/sb600_sata.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/sb600/sb600_sata.c	(Revision 3837)
+++ LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/sb600/sb600_sata.c	(Arbeitskopie)
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008 Carl-Daniel Hailfinger
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -26,6 +27,28 @@
 #include <arch/io.h>
 #include "sb600.h"

+int sata_drive_detect(int portnum, u16 iobar)
+{
+	u8 byte, byte2;
+	int i = 0;
+	outb(0xA0 + 0x10 * (portnum % 2), iobar + 0x6);
+	while (byte = inb(iobar + 0x6),
+	       byte2 = inb(iobar + 0x7),
+	       i++,
+	       (byte != (0xA0 + 0x10 * (portnum % 2))) ||
+	       ((byte2 & 0x88) != 0)) {
+		printk_spew("0x6=%x, 0x7=%x\n", byte, byte2);
+		if (byte != (0xA0 + 0x10 * (portnum % 2))) {
+			printk_debug("drive no longer selected after %i ms, retrying init\n", i * 10);
+			return 1;
+		} else
+			printk_spew("drive detection not yet completed, waiting...\n");
+		mdelay(10);
+	}
+	printk_spew("drive detection done after %i ms\n", i * 10);
+	return 0;
+}
+
 static void sata_init(struct device *dev)
 {
    u8 byte;
@@ -33,6 +56,7 @@
    u32 dword;
    u8 *sata_bar5;
    u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
+	int i;

struct southbridge_ati_sb600_config *conf;
    conf = dev->chip_info;
@@ -62,12 +86,12 @@
    sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x7;
    sata_bar4 = pci_read_config16(dev, 0x20) & ~0x7;

-	/* printk_debug("sata_bar0=%x\n", sata_bar0); */	/* 3030 */
-	/* printk_debug("sata_bar1=%x\n", sata_bar1); */	/* 3070 */
-	/* printk_debug("sata_bar2=%x\n", sata_bar2); */	/* 3040 */
-	/* printk_debug("sata_bar3=%x\n", sata_bar3); */	/* 3080 */
-	/* printk_debug("sata_bar4=%x\n", sata_bar4); */	/* 3000 */
-	/* printk_debug("sata_bar5=%x\n", sata_bar5); */	/* e0309000 */
+	printk_spew("sata_bar0=%x\n", sata_bar0);	/* 3030 */
+	printk_spew("sata_bar1=%x\n", sata_bar1);	/* 3070 */
+	printk_spew("sata_bar2=%x\n", sata_bar2);	/* 3040 */
+	printk_spew("sata_bar3=%x\n", sata_bar3);	/* 3080 */
+	printk_spew("sata_bar4=%x\n", sata_bar4);	/* 3000 */
+	printk_spew("sata_bar5=%x\n", sata_bar5);	/* e0309000 */

/* Program the 2C to 0x43801002 */
    dword = 0x43801002;
@@ -136,26 +160,26 @@
    byte |= 7 << 0;
    pci_write_config8(dev, 0x4, byte);

-	/* RPR6.6 SATA drive detection. Currently we detect Primary Master Device only */
-	/* Use BAR5+0x1A8,BAR0+0x6 for Primary Slave */
-	/* Use BAR5+0x228,BAR0+0x6 for Secondary Master */
-	/* Use BAR5+0x2A8,BAR0+0x6 for Secondary Slave */
+	/* RPR6.6 SATA drive detection. */
+	/* Use BAR5+0x128,BAR0 for Primary Slave */
+	/* Use BAR5+0x1A8,BAR0 for Primary Slave */
+	/* Use BAR5+0x228,BAR2 for Secondary Master */
+	/* Use BAR5+0x2A8,BAR2 for Secondary Slave */

-	byte = readb(sata_bar5 + 0x128);
-	/* printk_debug("byte=%x\n", byte); */
-	byte &= 0xF;
-	if (byte == 0x3) {
-		outb(0xA0, sata_bar0 + 0x6);
-		while ((inb(sata_bar0 + 0x6) != 0xA0)
-		       || ((inb(sata_bar0 + 0x7) & 0x88) != 0)) {
-			mdelay(10);
-			/* printk_debug("0x6=%x,0x7=%x\n", inb(sata_bar0 + 0x6),
-			   inb(sata_bar0 + 0x7)); */
-			printk_debug("drive detection fail,trying...\n");
+	for (i = 0; i < 4; i++) {
+		byte = readb(sata_bar5 + 0x128 + 0x80 * i);
+		printk_spew("SATA port %i status = %x\n", i, byte);
+		byte &= 0xF;
+		if (byte == 0x3) {
+			while (sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2));
+			printk_debug("%s %s device is ready\n",
+				     (i / 2) ? "Secondary" : "Primary",
+				     (i % 2 ) ? "Slave" : "Master");
+		} else {
+			printk_debug("No %s %s SATA drive on Slot%i\n",
+				     (i / 2) ? "Secondary" : "Primary",
+				     (i % 2 ) ? "Slave" : "Master", i);
    	}
-		printk_debug("Primary master device is ready\n");
-	} else {
-		printk_debug("No Primary master SATA drive on Slot0\n");
    }

/* Below is CIM InitSataLateFar */
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/pistachio/acpi_tables.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/pistachio/acpi_tables.c	(Revision 3837)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/pistachio/acpi_tables.c	(Arbeitskopie)
@@ -133,7 +133,7 @@
    u32 *v;
    struct cpuid_result cpuid1;

-	typedef struct power_limit_encoding {
+	struct power_limit_encoding {
    	u8 socket_type;
    	u8 cmp_cap;
    	u8 pwr_lmt;
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/pistachio/cache_as_ram_auto.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/pistachio/cache_as_ram_auto.c	(Revision 3837)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/pistachio/cache_as_ram_auto.c	(Arbeitskopie)
@@ -213,6 +213,7 @@

needs_reset = optimize_link_coherent_ht();
    needs_reset |= optimize_link_incoherent_ht(sysinfo);
+	rs690_htinit();
    printk_debug("needs_reset=0x%x\n", needs_reset);

post_code(0x06);
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/fadt.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/fadt.c	(Revision 3837)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/fadt.c	(Arbeitskopie)
@@ -25,6 +25,8 @@
 #include <console/console.h>
 #include <arch/acpi.h>
 #include <arch/io.h>
+#include <device/device.h>
+#include <../southbridge/amd/sb600/sb600.h>

/*extern*/ u16 pm_base = 0x800;
 /* pm_base should be set in sb acpi */
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Config.lb
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Config.lb	(Revision 3837)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Config.lb	(Arbeitskopie)
@@ -198,7 +198,7 @@
 #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
 chip northbridge/amd/amdk8/root_complex
    device apic_cluster 0 on
-		chip cpu/amd/socket_S1G1
+		chip cpu/amd/socket_AM2
    	device apic 0 on end
    	end
    end
@@ -214,8 +214,8 @@
    					end
    				end
    				device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
-					device pci 3.0 off end # PCIE P2P bridge	0x791b
-					device pci 4.0 on end # PCIE P2P bridge 0x1914
+					#device pci 3.0 off end # PCIE P2P bridge	0x791b
+					device pci 4.0 on end # PCIE P2P bridge 0x7914
    				device pci 5.0 on end # PCIE P2P bridge 0x7915
    				device pci 6.0 on end # PCIE P2P bridge 0x7916
    				device pci 7.0 on end # PCIE P2P bridge 0x7917
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Options.lb
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Options.lb	(Revision 3837)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Options.lb	(Arbeitskopie)
@@ -290,9 +290,9 @@
 ## SPEW       9   Way too many details

## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  DEFAULT_CONSOLE_LOGLEVEL=9
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  MAXIMUM_CONSOLE_LOGLEVEL=9

##
 ## Select power on after power fail setting
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/acpi_tables.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/acpi_tables.c	(Revision 3837)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/acpi_tables.c	(Arbeitskopie)
@@ -133,7 +133,7 @@
    u32 *v;
    struct cpuid_result cpuid1;

-	typedef struct power_limit_encoding {
+	struct power_limit_encoding {
    	u8 socket_type;
    	u8 cmp_cap;
    	u8 pwr_lmt;
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c	(Revision 3837)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c	(Arbeitskopie)
@@ -25,6 +25,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <device/pci_def.h>
+#include <../southbridge/amd/sb600/sb600.h>
 #include "chip.h"

#define ADT7461_ADDRESS 0x4C
@@ -34,6 +35,8 @@
 extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
 extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
    		       u8 val);
+extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type, 
+				uint64_t start, uint64_t size);
 #define ADT7461_read_byte(address) \
    do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
 #define ARA_read_byte(address) \
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c	(Revision 3837)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c	(Arbeitskopie)
@@ -210,6 +210,7 @@

needs_reset = optimize_link_coherent_ht();
    needs_reset |= optimize_link_incoherent_ht(sysinfo);
+	rs690_htinit();
    printk_debug("needs_reset=0x%x\n", needs_reset);

Index: LinuxBIOSv2-asus_m2a-vm/targets/amd/dbm690t/Config-abuild.lb
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/targets/amd/dbm690t/Config-abuild.lb	(Revision 3837)
+++ LinuxBIOSv2-asus_m2a-vm/targets/amd/dbm690t/Config-abuild.lb	(Arbeitskopie)
@@ -7,6 +7,9 @@
 option CROSS_COMPILE="CROSS_PREFIX"
 option HOSTCC="CROSS_HOSTCC"

+option DEFAULT_CONSOLE_LOGLEVEL = 9
+option MAXIMUM_CONSOLE_LOGLEVEL = 9
+
 __COMPRESSION__

option ROM_SIZE=1024*1024

[Carl-Daniel Hailfinger]

On 23.12.2008 04:51, Carl-Daniel Hailfinger wrote:
> On 17.12.2008 04:39, Carl-Daniel Hailfinger wrote:
> > Hi all,
> >
> > my Asus M2A-VM (690G/SB600) is working and boots to memtest and FILO.
>
> New status:
> Working:
> memtest86 works for 2 GB RAM
> FILO works and loads a Linux kernel
> Linux boots
> SATA disks work under Linux
> Network works under Linux
> Power button works
> Software poweroff works

- VGA text mode over D-Sub connector and over DVI connector (no idea
whether that's the digital or analog variant) works fine. Somehow Linux
does not want to activate the VESA framebuffer console.
> Untested:
> USB (later)
> SeaBIOS
>
> Probably not working, must retest:
> 4 GB RAM
>
> Not working:
> SATA multicount transfers (detected as unsupported by Linux)
> Powernow ("invalid freq entries 1000000 kHz vs. 800000 kHz")

[ron minnich]

If anyone wants to port these to v3 that would be helpful.

ron

[Carl-Daniel Hailfinger]

On 23.12.2008 17:12, ron minnich wrote:
> If anyone wants to port these to v3 that would be helpful.

With v3 I don't even get POST codes on my board. I'll tackle that in due
course.

Regards,
Carl-Daniel

[ron minnich]

On Tue, Dec 23, 2008 at 8:29 AM, Carl-Daniel Hailfinger
 wrote:
> I'll tackle that in due
> course.

A word to a very wise person.

Be very careful about commitments with a future tense. You are one of
the smartest guys we have, and I admire your enthusiasm. Thus you are
always prepared to help, which I think is wonderful. The only issue is
that you are spreading yourself a little thin. There are two harmful
effects from too many commitments
1. In the long term, it can hurt your credibility. I will only say
that I know this has harm to your credibility has happened. I don't
want it to happen -- you are too good a person.
2. It discourages others from taking on a task they might do -- "C-D
said he is doing that". We want to encourage others as much as we can.

So, please be very careful about making these commitments. Here is an
easy recommendation: ensure that people know that you are working on
one thing, and never make more than one commitment into the future.
Your work on the 690 has been fantastic -- let's make sure people
associate your name with these types of efforts.

Thanks and Merry Christmas! I really am grateful for the effort you
are putting into this project. Its continued improvement is due in no
small part to your efforts.

Ron

[ron minnich]

I apologize, that was supposed to be a private message.

That's what happens when the interrupt overload is too high.

I apologize again.

ron

[Carl-Daniel Hailfinger]

On 23.12.2008 14:54, Carl-Daniel Hailfinger wrote:
> On 23.12.2008 04:51, Carl-Daniel Hailfinger wrote:
> > On 17.12.2008 04:39, Carl-Daniel Hailfinger wrote:
> > > Hi all,
> > >
> > > my Asus M2A-VM (690G/SB600) is working and boots to memtest and FILO.
> >
> > New status:
> > Working:
> > memtest86 works for 2 GB RAM
> > FILO works and loads a Linux kernel
> > Linux boots
> > SATA disks work under Linux
> > Network works under Linux
> > Power button works
> > Software poweroff works
> VGA text mode over D-Sub connector and over DVI connector (no idea
>
> whether that's the digital or analog variant) works fine. Somehow Linux
> does not want to activate the VESA framebuffer console.
> > Untested:
> > USB (later)
> > SeaBIOS
> >
> > Probably not working, must retest:
> > 4 GB RAM
> >
> > Not working:
> > SATA multicount transfers (detected as unsupported by Linux)
> > Powernow ("invalid freq entries 1000000 kHz vs. 800000 kHz")

Boot log attached.

Regards,
Carl-Daniel

wiki page for Asus M2A-VM (was: Re: Asus M2A-VM)

[Paul Menzel]

Dear Carl-Daniel,

I hope you could enjoy Christmas, although you were being Santa Clause
giving us all this great present porting this board to coreboot.

I hope I did not do anything wrong creating a wiki page [1] for this
board. I put in Untested most of the times. Maybe you could enhance
that.

If you want to link to it from the supported motherboard page [2], just
add these lines to the table.

|- bgcolor="#dddddd"
| ASUS
| [http://www.asus.com/products.aspx?l1=3&l2=101&l3=496&l4=0&mo... M2A-VM]
| AMD 690G
| ATI SB600
| ITE™ IT8716F
| AMD Athlon™ 64X2 / 64FX / 64, Sempron™
| Socket AM2 / AM2+
| style="background:lime" | [[ASUS M2A-VM|OK...]]
| ?
| SPI
| style="background:lime" | N
| style="background:lime" | Y
| —

I hope the values are correct.

Thank you again for your great work. In the semester break, i. e. March,
I am going to put coreboot on my ASUS M2A-VM.

Thanks and have a good New Year,

Paul

[1] http://www.coreboot.org/index.php?title=ASUS_M2A-VM
[2] http://www.coreboot.org/Supported_Motherboards

wiki page for Asus M2A-VM

[Carl-Daniel Hailfinger]

Dear Paul,

On 30.12.2008 11:19, Paul Menzel wrote:
> Dear Carl-Daniel,
>
> I hope you could enjoy Christmas, although you were being Santa Clause
> giving us all this great present porting this board to coreboot.
>
> I hope I did not do anything wrong creating a wiki page [1] for this
> board. I put in Untested most of the times. Maybe you could enhance
> that.

Thanks, updated.
> If you want to link to it from the supported motherboard page [2], just
> add these lines to the table.
>
> |- bgcolor="#dddddd"
> | ASUS
> | [http://www.asus.com/products.aspx?l1=3&l2=101&l3=496&l4=0&mo... M2A-VM]
> | AMD 690G
> | ATI SB600
> | ITE™ IT8716F
> | AMD Athlon™ 64X2 / 64FX / 64, Sempron™
> | Socket AM2 / AM2+
> | style="background:lime" | [[ASUS M2A-VM|OK...]]
> | ?
> | SPI
> | style="background:lime" | N
> | style="background:lime" | Y
> | —
>
> I hope the values are correct.

Can you do that? Thanks! I will not have internet access in the next few
days.
> Thank you again for your great work. In the semester break, i. e. March,
> I am going to put coreboot on my ASUS M2A-VM.
>
> Thanks and have a good New Year,

Thanks, a good new year to you, too.

Regards,
Carl-Daniel

wiki page for Asus M2A-VM

[Paul Menzel]

Dear Carl-Daniel,

Am Dienstag, den 30.12.2008, 12:08 +0100 schrieb Carl-Daniel Hailfinger:
> On 30.12.2008 11:19, Paul Menzel wrote:
> > If you want to link to it from the supported motherboard page [2], just
> > add these lines to the table.
> >
> > |- bgcolor="#dddddd"
> > | ASUS
> > | [http://www.asus.com/products.aspx?l1=3&l2=101&l3=496&l4=0&mo... M2A-VM]
> > | AMD 690G
> > | ATI SB600
> > | ITE™ IT8716F
> > | AMD Athlon™ 64X2 / 64FX / 64, Sempron™
> > | Socket AM2 / AM2+
> > | style="background:lime" | [[ASUS M2A-VM|OK...]]
> > | ?
> > | SPI
> > | style="background:lime" | N
> > | style="background:lime" | Y
> > | —
> >
> > I hope the values are correct.
>
> Can you do that? Thanks! I will not have internet access in the next few
> days.

Done [1]. If you have time could you please send me or update the ROM
chip package (PLCC, DIP32, DIP8, SOIC8)?

Bests,

Paul

[1] http://www.coreboot.org/Supported_Motherboards#Motherboards_supported_in_cor...

wiki page for Asus M2A-VM

[Peter Stuge]

Paul Menzel wrote:
> Done [1]. If you have time could you please send me or update the
> ROM chip package (PLCC, DIP32, DIP8, SOIC8)?

The board has a soldered PLCC LPC flash chip.

//Peter

wiki page for Asus M2A-VM

[Paul Menzel]

Am Freitag, den 02.01.2009, 01:58 +0100 schrieb Peter Stuge:
> Paul Menzel wrote:
> > Done [1]. If you have time could you please send me or update the
> > ROM chip package (PLCC, DIP32, DIP8, SOIC8)?
>
> The board has a soldered PLCC LPC flash chip.

Thanks, Peter. Done [1].

Unfortunately the Wiki seems to be an older version, since the links in
the (change) comments are not formated correctly. At least it works in
Wikipedia I think. Also references would be supported directly.

No it is up to Carl-Daniel to announce the port on the main page.

Thanks,

Paul

[1] http://www.coreboot.org/index.php?title=Supported_Motherboards&oldid=780...

wiki page for Asus M2A-VM

[Carl-Daniel Hailfinger]

On 02.01.2009 16:24, Paul Menzel wrote:
> Am Freitag, den 02.01.2009, 01:58 +0100 schrieb Peter Stuge:
> > Paul Menzel wrote:
> > > Done [1]. If you have time could you please send me or update the
> > > ROM chip package (PLCC, DIP32, DIP8, SOIC8)?
> >
> > The board has a soldered PLCC LPC flash chip.
>
> Thanks, Peter. Done [1].
>
> Unfortunately the Wiki seems to be an older version, since the links in
> the (change) comments are not formated correctly. At least it works in
> Wikipedia I think. Also references would be supported directly.
>
> Now it is up to Carl-Daniel to announce the port on the main page.

Thanks, I'll test with 4 GB RAM and some USB flash drives and report back.

Regards,
Carl-Daniel

wiki page for Asus M2A-VM

[Carl-Daniel Hailfinger]

On 02.01.2009 16:37, Carl-Daniel Hailfinger wrote:
> On 02.01.2009 16:24, Paul Menzel wrote:
> > Am Freitag, den 02.01.2009, 01:58 +0100 schrieb Peter Stuge:
> > > Paul Menzel wrote:
> > > > Done [1]. If you have time could you please send me or update the
> > > > ROM chip package (PLCC, DIP32, DIP8, SOIC8)?
> > >
> > > The board has a soldered PLCC LPC flash chip.
> >
> > Thanks, Peter. Done [1].
> >
> > Unfortunately the Wiki seems to be an older version, since the links in
> > the (change) comments are not formated correctly. At least it works in
> > Wikipedia I think. Also references would be supported directly.
> >
> > Now it is up to Carl-Daniel to announce the port on the main page.
>
> Thanks, I'll test with 4 GB RAM and some USB flash drives and report back.

4 GB are a problem for dualchannel because my DIMMS are only compatible
and not identical. That's a missing feature in our code. I have sent a
cleanup patch which should make fixing that a bit easier.

Other status items were updated as well:

Fan control and sensors do not work yet because the GPIO and SIO
controls hang the machine during coreboot init if enabled via Config.lb.
Maybe direct PNP writes will fix that.

CPU frequency scaling works with the patch I sent a few hours ago.

Besides that, I think the board is in pretty good shape.

Regards,
Carl-Daniel