SMP or single CPU?
If SMP, and io apci is enabled, you may only focus on mptable.c and irq-tables.c may only contain device that point to the peer roots bus.
YH
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From: Dave Aubin [mailto:daubin@actuality-systems.com] Sent: Thursday, September 30, 2004 11:53 AM To: Dave Aubin; linuxbios@clustermatic.org Subject: RE: PCI IRQ tables
Hi,
I didn't get an answer from the previous post so I'll just simplify a little bit. Can someone point me to where I can learn more about the magic that makes the pci_irq files?
Thanks, Dave:)
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From: linuxbios-admin@clustermatic.org [mailto:linuxbios-admin@clustermatic.org] On Behalf Of Dave Aubin Sent: Wednesday, September 29, 2004 5:18 PM To: linuxbios@clustermatic.org Subject: PCI IRQ tables Hi,
What happens if the pci irq mapping is a mess? I know you can use getpir with a good bios, but what if you don't have one? Is there a way to get the pci irq mapping without a standard bios? If you had to do it by hand could you explain how it should be done?
Thanks, Dave
YhLu wrote:
SMP or single CPU?
If SMP, and io apci is enabled, you may only focus on mptable.c and irq-tables.c may only contain device that point to the peer roots bus.
YH
How about single CPU with IO-APIC enabled in linux?
We are designing a new AMD64 mainboard and want to use linuxbios, the IO architecture is showed in the attached picture. I'm not sure how to specify the "PCI IRQ Router" in pirq table for this architecture. Since each AMD8131 and AMD8111 all provide legacy PIC mode interrupt controller, I think maybe there isn't a global legacy PIC mode PCI IRQ router for different NCHT channels? Maybe APIC is the better choice?
Best Regards, Liu Tao
YhLu wrote:
SMP or single CPU?
If SMP, and io apci is enabled, you may only focus on mptable.c and irq-tables.c may only contain device that point to the peer roots bus.
YH
How about single CPU with IO-APIC enabled in linux?
We are designing a new AMD64 mainboard and want to use linuxbios, the IO architecture is showed in the attached picture. I'm not sure how to specify the "PCI IRQ Router" in pirq table for this architecture. Since each AMD8131 and AMD8111 all provide legacy PIC mode interrupt controller, I think maybe there isn't a global legacy PIC mode PCI IRQ router for different NCHT channels? Maybe APIC is the better choice?
Best Regards, Liu Tao
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Liu Tao -
YhLu