I am trying to put coreboot v2 on a tyan s2881 and I would like to use seabios and gpxe for the payload . I successfully created the coreboot.rom by following the s2881 build tutorial and seabios tutorial. I then tried to add gpxe to the coreboot rom and I received this output from cbfstool:
$./cbfstool ../../targets/tyan/s2881/s2881/coreboot.rom add ../../../gpxe-0.9.6-tg3-5704.rom pci14e4,1648 99 Could not add the file to CBFS, it's probably too big.
$ ./cbfstool ../../targets/tyan/s2881/s2881/coreboot.rom print ../../targets/tyan/s2881/s2881/coreboot.rom: 512 kB, bootblocksize 262144, romsize 524288, offset 0x0 Alignment: 64 bytes
Name Offset Type Size normal/payload 0x0 payload 65592 normal/coreboot_ram 0x10080 stage 56173 fallback/payload 0x1dc40 payload 65592 fallback/coreboot_ram 0x2dcc0 stage 55651 0x3b680 null 18744
I taked to Ron about this and he suggested to try the Kconfig build system as that would create a smaller rom. That failed and I received this output:
$make GEN build/build.h HOSTCC build_opt_tbl OPTION option_table.h In file included from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:17: /local/coreboot/coreboot-v2/build/option_table.h:45:1: warning: "CMOS_VSTART_reserved_memory" redefined /local/coreboot/coreboot-v2/build/option_table.h:1:1: warning: this is the location of the previous definition /local/coreboot/coreboot-v2/build/option_table.h:46:1: warning: "CMOS_VLEN_reserved_memory" redefined /local/coreboot/coreboot-v2/build/option_table.h:2:1: warning: this is the location of the previous definition In file included from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:19: /local/coreboot/coreboot-v2/src/pc80/serial.c:74: warning: no previous prototype for ‘uart_init’ In file included from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:21: /local/coreboot/coreboot-v2/src/lib/ramtest.c:137: warning: no previous prototype for ‘ram_check’ In file included from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:36: /local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c:32:2: error: #error This file needs CONFIG_USE_PRINTK_IN_CAR In file included from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:36: /local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c: In function ‘print_linkn_in’: /local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c:37: warning: implicit declaration of function ‘printk_debug’ /local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c: In function ‘ht_read_freq_cap’: /local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c:138: warning: implicit declaration of function ‘printk_spew’ /local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c: In function ‘ht_setup_chainx’: /local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c:571: warning: unused variable ‘i’ In file included from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:39: /local/coreboot/coreboot-v2/src/cpu/amd/model_fxx/apic_timer.c: At top level: /local/coreboot/coreboot-v2/src/cpu/amd/model_fxx/apic_timer.c:6: warning: no previous prototype for ‘init_timer’ /local/coreboot/coreboot-v2/src/cpu/amd/model_fxx/apic_timer.c:19: warning: no previous prototype for ‘udelay’ In file included from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:40: /local/coreboot/coreboot-v2/src/lib/delay.c:2: warning: no previous prototype for ‘mdelay’ /local/coreboot/coreboot-v2/src/lib/delay.c:9: warning: no previous prototype for ‘delay’ In file included from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:87: /local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/raminit.c:23: warning: redundant redeclaration of ‘hard_reset’ /local/coreboot/coreboot-v2/src/southbridge/amd/amd8111/amd8111_early_ctrl.c:39: warning: previous definition of ‘hard_reset’ was here In file included from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:87: /local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/raminit.c:576:2: warning: #warning "FIXME: Implement a better test for Opterons" /local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/raminit.c:1083: warning: no previous prototype for ‘memory_end_k’ /local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/raminit.c: In function ‘sdram_set_spd_registers’: /local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/raminit.c:2109: warning: implicit declaration of function ‘printk_err’ In file included from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:90: /local/coreboot/coreboot-v2/src/lib/generic_sdram.c: At top level: /local/coreboot/coreboot-v2/src/lib/generic_sdram.c:15: warning: no previous prototype for ‘sdram_no_memory’ /local/coreboot/coreboot-v2/src/lib/generic_sdram.c:27: warning: no previous prototype for ‘sdram_initialize’ In file included from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:92: /local/coreboot/coreboot-v2/src/cpu/amd/dualcore/dualcore.c: In function ‘do_k8_init_and_stop_secondaries’: /local/coreboot/coreboot-v2/src/cpu/amd/dualcore/dualcore.c:78: warning: unused variable ‘apicid’ In file included from /local/coreboot/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c:4, from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:97: /local/coreboot/coreboot-v2/src/cpu/amd/car/disable_cache_as_ram.c:19:5: warning: "CONFIG_DCACHE_RAM_SIZE" is not defined In file included from /local/coreboot/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c:6, from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:97: /local/coreboot/coreboot-v2/src/cpu/amd/car/clear_init_ram.c: In function ‘clear_init_ram’: /local/coreboot/coreboot-v2/src/cpu/amd/car/clear_init_ram.c:14: error: ‘CONFIG_DCACHE_RAM_SIZE’ undeclared (first use in this function) /local/coreboot/coreboot-v2/src/cpu/amd/car/clear_init_ram.c:14: error: (Each undeclared identifier is reported only once /local/coreboot/coreboot-v2/src/cpu/amd/car/clear_init_ram.c:14: error: for each function it appears in.) In file included from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:97: /local/coreboot/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c: In function ‘post_cache_as_ram’: /local/coreboot/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c:79: error: ‘CONFIG_DCACHE_RAM_SIZE’ undeclared (first use in this function) /local/coreboot/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c:79: error: ‘CONFIG_DCACHE_RAM_BASE’ undeclared (first use in this function) /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c: At top level: /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:107: warning: no previous prototype for ‘failover_process’ /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:155: warning: no previous prototype for ‘cache_as_ram_main’ make: *** [/local/coreboot/coreboot-v2/build/mainboard/tyan/s2881/auto.inc] Error 1
Any ideas? Thanks.
On Thu, Oct 1, 2009 at 8:54 AM, Hugh Greenberg hng@lanl.gov wrote:
I am trying to put coreboot v2 on a tyan s2881 and I would like to use seabios and gpxe for the payload . I successfully created the coreboot.rom by following the s2881 build tutorial and seabios tutorial. I then tried to add gpxe to the coreboot rom and I received this output from cbfstool:
$./cbfstool ../../targets/tyan/s2881/s2881/coreboot.rom add ../../../gpxe-0.9.6-tg3-5704.rom pci14e4,1648 99 Could not add the file to CBFS, it's probably too big.
$ ./cbfstool ../../targets/tyan/s2881/s2881/coreboot.rom print ../../targets/tyan/s2881/s2881/coreboot.rom: 512 kB, bootblocksize 262144, romsize 524288, offset 0x0 Alignment: 64 bytes
Name Offset Type Size normal/payload 0x0 payload 65592 normal/coreboot_ram 0x10080 stage 56173 fallback/payload 0x1dc40 payload 65592 fallback/coreboot_ram 0x2dcc0 stage 55651 0x3b680 null 18744
I didn't see how big the gpxe ROM is. That might influence which of these choices you make.
You could: 1. shrink your bootblock (CONFIG_ROM_IMAGE_SIZE) 2. do fallback-only (Remove anything that says normal in targets/tyan/s2881/s2881/Config.lb)
I taked to Ron about this and he suggested to try the Kconfig build system as that would create a smaller rom. That failed and I received this output:
3. Apply the attached patch (updated version of one that is waiting to be reviewed.)
Thanks, Myles
That patch looks fine to me, is there an issue?
ron
On Thu, Oct 1, 2009 at 10:14 AM, ron minnich rminnich@gmail.com wrote:
That patch looks fine to me, is there an issue?
Not that I know of. It was just waiting for review. I just forgot to include my sign off with the updated patch.
Signed-off-by: Myles Watson mylesgw@gmail.com
Thanks, Myles
On Thu, Oct 1, 2009 at 9:17 AM, Myles Watson mylesgw@gmail.com wrote:
On Thu, Oct 1, 2009 at 10:14 AM, ron minnich rminnich@gmail.com wrote:
That patch looks fine to me, is there an issue?
Not that I know of. It was just waiting for review. I just forgot to include my sign off with the updated patch.
Signed-off-by: Myles Watson mylesgw@gmail.com
Acked-by: Ronald G. Minnich rminnich@gmail.com
On Thu, Oct 1, 2009 at 10:19 AM, ron minnich rminnich@gmail.com wrote:
On Thu, Oct 1, 2009 at 9:17 AM, Myles Watson mylesgw@gmail.com wrote:
On Thu, Oct 1, 2009 at 10:14 AM, ron minnich rminnich@gmail.com wrote:
That patch looks fine to me, is there an issue?
Not that I know of. It was just waiting for review. I just forgot to include my sign off with the updated patch.
Signed-off-by: Myles Watson mylesgw@gmail.com
Acked-by: Ronald G. Minnich rminnich@gmail.com
Rev 4702.
Thanks, Myles
Thanks. I took option number 2. It flashed successfully, however, gpxe does not seem to be starting. Here is the output from the coreboot/seabios:
coreboot-2.0.0-r_s2881_Fallback Thu Oct 1 17:07:49 MDT 2009 starting... (0,1) link=00 (1,0) link=00 02 nodes initialized. core0 started: 01 started ap apicid: SBLink=02 NC node|link=02 ht reset -
coreboot-2.0.0-r_s2881_Fallback Thu Oct 1 17:07:49 MDT 2009 starting... (0,1) link=00 (1,0) link=00 02 nodes initialized. core0 started: 01 started ap apicid: SBLink=02 NC node|link=02 Ram1.00 Ram1.01 Ram2.00 RAM end at 0x00100000 kB Ram2.01 RAM end at 0x00200000 kB Ram3 Initializing memory: done Initializing memory: done Ram4 v_esp=000cfe38 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Jumping to image. Check fallback/payload Check fallback/coreboot_ram Stage: load fallback/coreboot_ram @ 16384/245760 bytes, enter @ 4000 Stage: done loading. Jumping to image. coreboot-2.0.0-r_s2881_Fallback Thu Oct 1 17:07:49 MDT 2009 booting... Enumerating buses... Show all devs...Before Device Enumeration. Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:18.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:09.0: enabled 1, 0 resources PCI: 00:09.1: enabled 1, 0 resources PCI: 00:0a.0: enabled 1, 0 resources PCI: 00:0a.1: enabled 1, 0 resources PCI: 00:00.1: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PCI: 00:01.1: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.1: enabled 1, 0 resources PCI: 00:00.2: enabled 0, 0 resources PCI: 00:01.0: enabled 0, 0 resources PCI: 00:05.0: enabled 1, 0 resources PCI: 00:06.0: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PNP: 002e.0: enabled 1, 3 resources PNP: 002e.1: enabled 0, 2 resources PNP: 002e.2: enabled 1, 2 resources PNP: 002e.3: enabled 0, 2 resources PNP: 002e.5: enabled 1, 4 resources PNP: 002e.6: enabled 0, 1 resources PNP: 002e.7: enabled 0, 3 resources PNP: 002e.8: enabled 0, 0 resources PNP: 002e.9: enabled 0, 0 resources PNP: 002e.a: enabled 0, 0 resources PNP: 002e.b: enabled 1, 2 resources PCI: 00:01.1: enabled 1, 0 resources PCI: 00:01.2: enabled 1, 0 resources PCI: 00:01.3: enabled 1, 0 resources I2C: 00:50: enabled 1, 0 resources I2C: 00:51: enabled 1, 0 resources I2C: 00:52: enabled 1, 0 resources I2C: 00:53: enabled 1, 0 resources I2C: 00:54: enabled 1, 0 resources I2C: 00:55: enabled 1, 0 resources I2C: 00:56: enabled 1, 0 resources I2C: 00:57: enabled 1, 0 resources I2C: 00:2d: enabled 1, 0 resources I2C: 00:2a: enabled 1, 0 resources I2C: 00:49: enabled 1, 0 resources I2C: 00:4a: enabled 1, 0 resources PCI: 00:01.5: enabled 0, 0 resources PCI: 00:01.6: enabled 0, 0 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 0 resources Compare with tree... Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:18.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:09.0: enabled 1, 0 resources PCI: 00:09.1: enabled 1, 0 resources PCI: 00:0a.0: enabled 1, 0 resources PCI: 00:0a.1: enabled 1, 0 resources PCI: 00:00.1: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PCI: 00:01.1: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.1: enabled 1, 0 resources PCI: 00:00.2: enabled 0, 0 resources PCI: 00:01.0: enabled 0, 0 resources PCI: 00:05.0: enabled 1, 0 resources PCI: 00:06.0: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PNP: 002e.0: enabled 1, 3 resources PNP: 002e.1: enabled 0, 2 resources PNP: 002e.2: enabled 1, 2 resources PNP: 002e.3: enabled 0, 2 resources PNP: 002e.5: enabled 1, 4 resources PNP: 002e.6: enabled 0, 1 resources PNP: 002e.7: enabled 0, 3 resources PNP: 002e.8: enabled 0, 0 resources PNP: 002e.9: enabled 0, 0 resources PNP: 002e.a: enabled 0, 0 resources PNP: 002e.b: enabled 1, 2 resources PCI: 00:01.1: enabled 1, 0 resources PCI: 00:01.2: enabled 1, 0 resources PCI: 00:01.3: enabled 1, 0 resources I2C: 00:50: enabled 1, 0 resources I2C: 00:51: enabled 1, 0 resources I2C: 00:52: enabled 1, 0 resources I2C: 00:53: enabled 1, 0 resources I2C: 00:54: enabled 1, 0 resources I2C: 00:55: enabled 1, 0 resources I2C: 00:56: enabled 1, 0 resources I2C: 00:57: enabled 1, 0 resources I2C: 00:2d: enabled 1, 0 resources I2C: 00:2a: enabled 1, 0 resources I2C: 00:49: enabled 1, 0 resources I2C: 00:4a: enabled 1, 0 resources PCI: 00:01.5: enabled 0, 0 resources PCI: 00:01.6: enabled 0, 0 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 0 resources APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled PCI: 00:18.3 siblings=0 CPU: APIC: 00 enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] enabled PCI: 00:19.3 siblings=0 CPU: APIC: 01 enabled PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] enabled
I don't see 14e4/1648 above. Is that the problem? Any suggestions? Thanks.
Thanks. I took option number 2. It flashed successfully, however, gpxe does not seem to be starting. Here is the output from the coreboot/seabios:
PCI: 00:01.5: enabled 0, 0 resources PCI: 00:01.6: enabled 0, 0 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 0 resources APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled PCI: 00:18.3 siblings=0 CPU: APIC: 00 enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] enabled PCI: 00:19.3 siblings=0 CPU: APIC: 01 enabled PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] enabled
I don't see 14e4/1648 above. Is that the problem?
It should come after this. The full log would be helpful. Do you see the device's PCI device number that you see in lspci? eg. PCI: 00:01.5
Thanks, Myles
This is all the output I get on the serial port. How can I get a full log? I do not see the device number, its: 02:09.0 .
-----Original Message----- From: Hugh Greenberg [mailto:hng@lanl.gov] Sent: Thursday, October 01, 2009 5:46 PM To: Myles Watson Cc: coreboot@coreboot.org Subject: Re: [coreboot] tyan s2881 with seabios and gpxe
This is all the output I get on the serial port. How can I get a full log? I do not see the device number, its: 02:09.0 .
I thought you'd truncated it. It's hanging for some reason. I've never seen Coreboot hang there.
-- Hugh Greenberg Los Alamos National Laboratory, CCS-1 Email: hng@lanl.gov Phone: (505) 665-6471
Myles Watson wrote:
Thanks. I took option number 2. It flashed successfully, however,
gpxe
does not seem to be starting. Here is the output from the coreboot/seabios:
PCI: 00:01.5: enabled 0, 0 resources PCI: 00:01.6: enabled 0, 0 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 0 resources APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled PCI: 00:18.3 siblings=0 CPU: APIC: 00 enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] enabled PCI: 00:19.3 siblings=0 CPU: APIC: 01 enabled PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] enabled
I don't see 14e4/1648 above. Is that the problem?
It should come after this. The full log would be helpful. Do you see
the
device's PCI device number that you see in lspci? eg. PCI: 00:01.5
The next thing in my log is:
PCI: Using configuration type 1
Do you want to try Rev 4645? 4646 was the last one that touched that code.
Sorry I'm not more help.
Thanks, Myles
I was able to get coreboot pretty much up and running with gpxe and seabios. The trick was to use the Kconfig build system instead. I still have an issue though. I was not able to build it with ACPI tables, an mp table, or a PIRQ table. If I did, I got this error:
make: *** No rule to make target `/local/coreboot-v2/src/mainboard/tyan/s2881/dsdt.dsl', needed by `/local/coreboot-v2/build/dsdt.c'. Stop.
It seems as though I need these tables as Linux is not able to load the drivers for any PCI device. Could someone help me with this? Thanks again.
On Wed, Oct 7, 2009 at 2:14 PM, Hugh Greenberg hng@lanl.gov wrote:
I was able to get coreboot pretty much up and running with gpxe and seabios. The trick was to use the Kconfig build system instead. I still have an issue though. I was not able to build it with ACPI tables, an mp table, or a PIRQ table. If I did, I got this error:
make: *** No rule to make target `/local/coreboot-v2/src/mainboard/tyan/s2881/dsdt.dsl', needed by `/local/coreboot-v2/build/dsdt.c'. Stop.
The Tyan s2881 doesn't have ACPI support. It compiles for me if I select Generate an MP table & Generate a PIRQ table
Could you try selecting just those two in the System Tables menu?
Thanks, Myles
Yeah, it compiled. Thanks.
Myles Watson wrote:
The Tyan s2881 doesn't have ACPI support.
Each board should indicate this, so that the menu does not show options which are known to not work.
//Peter
On Wed, Oct 7, 2009 at 4:46 PM, Peter Stuge peter@stuge.se wrote:
Myles Watson wrote:
The Tyan s2881 doesn't have ACPI support.
Each board should indicate this, so that the menu does not show options which are known to not work.
Absolutely agreed. I think there will have to be another variable like HAS_ACPI_SUPPORT for that to happen. Right now HAVE_ACPI_TABLES defaults to 'n' in the s2881.
Is there another way?
Thanks, Myles
Myles Watson wrote:
The Tyan s2881 doesn't have ACPI support.
Each board should indicate this, so that the menu does not show options which are known to not work.
Absolutely agreed. I think there will have to be another variable like HAS_ACPI_SUPPORT for that to happen.
How about simply ACPI?
Right now HAVE_ACPI_TABLES defaults to 'n' in the s2881.
Is there another way?
I don't think so, but I think it's fine to add CONFIG_ACPI for this.
//Peter
On Wed, Oct 7, 2009 at 5:02 PM, Peter Stuge peter@stuge.se wrote:
Myles Watson wrote:
Absolutely agreed. I think there will have to be another variable like HAS_ACPI_SUPPORT for that to happen.
How about simply ACPI?
I think HAVE_ACPI_TABLES should become GENERATE_ACPI_TABLES and HAVE_ACPI_TABLES should take that new meaning. ACPI isn't specific enough to see what it does without looking elsewhere.
Right now HAVE_ACPI_TABLES defaults to 'n' in the s2881.
Is there another way?
I don't think so, but I think it's fine to add CONFIG_ACPI for this.
Great. As soon as all boards have Kconfig support I think that should be done.
Thanks, Myles
Myles Watson wrote:
Absolutely agreed. I think there will have to be another variable like HAS_ACPI_SUPPORT for that to happen.
How about simply ACPI?
I think HAVE_ACPI_TABLES should become GENERATE_ACPI_TABLES
I like that!
and HAVE_ACPI_TABLES should take that new meaning. ACPI isn't specific enough to see what it does without looking elsewhere.
All right.
By the way - maybe we too should store big static tables in cbfs?
//Peter
By the way - maybe we too should store big static tables in cbfs?
I'm don't think ACPI is static enough. On my board the DSDT (3K) is the only static one. I'm not sure it's worth the trouble. I could be proven wrong.
Thanks, Myles
Myles Watson wrote:
By the way - maybe we too should store big static tables in cbfs?
I'm don't think ACPI is static enough. On my board the DSDT (3K) is the only static one. I'm not sure it's worth the trouble. I could be proven wrong.
I agree with you,.. it's not a big win either.
Stefan
This is all the output I get on the serial port. How can I get a full log?
If you set CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
You may get some more useful information.
Thanks, Myles
looking better.
Did I miss something? I don't see seabios in there.
ron