Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/707
-gerrit
commit bdab48d3f13d117bd1100be616837e6d1dbb55fc Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Mon Mar 5 09:25:12 2012 +0200
Fix address of IDT in real-mode entry
In a case of CS & 0x0fff != 0x0, lidt memory operand does not point to nullidt, this can raise an exception and shutdown the CPU.
When an AP CPU receives 8-bit Start-Up IPI vector yzH, it starts execute at physical address 000yz000H. Seems this translates to either yz00:0000 or y000:z000 (CS:IP), depending of the CPU model. With the change entry16.inc is relocatable as the commentary suggests and can be used as ap_sipi_vector on SMP systems.
Change-Id: I885a2888179700ba6e2b11d4f2d6a64ddea4c2dc Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/cpu/x86/16bit/entry16.inc | 15 ++++++++------- 1 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 0fa8c11..e4613bf 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -57,13 +57,6 @@ _start: * entry16.inc. */
- /* Load an IDT with NULL limit to prevent the 16bit IDT being used - * in protected mode before c_start.S sets up a 32bit IDT when entering - * ram stage. - */ - movw $nullidt_offset, %bx - lidt %cs:(%bx) - /* Note: gas handles memory addresses in 16 bit code very poorly. * In particular it doesn't appear to have a directive allowing you * associate a section or even an absolute offset with a segment register. @@ -98,10 +91,18 @@ _start: * the low 16 bits. This means that the intial segment used * when start is called must be 64K aligned. This should not * restrict the address as the ip address can be anything. + * + * Also load an IDT with NULL limit to prevent the 16bit IDT being used + * in protected mode before c_start.S sets up a 32bit IDT when entering + * ram stage. In practise: CPU will shutdown on any exception. + * See IA32 manual Vol 3A 19.26 Interrupts. */
movw %cs, %ax shlw $4, %ax + movw $nullidt_offset, %bx + subw %ax, %bx + lidt %cs:(%bx) movw $gdtptr16_offset, %bx subw %ax, %bx data32 lgdt %cs:(%bx)
Kyösti Mälkki wrote:
commit bdab48d3f13d117bd1100be616837e6d1dbb55fc Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Mon Mar 5 09:25:12 2012 +0200
Fix address of IDT in real-mode entry
Was this tested not to cause regression?
//Peter
On Tue, 2012-03-06 at 03:59 +0100, Peter Stuge wrote:
Kyösti Mälkki wrote:
commit bdab48d3f13d117bd1100be616837e6d1dbb55fc Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Mon Mar 5 09:25:12 2012 +0200
Fix address of IDT in real-mode entryWas this tested not to cause regression?
1. Tested as a fix to boot AP CPU on a hyper-threaded Intel P4 models f29 and f49.
2. Tested to cause no regression to boot a non-hyper-threaded Intel P4 CPU model f27 on the same platform as #1 testing.
3. Tested to cause no regression to boot AP CPUs on an Intel P4 Xeon platform with dual socket604 and hyper-threaded model f25 CPUs. The patch was not required for this platform to boot.
I have no possibility to test other platforms, so any feedback with AMDs and VIAs is much appreciated.
For these tests, I considered it as a "fix" or "no regression" if romstage executed with proper console output. Idwer Vollering proceeded with the tests #1 and #2 for me on a platform with no supported memory controller.
Test #3 is the A-Open board [1]. Gerrit version is outdated, I have postponed updates for that until all the dependencies are merged.
Thanks, KM
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Kyösti Mälkki -
Kyösti Mälkki -
Peter Stuge