Hello: Everyone, the code of rs780 refers to CIM several times. For example, "In CIMx 4.5.0 and RPR, 4c is done before 5 & 6. But in this way", "Compliant with CIM_33's PCIEPowerOffGppPorts", etc.
Does CIM means Common Information Model of DMTF? But I can't find the part about rs780.
Anyone konw about it? thanks.
Dear yili0568,
Am Dienstag, den 09.04.2013, 16:02 +0800 schrieb yili0568@gmail.com:
Everyone, the code of rs780 refers to CIM several times. Forexample, "In CIMx 4.5.0 and RPR, 4c is done before 5 & 6. But in this way", "Compliant with CIM_33's PCIEPowerOffGppPorts", etc.
Does CIM means Common Information Model of DMTF? But I can't find the part about rs780.
Anyone know about it? thanks.
CIMx means »Chipset Integration Module Extensive« and should be described in the datasheet [1]. At least I found it in the AMD SB800-Series BIOS Developers Guide (BDG).
Could you please apply for a Wiki account and add it to the Glossary [2]?
Thanks,
Paul
[1] http://www.coreboot.org/Datasheets [2] http://www.coreboot.org/Glossary
Thanks. And I found the comment "/* * Set registers in RS780 and CPU to enable the internal GFX. * Please refer to CIM source code and BKDG. */" from the file Targets/Bonito3a780e/pci/rs780_gfx.c, where is CIM source code?
On Tue, Apr 09, 2013 at 12:43:30PM +0200, Paul Menzel wrote:
Dear yili0568,
Am Dienstag, den 09.04.2013, 16:02 +0800 schrieb yili0568@gmail.com:
Everyone, the code of rs780 refers to CIM several times. Forexample, "In CIMx 4.5.0 and RPR, 4c is done before 5 & 6. But in this way", "Compliant with CIM_33's PCIEPowerOffGppPorts", etc.
Does CIM means Common Information Model of DMTF? But I can't find the part about rs780.
Anyone know about it? thanks.
CIMx means »Chipset Integration Module Extensive« and should be described in the datasheet [1]. At least I found it in the AMD SB800-Series BIOS Developers Guide (BDG).
Could you please apply for a Wiki account and add it to the Glossary [2]?
Thanks,
Paul
[1] http://www.coreboot.org/Datasheets [2] http://www.coreboot.org/Glossary
-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Dear yili0568,
please do not top post but use interleaved style instead [1].
Am Mittwoch, den 10.04.2013, 15:04 +0800 schrieb yili0568@gmail.com:
Thanks. And I found the comment "/*
- Set registers in RS780 and CPU to enable the internal GFX.
- Please refer to CIM source code and BKDG.
*/" from the file Targets/Bonito3a780e/pci/rs780_gfx.c,
Where do you get this source tree from? It does not look like our upstream coreboot tree? Searching for »Bonito3a780e«, do you develop a Lemote device [2][3]? This is great news when this is true and Lemote is using coreboot!
where is CIM source code?
$ find . -type d -iname '*cim*' ./src/northbridge/amd/cimx ./src/southbridge/amd/cimx ./src/vendorcode/amd/cimx ./build/southbridge/amd/cimx ./build/vendorcode/amd/cimx $ ls src/southbridge/amd/cimx/ cimx_util.c cimx_util.h Kconfig Makefile.inc sb700 sb800 sb900
[1] http://en.opensuse.org/openSUSE:Mailing_list_netiquette [2] http://dev.lemote.com/cgit/pmon.git/tree/Targets/Bonito3a780e/conf/files.Bon... [3] http://dev.lemote.com/cgit/pmon.git/tree/Targets/
On Wed, Apr 10, 2013 at 09:37:34AM +0200, Paul Menzel wrote:
Dear yili0568,
please do not top post but use interleaved style instead [1].
I'm sorry.
Am Mittwoch, den 10.04.2013, 15:04 +0800 schrieb yili0568@gmail.com:
Thanks. And I found the comment "/*
- Set registers in RS780 and CPU to enable the internal GFX.
- Please refer to CIM source code and BKDG.
*/" from the file Targets/Bonito3a780e/pci/rs780_gfx.c,
Where do you get this source tree from? It does not look like our upstream coreboot tree? Searching for »Bonito3a780e«, do you develop a Lemote device [2][3]? This is great news when this is true and Lemote is using coreboot!
Both lemote and loongson[1] is using pmon, in which a lot of codes ported from coreboot.
where is CIM source code?
$ find . -type d -iname '*cim*' ./src/northbridge/amd/cimx ./src/southbridge/amd/cimx ./src/vendorcode/amd/cimx ./build/southbridge/amd/cimx ./build/vendorcode/amd/cimx $ ls src/southbridge/amd/cimx/ cimx_util.c cimx_util.h Kconfig Makefile.inc sb700 sb800 sb900
[1] http://en.opensuse.org/openSUSE:Mailing_list_netiquette [2] http://dev.lemote.com/cgit/pmon.git/tree/Targets/Bonito3a780e/conf/files.Bon... [3] http://dev.lemote.com/cgit/pmon.git/tree/Targets/
Thanks, I've find the cimx, and there is another question. I've configured the rs780e's gfx as 2 x8 bridges(dev2 and dev3 of bus0), after link trained both dev2 and dev3 are x8.
From the function PcieTrainPort:
case 0x06: /* read back current link width [6:4]. */ current_link_width = (nbpcie_p_read_index(dev, 0xA2) >> 4) & 0x7; /* 4 means 7:4 and 15:12 * 3 means 7:2 and 15:10 * 2 means 7:1 and 15:9 * egnoring the reversal case */ lane_mask = (0xFF << (current_link_width - 2) * 2) & 0xFF; reg = nbpcie_ind_read_index(nb_dev, 0x65 | gfx_gpp_sb_sel); reg |= lane_mask << 8 | lane_mask; reg = 0xE0E0; /* TODO: See the comments in rs780_pcie.c, at about line 145. */ nbpcie_ind_write_index(nb_dev, 0x65 | gfx_gpp_sb_sel, reg); printk(BIOS_DEBUG, "link_width=%x, lane_mask=%x", current_link_width, lane_mask); set_pcie_reset(); mdelay(1); set_pcie_dereset(); break;
I've print the current_link_width, both dev2 and dev3 print 4. Does 4 means x8? Then I boot linux lspci -vvv 00:02.0 ...... LnkCap: Port #0, Speed 5GT/s, Width x8,...... ...... LnkSta: Speed 2.5GT/s, Width x2,......
It is the same to the dev3. The cb file is from src/mainboard/amd/mahogany_fam10/devicetree.cb
Do you know about the link tranning of gfx of rs780e? Thanks.
[1] http://www.loongson.cn/dev/gitweb/?p=pmon-loongson3;a=summary
Am Mittwoch, den 10.04.2013, 16:36 +0800 schrieb yili0568@gmail.com:
On Wed, Apr 10, 2013 at 09:37:34AM +0200, Paul Menzel wrote:
please do not top post but use interleaved style instead [1].
I'm sorry.
No problem. Thank you for now following the netiquette!
Am Mittwoch, den 10.04.2013, 15:04 +0800 schrieb yili0568@gmail.com:
Thanks. And I found the comment "/*
- Set registers in RS780 and CPU to enable the internal GFX.
- Please refer to CIM source code and BKDG.
*/" from the file Targets/Bonito3a780e/pci/rs780_gfx.c,
Where do you get this source tree from? It does not look like our upstream coreboot tree? Searching for »Bonito3a780e«, do you develop a Lemote device [2][3]? This is great news when this is true and Lemote is using coreboot!
Both lemote and loongson[4] is using pmon, in which a lot of codes ported from coreboot.
Interesting. Thank you for the information. I would be even happier if they used coreboot directly, so only one code base would need to be maintained and coreboot would of course benefit from more contributors. If you know the Lemote folks please lobby for that idea. ;-)
where is CIM source code?
$ find . -type d -iname '*cim*' ./src/northbridge/amd/cimx ./src/southbridge/amd/cimx ./src/vendorcode/amd/cimx ./build/southbridge/amd/cimx ./build/vendorcode/amd/cimx $ ls src/southbridge/amd/cimx/ cimx_util.c cimx_util.h Kconfig Makefile.inc sb700 sb800 sb900
[1] http://en.opensuse.org/openSUSE:Mailing_list_netiquette [2] http://dev.lemote.com/cgit/pmon.git/tree/Targets/Bonito3a780e/conf/files.Bon... [3] http://dev.lemote.com/cgit/pmon.git/tree/Targets/
Thanks, I've find the cimx, and there is another question. I've configured the rs780e's gfx as 2 x8 bridges(dev2 and dev3 of bus0), after link trained both dev2 and dev3 are x8.
From the function PcieTrainPort: case 0x06: /* read back current link width [6:4]. */ current_link_width = (nbpcie_p_read_index(dev, 0xA2) >> 4) & 0x7; /* 4 means 7:4 and 15:12 * 3 means 7:2 and 15:10 * 2 means 7:1 and 15:9 * egnoring the reversal case */ lane_mask = (0xFF << (current_link_width - 2) * 2) & 0xFF; reg = nbpcie_ind_read_index(nb_dev, 0x65 | gfx_gpp_sb_sel); reg |= lane_mask << 8 | lane_mask; reg = 0xE0E0; /* TODO: See the comments in rs780_pcie.c, at about line 145. */ nbpcie_ind_write_index(nb_dev, 0x65 | gfx_gpp_sb_sel, reg); printk(BIOS_DEBUG, "link_width=%x, lane_mask=%x", current_link_width, lane_mask); set_pcie_reset(); mdelay(1); set_pcie_dereset(); break;
I've print the current_link_width, both dev2 and dev3 print 4. Does 4 means x8?
I do not know. I guess so, but you need to look that up in the datasheet to be sure I guess.
Then I boot linux lspci -vvv
By the way, you can pass the -s (show) switch to lspci to limit the list of shown devices, so `sudo lspci -s 00:02.0 -vvv` in this case. (The `sudo` is a note to myself to run that command with root priviledges as I always forget this and wonder why I do not get the whole output.)
00:02.0 ...... LnkCap: Port #0, Speed 5GT/s, Width x8,...... ...... LnkSta: Speed 2.5GT/s, Width x2,......
It is the same to the dev3. The cb file is from src/mainboard/amd/mahogany_fam10/devicetree.cb
Do you know about the link training of gfx of rs780e? Thanks.
Unfortunately I do not. Maybe some other coreboot developer is able to help you. For example the ASRock 939A785GMH uses the AMD RS780 southbridge.
Thanks,
Paul
[4] http://www.loongson.cn/dev/gitweb/?p=pmon-loongson3;a=summary
-
Paul Menzel -
yili0568＠gmail.com