[commit] r5167 - in trunk/src: mainboard/asus/mew-am mainboard/asus/mew-vm mainboard/dell/s1850 mainboard/digitallogic/adl855pc mainboard/hp/e_vectra_p2706t mainboard/intel/jarrell mainboard/intel/...
Author: stepan Date: Sat Feb 27 02:50:21 2010 New Revision: 5167 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5167
Log: This does the following:
cd coreboot/src/southbridge svn mv i82801ca i82801cx svn mv i82801dbm i82801dx svn mv i82801er i82801ex svn copy i82801xx i82801bx svn mv i82801xx i82801ax
Plus, fixing up the filenames in these directories and the romstage.c and Kconfig files of the mainboards using those drivers. Plus, switching the thomson ip1000 and rca rm4100 to the i82801dx driver.
There's a lot more to be done, like - adding device IDs for the ICH3 and newer drivers that have been kept in i82801xx so far - drop the additional parts support from the ax and bx drivers.
Signed-off-by: Stefan Reinauer stepan@coresystems.de Acked-by: Uwe Hermann uwe@hermann-uwe.de Acked-by: Joseph Smith joe@settoplinux.org
Added: trunk/src/southbridge/intel/i82801ax/ - copied from r5166, trunk/src/southbridge/intel/i82801xx/ trunk/src/southbridge/intel/i82801ax/i82801ax.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx.c trunk/src/southbridge/intel/i82801ax/i82801ax.h - copied, changed from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx.h trunk/src/southbridge/intel/i82801ax/i82801ax_ac97.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_ac97.c trunk/src/southbridge/intel/i82801ax/i82801ax_early_lpc.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c trunk/src/southbridge/intel/i82801ax/i82801ax_ide.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_ide.c trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_lpc.c trunk/src/southbridge/intel/i82801ax/i82801ax_nic.c - copied unchanged from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_nic.c trunk/src/southbridge/intel/i82801ax/i82801ax_pci.c - copied unchanged from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_pci.c trunk/src/southbridge/intel/i82801ax/i82801ax_reset.c - copied unchanged from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_reset.c trunk/src/southbridge/intel/i82801ax/i82801ax_sata.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_sata.c trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_smbus.c trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h - copied unchanged from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_smbus.h trunk/src/southbridge/intel/i82801ax/i82801ax_usb.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_usb.c trunk/src/southbridge/intel/i82801ax/i82801ax_usb_ehci.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c trunk/src/southbridge/intel/i82801ax/i82801ax_watchdog.c - copied unchanged from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_watchdog.c trunk/src/southbridge/intel/i82801bx/ - copied from r5166, trunk/src/southbridge/intel/i82801xx/ trunk/src/southbridge/intel/i82801bx/i82801bx.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx.c trunk/src/southbridge/intel/i82801bx/i82801bx.h - copied, changed from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx.h trunk/src/southbridge/intel/i82801bx/i82801bx_ac97.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_ac97.c trunk/src/southbridge/intel/i82801bx/i82801bx_early_lpc.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c trunk/src/southbridge/intel/i82801bx/i82801bx_ide.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_ide.c trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_lpc.c trunk/src/southbridge/intel/i82801bx/i82801bx_nic.c - copied unchanged from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_nic.c trunk/src/southbridge/intel/i82801bx/i82801bx_pci.c - copied unchanged from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_pci.c trunk/src/southbridge/intel/i82801bx/i82801bx_reset.c - copied unchanged from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_reset.c trunk/src/southbridge/intel/i82801bx/i82801bx_sata.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_sata.c trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_smbus.c trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h - copied unchanged from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_smbus.h trunk/src/southbridge/intel/i82801bx/i82801bx_usb.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_usb.c trunk/src/southbridge/intel/i82801bx/i82801bx_usb_ehci.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c trunk/src/southbridge/intel/i82801bx/i82801bx_watchdog.c - copied unchanged from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_watchdog.c trunk/src/southbridge/intel/i82801cx/ - copied from r5166, trunk/src/southbridge/intel/i82801ca/ trunk/src/southbridge/intel/i82801cx/i82801cx.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801ca/i82801ca.c trunk/src/southbridge/intel/i82801cx/i82801cx.h - copied, changed from r5166, trunk/src/southbridge/intel/i82801ca/i82801ca.h trunk/src/southbridge/intel/i82801cx/i82801cx_ac97.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801ca/i82801ca_ac97.c trunk/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c trunk/src/southbridge/intel/i82801cx/i82801cx_ide.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801ca/i82801ca_ide.c trunk/src/southbridge/intel/i82801cx/i82801cx_lpc.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801ca/i82801ca_lpc.c trunk/src/southbridge/intel/i82801cx/i82801cx_nic.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801ca/i82801ca_nic.c trunk/src/southbridge/intel/i82801cx/i82801cx_pci.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801ca/i82801ca_pci.c trunk/src/southbridge/intel/i82801cx/i82801cx_reset.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801ca/i82801ca_reset.c trunk/src/southbridge/intel/i82801cx/i82801cx_smbus.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801ca/i82801ca_smbus.c trunk/src/southbridge/intel/i82801cx/i82801cx_usb.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801ca/i82801ca_usb.c trunk/src/southbridge/intel/i82801dx/ - copied from r5166, trunk/src/southbridge/intel/i82801dbm/ trunk/src/southbridge/intel/i82801dx/i82801dx.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm.c trunk/src/southbridge/intel/i82801dx/i82801dx.h - copied, changed from r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm.h trunk/src/southbridge/intel/i82801dx/i82801dx_ac97.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm_ac97.c trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c trunk/src/southbridge/intel/i82801dx/i82801dx_ide.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm_ide.c trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c trunk/src/southbridge/intel/i82801dx/i82801dx_nic.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm_nic.c trunk/src/southbridge/intel/i82801dx/i82801dx_pci.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm_pci.c trunk/src/southbridge/intel/i82801dx/i82801dx_reset.c - copied unchanged from r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm_reset.c trunk/src/southbridge/intel/i82801dx/i82801dx_sata.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm_sata.c trunk/src/southbridge/intel/i82801dx/i82801dx_smbus.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm_smbus.c trunk/src/southbridge/intel/i82801dx/i82801dx_usb.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm_usb.c trunk/src/southbridge/intel/i82801dx/i82801dx_usb2.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm_usb2.c trunk/src/southbridge/intel/i82801ex/ - copied from r5166, trunk/src/southbridge/intel/i82801er/ trunk/src/southbridge/intel/i82801ex/i82801ex.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801er/i82801er.c trunk/src/southbridge/intel/i82801ex/i82801ex.h - copied, changed from r5166, trunk/src/southbridge/intel/i82801er/i82801er.h trunk/src/southbridge/intel/i82801ex/i82801ex_ac97.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801er/i82801er_ac97.c trunk/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801er/i82801er_early_smbus.c trunk/src/southbridge/intel/i82801ex/i82801ex_ehci.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801er/i82801er_ehci.c trunk/src/southbridge/intel/i82801ex/i82801ex_ide.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801er/i82801er_ide.c trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801er/i82801er_lpc.c trunk/src/southbridge/intel/i82801ex/i82801ex_pci.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801er/i82801er_pci.c trunk/src/southbridge/intel/i82801ex/i82801ex_reset.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801er/i82801er_reset.c trunk/src/southbridge/intel/i82801ex/i82801ex_sata.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801er/i82801er_sata.c trunk/src/southbridge/intel/i82801ex/i82801ex_smbus.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801er/i82801er_smbus.c trunk/src/southbridge/intel/i82801ex/i82801ex_smbus.h - copied unchanged from r5166, trunk/src/southbridge/intel/i82801er/i82801er_smbus.h trunk/src/southbridge/intel/i82801ex/i82801ex_uhci.c - copied, changed from r5166, trunk/src/southbridge/intel/i82801er/i82801er_uhci.c trunk/src/southbridge/intel/i82801ex/i82801ex_watchdog.c - copied unchanged from r5166, trunk/src/southbridge/intel/i82801er/i82801er_watchdog.c Deleted: trunk/src/southbridge/intel/i82801ax/i82801xx.c trunk/src/southbridge/intel/i82801ax/i82801xx.h trunk/src/southbridge/intel/i82801ax/i82801xx_ac97.c trunk/src/southbridge/intel/i82801ax/i82801xx_early_lpc.c trunk/src/southbridge/intel/i82801ax/i82801xx_early_smbus.c trunk/src/southbridge/intel/i82801ax/i82801xx_ide.c trunk/src/southbridge/intel/i82801ax/i82801xx_lpc.c trunk/src/southbridge/intel/i82801ax/i82801xx_nic.c trunk/src/southbridge/intel/i82801ax/i82801xx_pci.c trunk/src/southbridge/intel/i82801ax/i82801xx_reset.c trunk/src/southbridge/intel/i82801ax/i82801xx_sata.c trunk/src/southbridge/intel/i82801ax/i82801xx_smbus.c trunk/src/southbridge/intel/i82801ax/i82801xx_smbus.h trunk/src/southbridge/intel/i82801ax/i82801xx_usb.c trunk/src/southbridge/intel/i82801ax/i82801xx_usb_ehci.c trunk/src/southbridge/intel/i82801ax/i82801xx_watchdog.c trunk/src/southbridge/intel/i82801bx/i82801xx.c trunk/src/southbridge/intel/i82801bx/i82801xx.h trunk/src/southbridge/intel/i82801bx/i82801xx_ac97.c trunk/src/southbridge/intel/i82801bx/i82801xx_early_lpc.c trunk/src/southbridge/intel/i82801bx/i82801xx_early_smbus.c trunk/src/southbridge/intel/i82801bx/i82801xx_ide.c trunk/src/southbridge/intel/i82801bx/i82801xx_lpc.c trunk/src/southbridge/intel/i82801bx/i82801xx_nic.c trunk/src/southbridge/intel/i82801bx/i82801xx_pci.c trunk/src/southbridge/intel/i82801bx/i82801xx_reset.c trunk/src/southbridge/intel/i82801bx/i82801xx_sata.c trunk/src/southbridge/intel/i82801bx/i82801xx_smbus.c trunk/src/southbridge/intel/i82801bx/i82801xx_smbus.h trunk/src/southbridge/intel/i82801bx/i82801xx_usb.c trunk/src/southbridge/intel/i82801bx/i82801xx_usb_ehci.c trunk/src/southbridge/intel/i82801bx/i82801xx_watchdog.c trunk/src/southbridge/intel/i82801ca/ trunk/src/southbridge/intel/i82801cx/i82801ca.c trunk/src/southbridge/intel/i82801cx/i82801ca.h trunk/src/southbridge/intel/i82801cx/i82801ca_ac97.c trunk/src/southbridge/intel/i82801cx/i82801ca_early_smbus.c trunk/src/southbridge/intel/i82801cx/i82801ca_ide.c trunk/src/southbridge/intel/i82801cx/i82801ca_lpc.c trunk/src/southbridge/intel/i82801cx/i82801ca_nic.c trunk/src/southbridge/intel/i82801cx/i82801ca_pci.c trunk/src/southbridge/intel/i82801cx/i82801ca_reset.c trunk/src/southbridge/intel/i82801cx/i82801ca_smbus.c trunk/src/southbridge/intel/i82801cx/i82801ca_usb.c trunk/src/southbridge/intel/i82801dbm/ trunk/src/southbridge/intel/i82801dx/i82801dbm.c trunk/src/southbridge/intel/i82801dx/i82801dbm.h trunk/src/southbridge/intel/i82801dx/i82801dbm_ac97.c trunk/src/southbridge/intel/i82801dx/i82801dbm_early_smbus.c trunk/src/southbridge/intel/i82801dx/i82801dbm_ide.c trunk/src/southbridge/intel/i82801dx/i82801dbm_lpc.c trunk/src/southbridge/intel/i82801dx/i82801dbm_nic.c trunk/src/southbridge/intel/i82801dx/i82801dbm_pci.c trunk/src/southbridge/intel/i82801dx/i82801dbm_reset.c trunk/src/southbridge/intel/i82801dx/i82801dbm_sata.c trunk/src/southbridge/intel/i82801dx/i82801dbm_smbus.c trunk/src/southbridge/intel/i82801dx/i82801dbm_usb.c trunk/src/southbridge/intel/i82801dx/i82801dbm_usb2.c trunk/src/southbridge/intel/i82801er/ trunk/src/southbridge/intel/i82801ex/i82801er.c trunk/src/southbridge/intel/i82801ex/i82801er.h trunk/src/southbridge/intel/i82801ex/i82801er_ac97.c trunk/src/southbridge/intel/i82801ex/i82801er_early_smbus.c trunk/src/southbridge/intel/i82801ex/i82801er_ehci.c trunk/src/southbridge/intel/i82801ex/i82801er_ide.c trunk/src/southbridge/intel/i82801ex/i82801er_lpc.c trunk/src/southbridge/intel/i82801ex/i82801er_pci.c trunk/src/southbridge/intel/i82801ex/i82801er_reset.c trunk/src/southbridge/intel/i82801ex/i82801er_sata.c trunk/src/southbridge/intel/i82801ex/i82801er_smbus.c trunk/src/southbridge/intel/i82801ex/i82801er_smbus.h trunk/src/southbridge/intel/i82801ex/i82801er_uhci.c trunk/src/southbridge/intel/i82801ex/i82801er_watchdog.c trunk/src/southbridge/intel/i82801xx/ Modified: trunk/src/mainboard/asus/mew-am/Kconfig trunk/src/mainboard/asus/mew-am/devicetree.cb trunk/src/mainboard/asus/mew-am/romstage.c trunk/src/mainboard/asus/mew-vm/Kconfig trunk/src/mainboard/asus/mew-vm/devicetree.cb trunk/src/mainboard/asus/mew-vm/romstage.c trunk/src/mainboard/dell/s1850/Kconfig trunk/src/mainboard/dell/s1850/devicetree.cb trunk/src/mainboard/dell/s1850/romstage.c trunk/src/mainboard/digitallogic/adl855pc/Kconfig trunk/src/mainboard/digitallogic/adl855pc/devicetree.cb trunk/src/mainboard/digitallogic/adl855pc/romstage.c trunk/src/mainboard/hp/e_vectra_p2706t/Kconfig trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c trunk/src/mainboard/intel/jarrell/Kconfig trunk/src/mainboard/intel/jarrell/devicetree.cb trunk/src/mainboard/intel/jarrell/romstage.c trunk/src/mainboard/intel/xe7501devkit/Kconfig trunk/src/mainboard/intel/xe7501devkit/devicetree.cb trunk/src/mainboard/intel/xe7501devkit/failover.c trunk/src/mainboard/intel/xe7501devkit/reset.c trunk/src/mainboard/intel/xe7501devkit/romstage.c trunk/src/mainboard/mitac/6513wu/Kconfig trunk/src/mainboard/mitac/6513wu/devicetree.cb trunk/src/mainboard/mitac/6513wu/romstage.c trunk/src/mainboard/msi/ms6178/Kconfig trunk/src/mainboard/msi/ms6178/devicetree.cb trunk/src/mainboard/msi/ms6178/romstage.c trunk/src/mainboard/nec/powermate2000/Kconfig trunk/src/mainboard/nec/powermate2000/devicetree.cb trunk/src/mainboard/nec/powermate2000/romstage.c trunk/src/mainboard/rca/rm4100/Kconfig trunk/src/mainboard/rca/rm4100/devicetree.cb trunk/src/mainboard/rca/rm4100/gpio.c trunk/src/mainboard/rca/rm4100/romstage.c trunk/src/mainboard/supermicro/x6dhe_g2/Kconfig trunk/src/mainboard/supermicro/x6dhe_g2/devicetree.cb trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig/Kconfig trunk/src/mainboard/supermicro/x6dhr_ig/devicetree.cb trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig2/Kconfig trunk/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c trunk/src/mainboard/thomson/ip1000/Kconfig trunk/src/mainboard/thomson/ip1000/devicetree.cb trunk/src/mainboard/thomson/ip1000/gpio.c trunk/src/mainboard/thomson/ip1000/romstage.c trunk/src/mainboard/tyan/s2735/Kconfig trunk/src/mainboard/tyan/s2735/devicetree.cb trunk/src/mainboard/tyan/s2735/reset.c trunk/src/mainboard/tyan/s2735/romstage.c trunk/src/southbridge/intel/Kconfig trunk/src/southbridge/intel/Makefile.inc trunk/src/southbridge/intel/i82801ax/Kconfig trunk/src/southbridge/intel/i82801ax/Makefile.inc trunk/src/southbridge/intel/i82801ax/chip.h trunk/src/southbridge/intel/i82801ax/cmos_failover.c trunk/src/southbridge/intel/i82801bx/Kconfig trunk/src/southbridge/intel/i82801bx/Makefile.inc trunk/src/southbridge/intel/i82801bx/chip.h trunk/src/southbridge/intel/i82801bx/cmos_failover.c trunk/src/southbridge/intel/i82801cx/Kconfig trunk/src/southbridge/intel/i82801cx/Makefile.inc trunk/src/southbridge/intel/i82801cx/chip.h trunk/src/southbridge/intel/i82801cx/cmos_failover.c trunk/src/southbridge/intel/i82801dx/Kconfig trunk/src/southbridge/intel/i82801dx/Makefile.inc trunk/src/southbridge/intel/i82801dx/chip.h trunk/src/southbridge/intel/i82801ex/Kconfig trunk/src/southbridge/intel/i82801ex/Makefile.inc trunk/src/southbridge/intel/i82801ex/chip.h
Modified: trunk/src/mainboard/asus/mew-am/Kconfig ============================================================================== --- trunk/src/mainboard/asus/mew-am/Kconfig Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/asus/mew-am/Kconfig Sat Feb 27 02:50:21 2010 (r5167) @@ -23,7 +23,7 @@ select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801XX + select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_SMSCSUPERIO select ROMCC select HAVE_PIRQ_TABLE
Modified: trunk/src/mainboard/asus/mew-am/devicetree.cb ============================================================================== --- trunk/src/mainboard/asus/mew-am/devicetree.cb Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/asus/mew-am/devicetree.cb Sat Feb 27 02:50:21 2010 (r5167) @@ -7,7 +7,7 @@ device pci_domain 0 on # PCI domain device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) device pci 1.0 on end # Chipset Graphics Controller (CGC) - chip southbridge/intel/i82801xx # Southbridge + chip southbridge/intel/i82801ax # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1"
Modified: trunk/src/mainboard/asus/mew-am/romstage.c ============================================================================== --- trunk/src/mainboard/asus/mew-am/romstage.c Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/asus/mew-am/romstage.c Sat Feb 27 02:50:21 2010 (r5167) @@ -31,7 +31,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c"
Modified: trunk/src/mainboard/asus/mew-vm/Kconfig ============================================================================== --- trunk/src/mainboard/asus/mew-vm/Kconfig Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/asus/mew-vm/Kconfig Sat Feb 27 02:50:21 2010 (r5167) @@ -23,7 +23,7 @@ select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801XX + select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_LPC47B272 select ROMCC select HAVE_PIRQ_TABLE
Modified: trunk/src/mainboard/asus/mew-vm/devicetree.cb ============================================================================== --- trunk/src/mainboard/asus/mew-vm/devicetree.cb Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/asus/mew-vm/devicetree.cb Sat Feb 27 02:50:21 2010 (r5167) @@ -4,7 +4,7 @@ device pci 1.0 on # Onboard Video # device pci 1.0 on end end - chip southbridge/intel/i82801xx # Southbridge + chip southbridge/intel/i82801ax # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1"
Modified: trunk/src/mainboard/asus/mew-vm/romstage.c ============================================================================== --- trunk/src/mainboard/asus/mew-vm/romstage.c Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/asus/mew-vm/romstage.c Sat Feb 27 02:50:21 2010 (r5167) @@ -38,7 +38,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1)
-#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c"
Modified: trunk/src/mainboard/dell/s1850/Kconfig ============================================================================== --- trunk/src/mainboard/dell/s1850/Kconfig Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/dell/s1850/Kconfig Sat Feb 27 02:50:21 2010 (r5167) @@ -3,7 +3,7 @@ select ARCH_X86 select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7520 - select SOUTHBRIDGE_INTEL_I82801ER + select SOUTHBRIDGE_INTEL_I82801EX select SOUTHBRIDGE_INTEL_PXHD select SUPERIO_NSC_PC8374 select ROMCC
Modified: trunk/src/mainboard/dell/s1850/devicetree.cb ============================================================================== --- trunk/src/mainboard/dell/s1850/devicetree.cb Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/dell/s1850/devicetree.cb Sat Feb 27 02:50:21 2010 (r5167) @@ -1,6 +1,6 @@ chip northbridge/intel/e7520 # mch device pci_domain 0 on - chip southbridge/intel/i82801er # i82801er + chip southbridge/intel/i82801ex # i82801er # USB ports device pci 1d.0 on end device pci 1d.1 on end
Modified: trunk/src/mainboard/dell/s1850/romstage.c ============================================================================== --- trunk/src/mainboard/dell/s1850/romstage.c Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/dell/s1850/romstage.c Sat Feb 27 02:50:21 2010 (r5167) @@ -12,7 +12,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801er/i82801er_early_smbus.c" +#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc8374/pc8374_early_init.c" #include "cpu/x86/lapic/boot_cpu.c"
Modified: trunk/src/mainboard/digitallogic/adl855pc/Kconfig ============================================================================== --- trunk/src/mainboard/digitallogic/adl855pc/Kconfig Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/digitallogic/adl855pc/Kconfig Sat Feb 27 02:50:21 2010 (r5167) @@ -3,7 +3,7 @@ select ARCH_X86 select CPU_INTEL_SOCKET_MPGA479M select NORTHBRIDGE_INTEL_I855 - select SOUTHBRIDGE_INTEL_I82801DBM + select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_WINBOND_W83627HF select ROMCC select HAVE_PIRQ_TABLE
Modified: trunk/src/mainboard/digitallogic/adl855pc/devicetree.cb ============================================================================== --- trunk/src/mainboard/digitallogic/adl855pc/devicetree.cb Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/digitallogic/adl855pc/devicetree.cb Sat Feb 27 02:50:21 2010 (r5167) @@ -2,7 +2,7 @@ device pci_domain 0 on device pci 0.0 on end device pci 1.0 on end - chip southbridge/intel/i82801dbm + chip southbridge/intel/i82801dx # pci 11.0 on end # pci 11.1 on end # pci 11.2 on end
Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/adl855pc/romstage.c Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/digitallogic/adl855pc/romstage.c Sat Feb 27 02:50:21 2010 (r5167) @@ -16,7 +16,8 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801dbm/i82801dbm_early_smbus.c" +#include "southbridge/intel/i82801dx/i82801dx.h" +#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c" #include "northbridge/intel/i855/raminit.h"
#if 0
Modified: trunk/src/mainboard/hp/e_vectra_p2706t/Kconfig ============================================================================== --- trunk/src/mainboard/hp/e_vectra_p2706t/Kconfig Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/hp/e_vectra_p2706t/Kconfig Sat Feb 27 02:50:21 2010 (r5167) @@ -26,7 +26,7 @@ select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801XX + select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_NSC_PC87360 select ROMCC select HAVE_PIRQ_TABLE
Modified: trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb ============================================================================== --- trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb Sat Feb 27 02:50:21 2010 (r5167) @@ -8,7 +8,7 @@ device pci_domain 0 on device pci 0.0 on end # Host bridge device pci 1.0 on end # Onboard VGA - chip southbridge/intel/i82801xx # Southbridge + chip southbridge/intel/i82801ax # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1"
Modified: trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c ============================================================================== --- trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c Sat Feb 27 02:50:21 2010 (r5167) @@ -37,7 +37,7 @@ #include "northbridge/intel/i82810/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" -#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "pc80/udelay_io.c" #include "lib/debug.c" #include "northbridge/intel/i82810/raminit.c"
Modified: trunk/src/mainboard/intel/jarrell/Kconfig ============================================================================== --- trunk/src/mainboard/intel/jarrell/Kconfig Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/intel/jarrell/Kconfig Sat Feb 27 02:50:21 2010 (r5167) @@ -4,7 +4,7 @@ select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7520 select SOUTHBRIDGE_INTEL_PXHD - select SOUTHBRIDGE_INTEL_I82801ER + select SOUTHBRIDGE_INTEL_I82801EX select SUPERIO_NSC_PC87427 select ROMCC select HAVE_PIRQ_TABLE
Modified: trunk/src/mainboard/intel/jarrell/devicetree.cb ============================================================================== --- trunk/src/mainboard/intel/jarrell/devicetree.cb Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/intel/jarrell/devicetree.cb Sat Feb 27 02:50:21 2010 (r5167) @@ -17,7 +17,7 @@ end end device pci 06.0 on end - chip southbridge/intel/i82801er # i82801er + chip southbridge/intel/i82801ex # i82801er device pci 1d.0 on end device pci 1d.1 on end device pci 1d.2 on end
Modified: trunk/src/mainboard/intel/jarrell/romstage.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/romstage.c Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/intel/jarrell/romstage.c Sat Feb 27 02:50:21 2010 (r5167) @@ -12,7 +12,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801er/i82801er_early_smbus.c" +#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc87427/pc87427.h" #include "cpu/x86/lapic/boot_cpu.c"
Modified: trunk/src/mainboard/intel/xe7501devkit/Kconfig ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/Kconfig Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/intel/xe7501devkit/Kconfig Sat Feb 27 02:50:21 2010 (r5167) @@ -4,7 +4,7 @@ select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7501 select SOUTHBRIDGE_INTEL_I82870 - select SOUTHBRIDGE_INTEL_I82801CA + select SOUTHBRIDGE_INTEL_I82801CX select SUPERIO_SMSC_LPC47B272 select ROMCC select HAVE_PIRQ_TABLE
Modified: trunk/src/mainboard/intel/xe7501devkit/devicetree.cb ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/devicetree.cb Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/intel/xe7501devkit/devicetree.cb Sat Feb 27 02:50:21 2010 (r5167) @@ -20,7 +20,7 @@ end end device pci 6.0 on end # E7501 Power management registers? (undocumented) - chip southbridge/intel/i82801ca + chip southbridge/intel/i82801cx device pci 1d.0 off end # USB (might not work, Southbridge code needs looking at) device pci 1d.1 off end # USB (not populated) device pci 1d.2 off end # USB (not populated)
Modified: trunk/src/mainboard/intel/xe7501devkit/failover.c ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/failover.c Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/intel/xe7501devkit/failover.c Sat Feb 27 02:50:21 2010 (r5167) @@ -7,7 +7,7 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include "pc80/mc146818rtc_early.c" -#include "southbridge/intel/i82801ca/cmos_failover.c" +#include "southbridge/intel/i82801cx/cmos_failover.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/intel/e7501/reset_test.c"
Modified: trunk/src/mainboard/intel/xe7501devkit/reset.c ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/reset.c Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/intel/xe7501devkit/reset.c Sat Feb 27 02:50:21 2010 (r5167) @@ -1,6 +1,6 @@ -void i82801ca_hard_reset(void); +void i82801cx_hard_reset(void);
void hard_reset(void) { - i82801ca_hard_reset(); + i82801cx_hard_reset(); }
Modified: trunk/src/mainboard/intel/xe7501devkit/romstage.c ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/romstage.c Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/intel/xe7501devkit/romstage.c Sat Feb 27 02:50:21 2010 (r5167) @@ -14,7 +14,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801ca/i82801ca_early_smbus.c" +#include "southbridge/intel/i82801cx/i82801cx_early_smbus.c" #include "northbridge/intel/e7501/raminit.h" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/intel/e7501/debug.c"
Modified: trunk/src/mainboard/mitac/6513wu/Kconfig ============================================================================== --- trunk/src/mainboard/mitac/6513wu/Kconfig Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/mitac/6513wu/Kconfig Sat Feb 27 02:50:21 2010 (r5167) @@ -23,7 +23,7 @@ select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801XX + select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_SMSCSUPERIO select ROMCC select HAVE_PIRQ_TABLE
Modified: trunk/src/mainboard/mitac/6513wu/devicetree.cb ============================================================================== --- trunk/src/mainboard/mitac/6513wu/devicetree.cb Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/mitac/6513wu/devicetree.cb Sat Feb 27 02:50:21 2010 (r5167) @@ -27,7 +27,7 @@ device pci_domain 0 on # PCI domain device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) device pci 1.0 on end - chip southbridge/intel/i82801xx # Southbridge + chip southbridge/intel/i82801ax # Southbridge register "pirqa_routing" = "0x03" register "pirqb_routing" = "0x05" register "pirqc_routing" = "0x09"
Modified: trunk/src/mainboard/mitac/6513wu/romstage.c ============================================================================== --- trunk/src/mainboard/mitac/6513wu/romstage.c Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/mitac/6513wu/romstage.c Sat Feb 27 02:50:21 2010 (r5167) @@ -31,7 +31,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c"
Modified: trunk/src/mainboard/msi/ms6178/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms6178/Kconfig Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/msi/ms6178/Kconfig Sat Feb 27 02:50:21 2010 (r5167) @@ -23,7 +23,7 @@ select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801XX + select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_WINBOND_W83627HF select ROMCC select HAVE_PIRQ_TABLE
Modified: trunk/src/mainboard/msi/ms6178/devicetree.cb ============================================================================== --- trunk/src/mainboard/msi/ms6178/devicetree.cb Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/msi/ms6178/devicetree.cb Sat Feb 27 02:50:21 2010 (r5167) @@ -27,7 +27,7 @@ device pci_domain 0 on device pci 0.0 on end # Host bridge device pci 1.0 on end # Onboard VGA - chip southbridge/intel/i82801xx # Southbridge + chip southbridge/intel/i82801ax # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1"
Modified: trunk/src/mainboard/msi/ms6178/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6178/romstage.c Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/msi/ms6178/romstage.c Sat Feb 27 02:50:21 2010 (r5167) @@ -35,7 +35,7 @@ #include "northbridge/intel/i82810/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" -#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "pc80/udelay_io.c" #include "lib/debug.c" #include "northbridge/intel/i82810/raminit.c"
Modified: trunk/src/mainboard/nec/powermate2000/Kconfig ============================================================================== --- trunk/src/mainboard/nec/powermate2000/Kconfig Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/nec/powermate2000/Kconfig Sat Feb 27 02:50:21 2010 (r5167) @@ -23,7 +23,7 @@ select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801XX + select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_SMSCSUPERIO select ROMCC select HAVE_PIRQ_TABLE
Modified: trunk/src/mainboard/nec/powermate2000/devicetree.cb ============================================================================== --- trunk/src/mainboard/nec/powermate2000/devicetree.cb Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/nec/powermate2000/devicetree.cb Sat Feb 27 02:50:21 2010 (r5167) @@ -7,7 +7,7 @@ device pci_domain 0 on device pci 0.0 on end # Host bridge device pci 1.0 off end # Onboard video - chip southbridge/intel/i82801xx # Southbridge + chip southbridge/intel/i82801ax # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1"
Modified: trunk/src/mainboard/nec/powermate2000/romstage.c ============================================================================== --- trunk/src/mainboard/nec/powermate2000/romstage.c Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/nec/powermate2000/romstage.c Sat Feb 27 02:50:21 2010 (r5167) @@ -35,7 +35,7 @@ #include "northbridge/intel/i82810/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" -#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "pc80/udelay_io.c" #include "northbridge/intel/i82810/raminit.c"
Modified: trunk/src/mainboard/rca/rm4100/Kconfig ============================================================================== --- trunk/src/mainboard/rca/rm4100/Kconfig Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/rca/rm4100/Kconfig Sat Feb 27 02:50:21 2010 (r5167) @@ -3,7 +3,7 @@ select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82830 - select SOUTHBRIDGE_INTEL_I82801XX + select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_SMSC_SMSCSUPERIO select ROMCC select HAVE_PIRQ_TABLE
Modified: trunk/src/mainboard/rca/rm4100/devicetree.cb ============================================================================== --- trunk/src/mainboard/rca/rm4100/devicetree.cb Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/rca/rm4100/devicetree.cb Sat Feb 27 02:50:21 2010 (r5167) @@ -2,7 +2,7 @@ device pci_domain 0 on # PCI domain device pci 0.0 on end # Host bridge device pci 2.0 on end # VGA (Intel 82830 CGC) - chip southbridge/intel/i82801xx # Southbridge + chip southbridge/intel/i82801dx # Southbridge register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x06" register "pirqc_routing" = "0x07"
Modified: trunk/src/mainboard/rca/rm4100/gpio.c ============================================================================== --- trunk/src/mainboard/rca/rm4100/gpio.c Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/rca/rm4100/gpio.c Sat Feb 27 02:50:21 2010 (r5167) @@ -34,8 +34,8 @@ dev = PCI_DEV(0x0, 0x1f, 0x0);
/* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1)); - pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10); + pci_write_config32(dev, GPIO_BASE, (ICH_IO_BASE_ADDR | 1)); + pci_write_config8(dev, GPIO_CNTL, 0x10);
/* Set GPIO23 to high, this enables the LAN controller. */ udelay(10);
Modified: trunk/src/mainboard/rca/rm4100/romstage.c ============================================================================== --- trunk/src/mainboard/rca/rm4100/romstage.c Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/rca/rm4100/romstage.c Sat Feb 27 02:50:21 2010 (r5167) @@ -35,8 +35,8 @@ #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82830/raminit.h" #include "northbridge/intel/i82830/memory_initialized.c" -#include "southbridge/intel/i82801xx/i82801xx.h" -#include "southbridge/intel/i82801xx/i82801xx_reset.c" +#include "southbridge/intel/i82801dx/i82801dx.h" +#include "southbridge/intel/i82801dx/i82801dx_reset.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "spd_table.h" @@ -44,7 +44,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
-#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
/** * The onboard 64MB PC133 memory does not have a SPD EEPROM so the @@ -127,4 +127,4 @@ /* Check RAM. */ /* ram_check(0, 640 * 1024); */ /* ram_check(64512 * 1024, 65536 * 1024); */ -} \ No newline at end of file +}
Modified: trunk/src/mainboard/supermicro/x6dhe_g2/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/Kconfig Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/supermicro/x6dhe_g2/Kconfig Sat Feb 27 02:50:21 2010 (r5167) @@ -3,7 +3,7 @@ select ARCH_X86 select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7520 - select SOUTHBRIDGE_INTEL_I82801ER + select SOUTHBRIDGE_INTEL_I82801EX select SOUTHBRIDGE_INTEL_PXHD select SUPERIO_NSC_PC87427 select ROMCC
Modified: trunk/src/mainboard/supermicro/x6dhe_g2/devicetree.cb ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/devicetree.cb Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/supermicro/x6dhe_g2/devicetree.cb Sat Feb 27 02:50:21 2010 (r5167) @@ -6,7 +6,7 @@ device pnp 00.3 off end end device pci_domain 0 on - chip southbridge/intel/i82801er # ICH5R + chip southbridge/intel/i82801ex # ICH5R register "pirq_a_d" = "0x0b070a05" register "pirq_e_h" = "0x0a808080"
Modified: trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Sat Feb 27 02:50:21 2010 (r5167) @@ -12,7 +12,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801er/i82801er_early_smbus.c" +#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc87427/pc87427.h" #include "cpu/x86/lapic/boot_cpu.c"
Modified: trunk/src/mainboard/supermicro/x6dhr_ig/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/Kconfig Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/supermicro/x6dhr_ig/Kconfig Sat Feb 27 02:50:21 2010 (r5167) @@ -3,7 +3,7 @@ select ARCH_X86 select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7520 - select SOUTHBRIDGE_INTEL_I82801ER + select SOUTHBRIDGE_INTEL_I82801EX select SOUTHBRIDGE_INTEL_PXHD select SUPERIO_WINBOND_W83627HF select ROMCC
Modified: trunk/src/mainboard/supermicro/x6dhr_ig/devicetree.cb ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/devicetree.cb Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/supermicro/x6dhr_ig/devicetree.cb Sat Feb 27 02:50:21 2010 (r5167) @@ -1,6 +1,6 @@ chip northbridge/intel/e7520 # mch device pci_domain 0 on - chip southbridge/intel/i82801er # i82801er + chip southbridge/intel/i82801ex # i82801er # USB ports device pci 1d.0 on end device pci 1d.1 on end
Modified: trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Sat Feb 27 02:50:21 2010 (r5167) @@ -12,7 +12,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801er/i82801er_early_smbus.c" +#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c"
Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/Kconfig Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/Kconfig Sat Feb 27 02:50:21 2010 (r5167) @@ -3,7 +3,7 @@ select ARCH_X86 select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7520 - select SOUTHBRIDGE_INTEL_I82801ER + select SOUTHBRIDGE_INTEL_I82801EX select SOUTHBRIDGE_INTEL_PXHD select SUPERIO_WINBOND_W83627HF select ROMCC
Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb Sat Feb 27 02:50:21 2010 (r5167) @@ -1,6 +1,6 @@ chip northbridge/intel/e7520 # mch device pci_domain 0 on - chip southbridge/intel/i82801er # i82801er + chip southbridge/intel/i82801ex # i82801er # USB ports device pci 1d.0 on end device pci 1d.1 on end
Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Sat Feb 27 02:50:21 2010 (r5167) @@ -12,7 +12,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" -#include "southbridge/intel/i82801er/i82801er_early_smbus.c" +#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c"
Modified: trunk/src/mainboard/thomson/ip1000/Kconfig ============================================================================== --- trunk/src/mainboard/thomson/ip1000/Kconfig Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/thomson/ip1000/Kconfig Sat Feb 27 02:50:21 2010 (r5167) @@ -3,7 +3,7 @@ select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82830 - select SOUTHBRIDGE_INTEL_I82801XX + select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_SMSC_SMSCSUPERIO select ROMCC select HAVE_PIRQ_TABLE @@ -28,4 +28,4 @@ config IRQ_SLOT_COUNT int default 7 - depends on BOARD_THOMSON_IP1000 \ No newline at end of file + depends on BOARD_THOMSON_IP1000
Modified: trunk/src/mainboard/thomson/ip1000/devicetree.cb ============================================================================== --- trunk/src/mainboard/thomson/ip1000/devicetree.cb Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/thomson/ip1000/devicetree.cb Sat Feb 27 02:50:21 2010 (r5167) @@ -2,7 +2,7 @@ device pci_domain 0 on # PCI domain device pci 0.0 on end # Host bridge device pci 2.0 on end # VGA (Intel 82830 CGC) - chip southbridge/intel/i82801xx # Southbridge + chip southbridge/intel/i82801dx # Southbridge register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x06" register "pirqc_routing" = "0x07"
Modified: trunk/src/mainboard/thomson/ip1000/gpio.c ============================================================================== --- trunk/src/mainboard/thomson/ip1000/gpio.c Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/thomson/ip1000/gpio.c Sat Feb 27 02:50:21 2010 (r5167) @@ -34,8 +34,8 @@ dev = PCI_DEV(0x0, 0x1f, 0x0);
/* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1)); - pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10); + pci_write_config32(dev, GPIO_BASE, (ICH_IO_BASE_ADDR | 1)); + pci_write_config8(dev, GPIO_CNTL, 0x10);
/* Set GPIO23 to high, this enables the LAN controller. */ udelay(10);
Modified: trunk/src/mainboard/thomson/ip1000/romstage.c ============================================================================== --- trunk/src/mainboard/thomson/ip1000/romstage.c Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/thomson/ip1000/romstage.c Sat Feb 27 02:50:21 2010 (r5167) @@ -35,8 +35,8 @@ #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82830/raminit.h" #include "northbridge/intel/i82830/memory_initialized.c" -#include "southbridge/intel/i82801xx/i82801xx.h" -#include "southbridge/intel/i82801xx/i82801xx_reset.c" +#include "southbridge/intel/i82801dx/i82801dx.h" +#include "southbridge/intel/i82801dx/i82801dx_reset.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "spd_table.h" @@ -44,7 +44,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
-#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" +#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
/** * The onboard 64MB PC133 memory does not have a SPD EEPROM so the @@ -127,4 +127,4 @@ /* Check RAM. */ /* ram_check(0, 640 * 1024); */ /* ram_check(64512 * 1024, 65536 * 1024); */ -} \ No newline at end of file +}
Modified: trunk/src/mainboard/tyan/s2735/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2735/Kconfig Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/tyan/s2735/Kconfig Sat Feb 27 02:50:21 2010 (r5167) @@ -4,7 +4,7 @@ select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7501 select SOUTHBRIDGE_INTEL_I82870 - select SOUTHBRIDGE_INTEL_I82801ER + select SOUTHBRIDGE_INTEL_I82801EX select SUPERIO_WINBOND_W83627HF select HAVE_PIRQ_TABLE select HAVE_MP_TABLE
Modified: trunk/src/mainboard/tyan/s2735/devicetree.cb ============================================================================== --- trunk/src/mainboard/tyan/s2735/devicetree.cb Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/tyan/s2735/devicetree.cb Sat Feb 27 02:50:21 2010 (r5167) @@ -14,7 +14,7 @@ end end device pci 6.0 on end - chip southbridge/intel/i82801er + chip southbridge/intel/i82801ex device pci 1d.0 on end device pci 1d.1 on end device pci 1d.2 on end
Modified: trunk/src/mainboard/tyan/s2735/reset.c ============================================================================== --- trunk/src/mainboard/tyan/s2735/reset.c Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/tyan/s2735/reset.c Sat Feb 27 02:50:21 2010 (r5167) @@ -1,7 +1,7 @@ -void i82801er_hard_reset(void); +void i82801ex_hard_reset(void);
/* FIXME: There's another hard_reset() in romstage.c. Why? */ void hard_reset(void) { - i82801er_hard_reset(); + i82801ex_hard_reset(); }
Modified: trunk/src/mainboard/tyan/s2735/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2735/romstage.c Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/mainboard/tyan/s2735/romstage.c Sat Feb 27 02:50:21 2010 (r5167) @@ -25,7 +25,7 @@ } #endif
-#include "southbridge/intel/i82801er/i82801er_early_smbus.c" +#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7501/raminit.h"
#include "cpu/x86/lapic/boot_cpu.c" @@ -82,7 +82,7 @@
#if CONFIG_USE_FALLBACK_IMAGE == 1
-#include "southbridge/intel/i82801er/cmos_failover.c" +#include "southbridge/intel/i82801ex/cmos_failover.c"
void real_main(unsigned long bist);
Modified: trunk/src/southbridge/intel/Kconfig ============================================================================== --- trunk/src/southbridge/intel/Kconfig Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/southbridge/intel/Kconfig Sat Feb 27 02:50:21 2010 (r5167) @@ -1,10 +1,11 @@ source src/southbridge/intel/esb6300/Kconfig source src/southbridge/intel/i3100/Kconfig source src/southbridge/intel/i82371eb/Kconfig -source src/southbridge/intel/i82801ca/Kconfig -source src/southbridge/intel/i82801dbm/Kconfig -source src/southbridge/intel/i82801er/Kconfig +source src/southbridge/intel/i82801ax/Kconfig +source src/southbridge/intel/i82801bx/Kconfig +source src/southbridge/intel/i82801cx/Kconfig +source src/southbridge/intel/i82801dx/Kconfig +source src/southbridge/intel/i82801ex/Kconfig source src/southbridge/intel/i82801gx/Kconfig -source src/southbridge/intel/i82801xx/Kconfig source src/southbridge/intel/i82870/Kconfig source src/southbridge/intel/pxhd/Kconfig
Modified: trunk/src/southbridge/intel/Makefile.inc ============================================================================== --- trunk/src/southbridge/intel/Makefile.inc Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/southbridge/intel/Makefile.inc Sat Feb 27 02:50:21 2010 (r5167) @@ -1,11 +1,12 @@ subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_ESB6300) += esb6300 subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I3100) += i3100 subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801CA) += i82801ca -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801DBM) += i82801dbm -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801ER) += i82801er +subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801AX) += i82801ax +subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801BX) += i82801bx +subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801CX) += i82801cx +subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801DX) += i82801dx +subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801EX) += i82801ex subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx -subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82870) += i82870 subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_PXHD) += pxhd
Modified: trunk/src/southbridge/intel/i82801ax/Kconfig ============================================================================== --- trunk/src/southbridge/intel/i82801xx/Kconfig Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/southbridge/intel/i82801ax/Kconfig Sat Feb 27 02:50:21 2010 (r5167) @@ -18,6 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-config SOUTHBRIDGE_INTEL_I82801XX +config SOUTHBRIDGE_INTEL_I82801AX bool
Modified: trunk/src/southbridge/intel/i82801ax/Makefile.inc ============================================================================== --- trunk/src/southbridge/intel/i82801xx/Makefile.inc Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/southbridge/intel/i82801ax/Makefile.inc Sat Feb 27 02:50:21 2010 (r5167) @@ -18,21 +18,21 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-driver-y += i82801xx.o -driver-y += i82801xx_ac97.o -driver-y += i82801xx_ide.o -driver-y += i82801xx_lpc.o -driver-y += i82801xx_nic.o -driver-y += i82801xx_pci.o -driver-y += i82801xx_sata.o -# driver-y += i82801xx_smbus.o -driver-y += i82801xx_usb.o -driver-y += i82801xx_usb_ehci.o +driver-y += i82801ax.o +driver-y += i82801ax_ac97.o +driver-y += i82801ax_ide.o +driver-y += i82801ax_lpc.o +driver-y += i82801ax_nic.o +driver-y += i82801ax_pci.o +driver-y += i82801ax_sata.o +# driver-y += i82801ax_smbus.o +driver-y += i82801ax_usb.o +driver-y += i82801ax_usb_ehci.o
-obj-y += i82801xx_reset.o -obj-y += i82801xx_watchdog.o +obj-y += i82801ax_reset.o +obj-y += i82801ax_watchdog.o
# TODO: What about cmos_failover.c?
-# TODO: Fix and enable i82801xx_smbus.o later. +# TODO: Fix and enable i82801ax_smbus.o later.
Modified: trunk/src/southbridge/intel/i82801ax/chip.h ============================================================================== --- trunk/src/southbridge/intel/i82801xx/chip.h Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/southbridge/intel/i82801ax/chip.h Sat Feb 27 02:50:21 2010 (r5167) @@ -19,7 +19,7 @@ */
/* - * The i82801xx code currently supports: + * The i82801ax code currently supports: * - 82801AA * - 82801AB * - 82801BA @@ -32,10 +32,10 @@ * This code should NOT be used for ICH6 and later versions. */
-#ifndef SOUTHBRIDGE_INTEL_I82801XX_CHIP_H -#define SOUTHBRIDGE_INTEL_I82801XX_CHIP_H +#ifndef SOUTHBRIDGE_INTEL_I82801AX_CHIP_H +#define SOUTHBRIDGE_INTEL_I82801AX_CHIP_H
-struct southbridge_intel_i82801xx_config { +struct southbridge_intel_i82801ax_config { /** * Interrupt Routing configuration * If bit7 is 1, the interrupt is disabled. @@ -53,6 +53,6 @@ uint8_t ide1_enable; };
-extern struct chip_operations southbridge_intel_i82801xx_ops; +extern struct chip_operations southbridge_intel_i82801ax_ops;
#endif
Modified: trunk/src/southbridge/intel/i82801ax/cmos_failover.c ============================================================================== --- trunk/src/southbridge/intel/i82801xx/cmos_failover.c Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/southbridge/intel/i82801ax/cmos_failover.c Sat Feb 27 02:50:21 2010 (r5167) @@ -16,7 +16,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include "i82801xx.h" +#include "i82801ax.h"
static void check_cmos_failed(void) {
Copied and modified: trunk/src/southbridge/intel/i82801ax/i82801ax.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx.c) ============================================================================== --- trunk/src/southbridge/intel/i82801xx/i82801xx.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801ax/i82801ax.c Sat Feb 27 02:50:21 2010 (r5167) @@ -23,9 +23,9 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include "i82801xx.h" +#include "i82801ax.h"
-void i82801xx_enable(device_t dev) +void i82801ax_enable(device_t dev) { unsigned int index = 0; uint16_t cur_disable_mask, new_disable_mask; @@ -61,7 +61,7 @@ } }
-struct chip_operations southbridge_intel_i82801xx_ops = { - CHIP_NAME("Intel 82801 Series Southbridge") - .enable_dev = i82801xx_enable, +struct chip_operations southbridge_intel_i82801ax_ops = { + CHIP_NAME("Intel ICH/ICH0 (82801AA/AB) Series Southbridge") + .enable_dev = i82801ax_enable, };
Copied and modified: trunk/src/southbridge/intel/i82801ax/i82801ax.h (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx.h) ============================================================================== --- trunk/src/southbridge/intel/i82801xx/i82801xx.h Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801ax/i82801ax.h Sat Feb 27 02:50:21 2010 (r5167) @@ -18,12 +18,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#ifndef SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H -#define SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H +#ifndef SOUTHBRIDGE_INTEL_I82801AX_I82801AX_H +#define SOUTHBRIDGE_INTEL_I82801AX_I82801AX_H
#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) #include "chip.h" -extern void i82801xx_enable(device_t dev); +extern void i82801ax_enable(device_t dev); #endif
#define PCI_DMA_CFG 0x90 @@ -117,4 +117,4 @@ /* HPET, if present */ #define HPET_ADDR 0xfed0000
-#endif /* SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H */ +#endif /* SOUTHBRIDGE_INTEL_I82801AX_I82801AX_H */
Copied and modified: trunk/src/southbridge/intel/i82801ax/i82801ax_ac97.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_ac97.c) ============================================================================== --- trunk/src/southbridge/intel/i82801xx/i82801xx_ac97.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_ac97.c Sat Feb 27 02:50:21 2010 (r5167) @@ -25,7 +25,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "i82801xx.h" +#include "i82801ax.h"
static struct device_operations ac97_ops = { .read_resources = pci_dev_read_resources, @@ -33,7 +33,7 @@ .enable_resources = pci_dev_enable_resources, .init = 0, .scan_bus = 0, - .enable = i82801xx_enable, + .enable = i82801ax_enable, };
/* 82801AA (ICH) */
Copied and modified: trunk/src/southbridge/intel/i82801ax/i82801ax_early_lpc.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c) ============================================================================== --- trunk/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_early_lpc.c Sat Feb 27 02:50:21 2010 (r5167) @@ -18,7 +18,7 @@ * */
-static void i82801xx_halt_tco_timer(void) +static void i82801ax_halt_tco_timer(void) { device_t dev; uint16_t halt_tco_timer;
Copied and modified: trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c) ============================================================================== --- trunk/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c Sat Feb 27 02:50:21 2010 (r5167) @@ -21,8 +21,8 @@ */
#include <device/pci_ids.h> -#include "i82801xx.h" -#include "i82801xx_smbus.h" +#include "i82801ax.h" +#include "i82801ax_smbus.h"
static void enable_smbus(void) {
Copied and modified: trunk/src/southbridge/intel/i82801ax/i82801ax_ide.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_ide.c) ============================================================================== --- trunk/src/southbridge/intel/i82801xx/i82801xx_ide.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_ide.c Sat Feb 27 02:50:21 2010 (r5167) @@ -25,9 +25,9 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "i82801xx.h" +#include "i82801ax.h"
-typedef struct southbridge_intel_i82801xx_config config_t; +typedef struct southbridge_intel_i82801ax_config config_t;
static void ide_init(struct device *dev) { @@ -67,7 +67,7 @@ .enable_resources = pci_dev_enable_resources, .init = ide_init, .scan_bus = 0, - .enable = i82801xx_enable, + .enable = i82801ax_enable, };
/* 82801AA */
Copied and modified: trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_lpc.c) ============================================================================== --- trunk/src/southbridge/intel/i82801xx/i82801xx_lpc.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c Sat Feb 27 02:50:21 2010 (r5167) @@ -30,13 +30,13 @@ #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <arch/io.h> -#include "i82801xx.h" +#include "i82801ax.h"
#define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */
#define NMI_OFF 0
-typedef struct southbridge_intel_i82801xx_config config_t; +typedef struct southbridge_intel_i82801ax_config config_t;
/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control * 0x00 - 0000 = Reserved @@ -74,7 +74,7 @@ * specific IRQ values in your mainboards Config.lb. */
-void i82801xx_enable_apic(struct device *dev) +void i82801ax_enable_apic(struct device *dev) { uint32_t reg32; volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000; @@ -108,7 +108,7 @@ *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ }
-void i82801xx_enable_serial_irqs(struct device *dev) +void i82801ax_enable_serial_irqs(struct device *dev) { /* Set packet length and toggle silent mode bit. */ pci_write_config8(dev, SERIRQ_CNTL, @@ -118,7 +118,7 @@ /* TODO: Explain/#define the real meaning of these magic numbers. */ }
-static void i82801xx_pirq_init(device_t dev, uint16_t ich_model) +static void i82801ax_pirq_init(device_t dev, uint16_t ich_model) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -176,7 +176,7 @@ } }
-static void i82801xx_power_options(device_t dev) +static void i82801ax_power_options(device_t dev) { uint8_t byte; int pwr_on = -1; @@ -220,7 +220,7 @@ } }
-void i82801xx_rtc_init(struct device *dev) +void i82801ax_rtc_init(struct device *dev) { uint8_t reg8; uint32_t reg32; @@ -240,7 +240,7 @@ pci_write_config8(dev, RTC_CONF, 0x04); }
-void i82801xx_lpc_route_dma(struct device *dev, uint8_t mask) +void i82801ax_lpc_route_dma(struct device *dev, uint8_t mask) { uint16_t reg16; int i; @@ -255,7 +255,7 @@ pci_write_config16(dev, PCI_DMA_CFG, reg16); }
-static void i82801xx_lpc_decode_en(device_t dev, uint16_t ich_model) +static void i82801ax_lpc_decode_en(device_t dev, uint16_t ich_model) { /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. @@ -302,36 +302,36 @@ pci_write_config16(dev, PCI_COMMAND, 0x000f);
/* IO APIC initialization. */ - i82801xx_enable_apic(dev); + i82801ax_enable_apic(dev);
- i82801xx_enable_serial_irqs(dev); + i82801ax_enable_serial_irqs(dev);
/* Setup the PIRQ. */ - i82801xx_pirq_init(dev, ich_model); + i82801ax_pirq_init(dev, ich_model);
/* Setup power options. */ - i82801xx_power_options(dev); + i82801ax_power_options(dev);
/* Set the state of the GPIO lines. */ gpio_init(dev, ich_model);
/* Initialize the real time clock. */ - i82801xx_rtc_init(dev); + i82801ax_rtc_init(dev);
/* Route DMA. */ - i82801xx_lpc_route_dma(dev, 0xff); + i82801ax_lpc_route_dma(dev, 0xff);
/* Initialize ISA DMA. */ isa_dma_init();
/* Setup decode ports and LPC I/F enables. */ - i82801xx_lpc_decode_en(dev, ich_model); + i82801ax_lpc_decode_en(dev, ich_model);
/* Initialize the High Precision Event Timers, if present. */ enable_hpet(dev); }
-static void i82801xx_lpc_read_resources(device_t dev) +static void i82801ax_lpc_read_resources(device_t dev) { struct resource *res;
@@ -357,19 +357,19 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; }
-static void i82801xx_lpc_enable_resources(device_t dev) +static void i82801ax_lpc_enable_resources(device_t dev) { pci_dev_enable_resources(dev); enable_childrens_resources(dev); }
static struct device_operations lpc_ops = { - .read_resources = i82801xx_lpc_read_resources, + .read_resources = i82801ax_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = i82801xx_lpc_enable_resources, + .enable_resources = i82801ax_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, - .enable = i82801xx_enable, + .enable = i82801ax_enable, };
static const struct pci_driver i82801aa_lpc __pci_driver = {
Copied: trunk/src/southbridge/intel/i82801ax/i82801ax_nic.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_nic.c) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_nic.c Sat Feb 27 02:50:21 2010 (r5167, copy of r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_nic.c) @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Corey Osgood corey.osgood@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This code should work for all ICH* southbridges with a NIC. */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static struct device_operations nic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, +}; + +/* Note: There's no NIC on 82801AA/AB (ICH/ICH0). */ + +/* 82801BA/BAM/CA/CAM (ICH2/ICH2-M/ICH3-S/ICH3-M) */ +static const struct pci_driver i82801ba_nic __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801BA_LAN, +}; + +/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */ +static const struct pci_driver i82801db_nic __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801DB_LAN, +}; + +/* 82801EB/ER (ICH5/ICH5R) */ +static const struct pci_driver i82801eb_nic __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801EB_LAN, +}; + +/* 82801FB/FR/FW/FRW/FBM (ICH6/ICH6R/ICH6W/ICH6RW/ICH6-M) */ +static const struct pci_driver i82801fb_nic __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801FB_LAN, +}; + +/* 82801E (C-ICH) */ +static const struct pci_driver i82801e_nic1 __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801E_LAN1, +}; + +static const struct pci_driver i82801e_nic2 __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801E_LAN2, +}; +
Copied: trunk/src/southbridge/intel/i82801ax/i82801ax_pci.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_pci.c) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_pci.c Sat Feb 27 02:50:21 2010 (r5167, copy of r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_pci.c) @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Tyan Computer + * (Written by Yinghai Lu yinghailu@gmail.com for Tyan Computer) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static void pci_init(struct device *dev) +{ + uint16_t reg16; + + /* Clear system errors */ + reg16 = pci_read_config16(dev, 0x06); + reg16 |= 0xf900; /* Clear possible errors */ + pci_write_config16(dev, 0x06, reg16); + + reg16 = pci_read_config16(dev, 0x1e); + reg16 |= 0xf800; /* Clear possible errors */ + pci_write_config16(dev, 0x1e, reg16); +} + +static struct device_operations pci_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pci_init, + .scan_bus = pci_scan_bridge, +}; + +static const struct pci_driver i82801aa_pci __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2418, +}; + +static const struct pci_driver i82801ab_pci __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2428, +}; + +/* 82801BA, 82801CA, 82801DB, 82801EB, and 82801ER */ +static const struct pci_driver i82801misc_pci __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x244e, +}; + +static const struct pci_driver i82801dbm_pci __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2448, +};
Copied: trunk/src/southbridge/intel/i82801ax/i82801ax_reset.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_reset.c) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_reset.c Sat Feb 27 02:50:21 2010 (r5167, copy of r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_reset.c) @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2002 Eric Biederman ebiederm@xmission.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> + +void hard_reset(void) +{ + /* Try rebooting through port 0xcf9. */ + outb((1 << 2) | (1 << 1), 0xcf9); +}
Copied and modified: trunk/src/southbridge/intel/i82801ax/i82801ax_sata.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_sata.c) ============================================================================== --- trunk/src/southbridge/intel/i82801xx/i82801xx_sata.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_sata.c Sat Feb 27 02:50:21 2010 (r5167) @@ -23,7 +23,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "i82801xx.h" +#include "i82801ax.h"
/* TODO: Set dynamically, if the user only wants one SATA channel or none * at all. @@ -64,7 +64,7 @@ .enable_resources = pci_dev_enable_resources, .init = sata_init, .scan_bus = 0, - .enable = i82801xx_enable, + .enable = i82801ax_enable, };
/* 82801EB */
Copied and modified: trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_smbus.c) ============================================================================== --- trunk/src/southbridge/intel/i82801xx/i82801xx_smbus.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.c Sat Feb 27 02:50:21 2010 (r5167) @@ -24,7 +24,7 @@ #include <smbus.h> #include <pci.h> #include <arch/io.h> -#include "i82801xx.h" +#include "i82801ax.h" #include "i82801_smbus.h"
static int smbus_read_byte(struct bus *bus, device_t dev, u8 address)
Copied: trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_smbus.h) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h Sat Feb 27 02:50:21 2010 (r5167, copy of r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_smbus.h) @@ -0,0 +1,183 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Yinghai Lu yinghailu@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/smbus_def.h> + +static void smbus_delay(void) +{ + inb(0x80); +} + +static int smbus_wait_until_ready(void) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } while (byte & 1); + return loops ? 0 : -1; +} + +static int smbus_wait_until_done(void) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0); + return loops ? 0 : -1; +} + +static int smbus_wait_until_blk_done(void) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } while ((byte & (1 << 7)) == 0); + return loops ? 0 : -1; +} + +static int do_smbus_read_byte(unsigned device, unsigned address) +{ + unsigned char global_status_register; + unsigned char byte; + + if (smbus_wait_until_ready() < 0) { + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } + /* Setup transaction */ + /* Disable interrupts */ + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); + /* Set the command/address... */ + outb(address & 0xff, SMBUS_IO_BASE + SMBHSTCMD); + /* Set up for a byte data read */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2), + (SMBUS_IO_BASE + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + + /* Clear the data byte... */ + outb(0, SMBUS_IO_BASE + SMBHSTDAT0); + + /* Start the command */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), + SMBUS_IO_BASE + SMBHSTCTL); + + /* Poll for transaction completion */ + if (smbus_wait_until_done() < 0) { + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + } + + global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); + + /* Ignore the "In Use" status... */ + global_status_register &= ~(3 << 5); + + /* Read results of transaction */ + byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); + if (global_status_register != (1 << 1)) { + return SMBUS_ERROR; + } + return byte; +} + +/* This function is neither used nor tested by me (Corey Osgood), the author +(Yinghai) probably tested/used it on i82801er */ +static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, + unsigned data1, unsigned data2) +{ +#warning "do_smbus_write_block is commented out" + print_err("Untested smbus_write_block called\r\n"); +#if 0 + unsigned char global_control_register; + unsigned char global_status_register; + unsigned char byte; + unsigned char stat; + int i; + + /* Clear the PM timeout flags, SECOND_TO_STS */ + outw(inw(0x0400 + 0x66), 0x0400 + 0x66); + + if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) { + return -2; + } + + /* Setup transaction */ + /* Obtain ownership */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + for (stat = 0; (stat & 0x40) == 0;) { + stat = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } + /* Clear the done bit */ + outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT); + /* Disable interrupts */ + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); + + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD); + + /* Set the command address */ + outb(cmd & 0xff, SMBUS_IO_BASE + SMBHSTCMD); + + /* Set the block length */ + outb(length & 0xff, SMBUS_IO_BASE + SMBHSTDAT0); + + /* Try sending out the first byte of data here */ + byte = (data1 >> (0)) & 0x0ff; + outb(byte, SMBUS_IO_BASE + SMBBLKDAT); + /* Issue a block write command */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x5 << 2) | 0x40, + SMBUS_IO_BASE + SMBHSTCTL); + + for (i = 0; i < length; i++) { + + /* Poll for transaction completion */ + if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) { + return -3; + } + + /* Load the next byte */ + if (i > 3) + byte = (data2 >> (i % 4)) & 0x0ff; + else + byte = (data1 >> (i)) & 0x0ff; + outb(byte, SMBUS_IO_BASE + SMBBLKDAT); + + /* Clear the done bit */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), + SMBUS_IO_BASE + SMBHSTSTAT); + } + + print_debug("SMBUS Block complete\r\n"); + return 0; +#endif +}
Copied and modified: trunk/src/southbridge/intel/i82801ax/i82801ax_usb.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_usb.c) ============================================================================== --- trunk/src/southbridge/intel/i82801xx/i82801xx_usb.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_usb.c Sat Feb 27 02:50:21 2010 (r5167) @@ -24,7 +24,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "i82801xx.h" +#include "i82801ax.h"
static void usb_init(struct device *dev) { @@ -37,7 +37,7 @@ .enable_resources = pci_dev_enable_resources, .init = usb_init, .scan_bus = 0, - .enable = i82801xx_enable, + .enable = i82801ax_enable, };
/* 82801AA (ICH) */
Copied and modified: trunk/src/southbridge/intel/i82801ax/i82801ax_usb_ehci.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c) ============================================================================== --- trunk/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_usb_ehci.c Sat Feb 27 02:50:21 2010 (r5167) @@ -23,7 +23,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "i82801xx.h" +#include "i82801ax.h"
static void usb_ehci_init(struct device *dev) { @@ -65,7 +65,7 @@ .enable_resources = pci_dev_enable_resources, .init = usb_ehci_init, .scan_bus = 0, - .enable = i82801xx_enable, + .enable = i82801ax_enable, .ops_pci = &lops_pci, };
Copied: trunk/src/southbridge/intel/i82801ax/i82801ax_watchdog.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_watchdog.c) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_watchdog.c Sat Feb 27 02:50:21 2010 (r5167, copy of r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_watchdog.c) @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 John Dufresne jon.dufresne@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> + +/* TODO: I'm fairly sure the same functionality is provided elsewhere. */ + +void watchdog_off(void) +{ + device_t dev; + unsigned long value, base; + + /* Turn off the ICH5 watchdog. */ + dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + + /* Enable I/O space. */ + value = pci_read_config16(dev, 0x04); + value |= (1 << 10); + pci_write_config16(dev, 0x04, value); + + /* Get TCO base. */ + base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; + + /* Disable the watchdog timer. */ + value = inw(base + 0x08); + value |= 1 << 11; + outw(value, base + 0x08); + + /* Clear TCO timeout status. */ + outw(0x0008, base + 0x04); + outw(0x0002, base + 0x06); + + printk_debug("ICH Watchdog disabled\r\n"); +}
Modified: trunk/src/southbridge/intel/i82801bx/Kconfig ============================================================================== --- trunk/src/southbridge/intel/i82801xx/Kconfig Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/southbridge/intel/i82801bx/Kconfig Sat Feb 27 02:50:21 2010 (r5167) @@ -18,6 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-config SOUTHBRIDGE_INTEL_I82801XX +config SOUTHBRIDGE_INTEL_I82801BX bool
Modified: trunk/src/southbridge/intel/i82801bx/Makefile.inc ============================================================================== --- trunk/src/southbridge/intel/i82801xx/Makefile.inc Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/southbridge/intel/i82801bx/Makefile.inc Sat Feb 27 02:50:21 2010 (r5167) @@ -18,21 +18,21 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-driver-y += i82801xx.o -driver-y += i82801xx_ac97.o -driver-y += i82801xx_ide.o -driver-y += i82801xx_lpc.o -driver-y += i82801xx_nic.o -driver-y += i82801xx_pci.o -driver-y += i82801xx_sata.o -# driver-y += i82801xx_smbus.o -driver-y += i82801xx_usb.o -driver-y += i82801xx_usb_ehci.o +driver-y += i82801bx.o +driver-y += i82801bx_ac97.o +driver-y += i82801bx_ide.o +driver-y += i82801bx_lpc.o +driver-y += i82801bx_nic.o +driver-y += i82801bx_pci.o +driver-y += i82801bx_sata.o +# driver-y += i82801bx_smbus.o +driver-y += i82801bx_usb.o +driver-y += i82801bx_usb_ehci.o
-obj-y += i82801xx_reset.o -obj-y += i82801xx_watchdog.o +obj-y += i82801bx_reset.o +obj-y += i82801bx_watchdog.o
# TODO: What about cmos_failover.c?
-# TODO: Fix and enable i82801xx_smbus.o later. +# TODO: Fix and enable i82801bx_smbus.o later.
Modified: trunk/src/southbridge/intel/i82801bx/chip.h ============================================================================== --- trunk/src/southbridge/intel/i82801xx/chip.h Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/southbridge/intel/i82801bx/chip.h Sat Feb 27 02:50:21 2010 (r5167) @@ -19,7 +19,7 @@ */
/* - * The i82801xx code currently supports: + * The i82801bx code currently supports: * - 82801AA * - 82801AB * - 82801BA @@ -32,10 +32,10 @@ * This code should NOT be used for ICH6 and later versions. */
-#ifndef SOUTHBRIDGE_INTEL_I82801XX_CHIP_H -#define SOUTHBRIDGE_INTEL_I82801XX_CHIP_H +#ifndef SOUTHBRIDGE_INTEL_I82801BX_CHIP_H +#define SOUTHBRIDGE_INTEL_I82801BX_CHIP_H
-struct southbridge_intel_i82801xx_config { +struct southbridge_intel_i82801bx_config { /** * Interrupt Routing configuration * If bit7 is 1, the interrupt is disabled. @@ -53,6 +53,6 @@ uint8_t ide1_enable; };
-extern struct chip_operations southbridge_intel_i82801xx_ops; +extern struct chip_operations southbridge_intel_i82801bx_ops;
#endif
Modified: trunk/src/southbridge/intel/i82801bx/cmos_failover.c ============================================================================== --- trunk/src/southbridge/intel/i82801xx/cmos_failover.c Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/southbridge/intel/i82801bx/cmos_failover.c Sat Feb 27 02:50:21 2010 (r5167) @@ -16,7 +16,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include "i82801xx.h" +#include "i82801bx.h"
static void check_cmos_failed(void) {
Copied and modified: trunk/src/southbridge/intel/i82801bx/i82801bx.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx.c) ============================================================================== --- trunk/src/southbridge/intel/i82801xx/i82801xx.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801bx/i82801bx.c Sat Feb 27 02:50:21 2010 (r5167) @@ -23,9 +23,9 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include "i82801xx.h" +#include "i82801bx.h"
-void i82801xx_enable(device_t dev) +void i82801bx_enable(device_t dev) { unsigned int index = 0; uint16_t cur_disable_mask, new_disable_mask; @@ -61,7 +61,7 @@ } }
-struct chip_operations southbridge_intel_i82801xx_ops = { - CHIP_NAME("Intel 82801 Series Southbridge") - .enable_dev = i82801xx_enable, +struct chip_operations southbridge_intel_i82801bx_ops = { + CHIP_NAME("Intel ICH2 (82801Bx) Series Southbridge") + .enable_dev = i82801bx_enable, };
Copied and modified: trunk/src/southbridge/intel/i82801bx/i82801bx.h (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx.h) ============================================================================== --- trunk/src/southbridge/intel/i82801xx/i82801xx.h Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801bx/i82801bx.h Sat Feb 27 02:50:21 2010 (r5167) @@ -18,12 +18,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#ifndef SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H -#define SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H +#ifndef SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H +#define SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H
#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) #include "chip.h" -extern void i82801xx_enable(device_t dev); +extern void i82801bx_enable(device_t dev); #endif
#define PCI_DMA_CFG 0x90 @@ -117,4 +117,5 @@ /* HPET, if present */ #define HPET_ADDR 0xfed0000
-#endif /* SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H */ +#endif /* SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H */ +
Copied and modified: trunk/src/southbridge/intel/i82801bx/i82801bx_ac97.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_ac97.c) ============================================================================== --- trunk/src/southbridge/intel/i82801xx/i82801xx_ac97.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_ac97.c Sat Feb 27 02:50:21 2010 (r5167) @@ -25,7 +25,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "i82801xx.h" +#include "i82801bx.h"
static struct device_operations ac97_ops = { .read_resources = pci_dev_read_resources, @@ -33,7 +33,7 @@ .enable_resources = pci_dev_enable_resources, .init = 0, .scan_bus = 0, - .enable = i82801xx_enable, + .enable = i82801bx_enable, };
/* 82801AA (ICH) */
Copied and modified: trunk/src/southbridge/intel/i82801bx/i82801bx_early_lpc.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c) ============================================================================== --- trunk/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_early_lpc.c Sat Feb 27 02:50:21 2010 (r5167) @@ -18,7 +18,7 @@ * */
-static void i82801xx_halt_tco_timer(void) +static void i82801bx_halt_tco_timer(void) { device_t dev; uint16_t halt_tco_timer;
Copied and modified: trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c) ============================================================================== --- trunk/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c Sat Feb 27 02:50:21 2010 (r5167) @@ -21,8 +21,8 @@ */
#include <device/pci_ids.h> -#include "i82801xx.h" -#include "i82801xx_smbus.h" +#include "i82801bx.h" +#include "i82801bx_smbus.h"
static void enable_smbus(void) {
Copied and modified: trunk/src/southbridge/intel/i82801bx/i82801bx_ide.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_ide.c) ============================================================================== --- trunk/src/southbridge/intel/i82801xx/i82801xx_ide.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_ide.c Sat Feb 27 02:50:21 2010 (r5167) @@ -25,9 +25,9 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "i82801xx.h" +#include "i82801bx.h"
-typedef struct southbridge_intel_i82801xx_config config_t; +typedef struct southbridge_intel_i82801bx_config config_t;
static void ide_init(struct device *dev) { @@ -67,7 +67,7 @@ .enable_resources = pci_dev_enable_resources, .init = ide_init, .scan_bus = 0, - .enable = i82801xx_enable, + .enable = i82801bx_enable, };
/* 82801AA */
Copied and modified: trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_lpc.c) ============================================================================== --- trunk/src/southbridge/intel/i82801xx/i82801xx_lpc.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c Sat Feb 27 02:50:21 2010 (r5167) @@ -30,13 +30,13 @@ #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <arch/io.h> -#include "i82801xx.h" +#include "i82801bx.h"
#define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */
#define NMI_OFF 0
-typedef struct southbridge_intel_i82801xx_config config_t; +typedef struct southbridge_intel_i82801bx_config config_t;
/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control * 0x00 - 0000 = Reserved @@ -74,7 +74,7 @@ * specific IRQ values in your mainboards Config.lb. */
-void i82801xx_enable_apic(struct device *dev) +void i82801bx_enable_apic(struct device *dev) { uint32_t reg32; volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000; @@ -108,7 +108,7 @@ *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ }
-void i82801xx_enable_serial_irqs(struct device *dev) +void i82801bx_enable_serial_irqs(struct device *dev) { /* Set packet length and toggle silent mode bit. */ pci_write_config8(dev, SERIRQ_CNTL, @@ -118,7 +118,7 @@ /* TODO: Explain/#define the real meaning of these magic numbers. */ }
-static void i82801xx_pirq_init(device_t dev, uint16_t ich_model) +static void i82801bx_pirq_init(device_t dev, uint16_t ich_model) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -176,7 +176,7 @@ } }
-static void i82801xx_power_options(device_t dev) +static void i82801bx_power_options(device_t dev) { uint8_t byte; int pwr_on = -1; @@ -220,7 +220,7 @@ } }
-void i82801xx_rtc_init(struct device *dev) +void i82801bx_rtc_init(struct device *dev) { uint8_t reg8; uint32_t reg32; @@ -240,7 +240,7 @@ pci_write_config8(dev, RTC_CONF, 0x04); }
-void i82801xx_lpc_route_dma(struct device *dev, uint8_t mask) +void i82801bx_lpc_route_dma(struct device *dev, uint8_t mask) { uint16_t reg16; int i; @@ -255,7 +255,7 @@ pci_write_config16(dev, PCI_DMA_CFG, reg16); }
-static void i82801xx_lpc_decode_en(device_t dev, uint16_t ich_model) +static void i82801bx_lpc_decode_en(device_t dev, uint16_t ich_model) { /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. @@ -302,36 +302,36 @@ pci_write_config16(dev, PCI_COMMAND, 0x000f);
/* IO APIC initialization. */ - i82801xx_enable_apic(dev); + i82801bx_enable_apic(dev);
- i82801xx_enable_serial_irqs(dev); + i82801bx_enable_serial_irqs(dev);
/* Setup the PIRQ. */ - i82801xx_pirq_init(dev, ich_model); + i82801bx_pirq_init(dev, ich_model);
/* Setup power options. */ - i82801xx_power_options(dev); + i82801bx_power_options(dev);
/* Set the state of the GPIO lines. */ gpio_init(dev, ich_model);
/* Initialize the real time clock. */ - i82801xx_rtc_init(dev); + i82801bx_rtc_init(dev);
/* Route DMA. */ - i82801xx_lpc_route_dma(dev, 0xff); + i82801bx_lpc_route_dma(dev, 0xff);
/* Initialize ISA DMA. */ isa_dma_init();
/* Setup decode ports and LPC I/F enables. */ - i82801xx_lpc_decode_en(dev, ich_model); + i82801bx_lpc_decode_en(dev, ich_model);
/* Initialize the High Precision Event Timers, if present. */ enable_hpet(dev); }
-static void i82801xx_lpc_read_resources(device_t dev) +static void i82801bx_lpc_read_resources(device_t dev) { struct resource *res;
@@ -357,19 +357,19 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; }
-static void i82801xx_lpc_enable_resources(device_t dev) +static void i82801bx_lpc_enable_resources(device_t dev) { pci_dev_enable_resources(dev); enable_childrens_resources(dev); }
static struct device_operations lpc_ops = { - .read_resources = i82801xx_lpc_read_resources, + .read_resources = i82801bx_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = i82801xx_lpc_enable_resources, + .enable_resources = i82801bx_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, - .enable = i82801xx_enable, + .enable = i82801bx_enable, };
static const struct pci_driver i82801aa_lpc __pci_driver = {
Copied: trunk/src/southbridge/intel/i82801bx/i82801bx_nic.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_nic.c) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_nic.c Sat Feb 27 02:50:21 2010 (r5167, copy of r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_nic.c) @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Corey Osgood corey.osgood@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This code should work for all ICH* southbridges with a NIC. */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static struct device_operations nic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, +}; + +/* Note: There's no NIC on 82801AA/AB (ICH/ICH0). */ + +/* 82801BA/BAM/CA/CAM (ICH2/ICH2-M/ICH3-S/ICH3-M) */ +static const struct pci_driver i82801ba_nic __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801BA_LAN, +}; + +/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */ +static const struct pci_driver i82801db_nic __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801DB_LAN, +}; + +/* 82801EB/ER (ICH5/ICH5R) */ +static const struct pci_driver i82801eb_nic __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801EB_LAN, +}; + +/* 82801FB/FR/FW/FRW/FBM (ICH6/ICH6R/ICH6W/ICH6RW/ICH6-M) */ +static const struct pci_driver i82801fb_nic __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801FB_LAN, +}; + +/* 82801E (C-ICH) */ +static const struct pci_driver i82801e_nic1 __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801E_LAN1, +}; + +static const struct pci_driver i82801e_nic2 __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801E_LAN2, +}; +
Copied: trunk/src/southbridge/intel/i82801bx/i82801bx_pci.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_pci.c) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_pci.c Sat Feb 27 02:50:21 2010 (r5167, copy of r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_pci.c) @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Tyan Computer + * (Written by Yinghai Lu yinghailu@gmail.com for Tyan Computer) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static void pci_init(struct device *dev) +{ + uint16_t reg16; + + /* Clear system errors */ + reg16 = pci_read_config16(dev, 0x06); + reg16 |= 0xf900; /* Clear possible errors */ + pci_write_config16(dev, 0x06, reg16); + + reg16 = pci_read_config16(dev, 0x1e); + reg16 |= 0xf800; /* Clear possible errors */ + pci_write_config16(dev, 0x1e, reg16); +} + +static struct device_operations pci_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pci_init, + .scan_bus = pci_scan_bridge, +}; + +static const struct pci_driver i82801aa_pci __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2418, +}; + +static const struct pci_driver i82801ab_pci __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2428, +}; + +/* 82801BA, 82801CA, 82801DB, 82801EB, and 82801ER */ +static const struct pci_driver i82801misc_pci __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x244e, +}; + +static const struct pci_driver i82801dbm_pci __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2448, +};
Copied: trunk/src/southbridge/intel/i82801bx/i82801bx_reset.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_reset.c) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_reset.c Sat Feb 27 02:50:21 2010 (r5167, copy of r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_reset.c) @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2002 Eric Biederman ebiederm@xmission.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> + +void hard_reset(void) +{ + /* Try rebooting through port 0xcf9. */ + outb((1 << 2) | (1 << 1), 0xcf9); +}
Copied and modified: trunk/src/southbridge/intel/i82801bx/i82801bx_sata.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_sata.c) ============================================================================== --- trunk/src/southbridge/intel/i82801xx/i82801xx_sata.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_sata.c Sat Feb 27 02:50:21 2010 (r5167) @@ -23,7 +23,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "i82801xx.h" +#include "i82801bx.h"
/* TODO: Set dynamically, if the user only wants one SATA channel or none * at all. @@ -64,7 +64,7 @@ .enable_resources = pci_dev_enable_resources, .init = sata_init, .scan_bus = 0, - .enable = i82801xx_enable, + .enable = i82801bx_enable, };
/* 82801EB */
Copied and modified: trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_smbus.c) ============================================================================== --- trunk/src/southbridge/intel/i82801xx/i82801xx_smbus.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.c Sat Feb 27 02:50:21 2010 (r5167) @@ -24,7 +24,7 @@ #include <smbus.h> #include <pci.h> #include <arch/io.h> -#include "i82801xx.h" +#include "i82801bx.h" #include "i82801_smbus.h"
static int smbus_read_byte(struct bus *bus, device_t dev, u8 address)
Copied: trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_smbus.h) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h Sat Feb 27 02:50:21 2010 (r5167, copy of r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_smbus.h) @@ -0,0 +1,183 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Yinghai Lu yinghailu@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/smbus_def.h> + +static void smbus_delay(void) +{ + inb(0x80); +} + +static int smbus_wait_until_ready(void) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } while (byte & 1); + return loops ? 0 : -1; +} + +static int smbus_wait_until_done(void) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0); + return loops ? 0 : -1; +} + +static int smbus_wait_until_blk_done(void) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } while ((byte & (1 << 7)) == 0); + return loops ? 0 : -1; +} + +static int do_smbus_read_byte(unsigned device, unsigned address) +{ + unsigned char global_status_register; + unsigned char byte; + + if (smbus_wait_until_ready() < 0) { + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } + /* Setup transaction */ + /* Disable interrupts */ + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); + /* Set the command/address... */ + outb(address & 0xff, SMBUS_IO_BASE + SMBHSTCMD); + /* Set up for a byte data read */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2), + (SMBUS_IO_BASE + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + + /* Clear the data byte... */ + outb(0, SMBUS_IO_BASE + SMBHSTDAT0); + + /* Start the command */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), + SMBUS_IO_BASE + SMBHSTCTL); + + /* Poll for transaction completion */ + if (smbus_wait_until_done() < 0) { + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + } + + global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); + + /* Ignore the "In Use" status... */ + global_status_register &= ~(3 << 5); + + /* Read results of transaction */ + byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); + if (global_status_register != (1 << 1)) { + return SMBUS_ERROR; + } + return byte; +} + +/* This function is neither used nor tested by me (Corey Osgood), the author +(Yinghai) probably tested/used it on i82801er */ +static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, + unsigned data1, unsigned data2) +{ +#warning "do_smbus_write_block is commented out" + print_err("Untested smbus_write_block called\r\n"); +#if 0 + unsigned char global_control_register; + unsigned char global_status_register; + unsigned char byte; + unsigned char stat; + int i; + + /* Clear the PM timeout flags, SECOND_TO_STS */ + outw(inw(0x0400 + 0x66), 0x0400 + 0x66); + + if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) { + return -2; + } + + /* Setup transaction */ + /* Obtain ownership */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + for (stat = 0; (stat & 0x40) == 0;) { + stat = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } + /* Clear the done bit */ + outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT); + /* Disable interrupts */ + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); + + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD); + + /* Set the command address */ + outb(cmd & 0xff, SMBUS_IO_BASE + SMBHSTCMD); + + /* Set the block length */ + outb(length & 0xff, SMBUS_IO_BASE + SMBHSTDAT0); + + /* Try sending out the first byte of data here */ + byte = (data1 >> (0)) & 0x0ff; + outb(byte, SMBUS_IO_BASE + SMBBLKDAT); + /* Issue a block write command */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x5 << 2) | 0x40, + SMBUS_IO_BASE + SMBHSTCTL); + + for (i = 0; i < length; i++) { + + /* Poll for transaction completion */ + if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) { + return -3; + } + + /* Load the next byte */ + if (i > 3) + byte = (data2 >> (i % 4)) & 0x0ff; + else + byte = (data1 >> (i)) & 0x0ff; + outb(byte, SMBUS_IO_BASE + SMBBLKDAT); + + /* Clear the done bit */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), + SMBUS_IO_BASE + SMBHSTSTAT); + } + + print_debug("SMBUS Block complete\r\n"); + return 0; +#endif +}
Copied and modified: trunk/src/southbridge/intel/i82801bx/i82801bx_usb.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_usb.c) ============================================================================== --- trunk/src/southbridge/intel/i82801xx/i82801xx_usb.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_usb.c Sat Feb 27 02:50:21 2010 (r5167) @@ -24,7 +24,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "i82801xx.h" +#include "i82801bx.h"
static void usb_init(struct device *dev) { @@ -37,7 +37,7 @@ .enable_resources = pci_dev_enable_resources, .init = usb_init, .scan_bus = 0, - .enable = i82801xx_enable, + .enable = i82801bx_enable, };
/* 82801AA (ICH) */
Copied and modified: trunk/src/southbridge/intel/i82801bx/i82801bx_usb_ehci.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c) ============================================================================== --- trunk/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_usb_ehci.c Sat Feb 27 02:50:21 2010 (r5167) @@ -23,7 +23,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "i82801xx.h" +#include "i82801bx.h"
static void usb_ehci_init(struct device *dev) { @@ -65,7 +65,7 @@ .enable_resources = pci_dev_enable_resources, .init = usb_ehci_init, .scan_bus = 0, - .enable = i82801xx_enable, + .enable = i82801bx_enable, .ops_pci = &lops_pci, };
Copied: trunk/src/southbridge/intel/i82801bx/i82801bx_watchdog.c (from r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_watchdog.c) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_watchdog.c Sat Feb 27 02:50:21 2010 (r5167, copy of r5166, trunk/src/southbridge/intel/i82801xx/i82801xx_watchdog.c) @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 John Dufresne jon.dufresne@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> + +/* TODO: I'm fairly sure the same functionality is provided elsewhere. */ + +void watchdog_off(void) +{ + device_t dev; + unsigned long value, base; + + /* Turn off the ICH5 watchdog. */ + dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + + /* Enable I/O space. */ + value = pci_read_config16(dev, 0x04); + value |= (1 << 10); + pci_write_config16(dev, 0x04, value); + + /* Get TCO base. */ + base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; + + /* Disable the watchdog timer. */ + value = inw(base + 0x08); + value |= 1 << 11; + outw(value, base + 0x08); + + /* Clear TCO timeout status. */ + outw(0x0008, base + 0x04); + outw(0x0002, base + 0x06); + + printk_debug("ICH Watchdog disabled\r\n"); +}
Modified: trunk/src/southbridge/intel/i82801cx/Kconfig ============================================================================== --- trunk/src/southbridge/intel/i82801ca/Kconfig Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/southbridge/intel/i82801cx/Kconfig Sat Feb 27 02:50:21 2010 (r5167) @@ -1,2 +1,2 @@ -config SOUTHBRIDGE_INTEL_I82801CA +config SOUTHBRIDGE_INTEL_I82801CX bool
Modified: trunk/src/southbridge/intel/i82801cx/Makefile.inc ============================================================================== --- trunk/src/southbridge/intel/i82801ca/Makefile.inc Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/southbridge/intel/i82801cx/Makefile.inc Sat Feb 27 02:50:21 2010 (r5167) @@ -1,8 +1,8 @@ -driver-y += i82801ca.o -driver-y += i82801ca_usb.o -driver-y += i82801ca_lpc.o -driver-y += i82801ca_ide.o -driver-y += i82801ca_ac97.o -#driver-y += i82801ca_nic.o -driver-y += i82801ca_pci.o -obj-y += i82801ca_reset.o +driver-y += i82801cx.o +driver-y += i82801cx_usb.o +driver-y += i82801cx_lpc.o +driver-y += i82801cx_ide.o +driver-y += i82801cx_ac97.o +#driver-y += i82801cx_nic.o +driver-y += i82801cx_pci.o +obj-y += i82801cx_reset.o
Modified: trunk/src/southbridge/intel/i82801cx/chip.h ============================================================================== --- trunk/src/southbridge/intel/i82801ca/chip.h Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/southbridge/intel/i82801cx/chip.h Sat Feb 27 02:50:21 2010 (r5167) @@ -1,9 +1,9 @@ -#ifndef I82801CA_CHIP_H -#define I82801CA_CHIP_H +#ifndef I82801CX_CHIP_H +#define I82801CX_CHIP_H
-struct southbridge_intel_i82801ca_config +struct southbridge_intel_i82801cx_config { }; -extern struct chip_operations southbridge_intel_i82801ca_ops; +extern struct chip_operations southbridge_intel_i82801cx_ops;
-#endif /* I82801CA_CHIP_H */ +#endif /* I82801CX_CHIP_H */
Modified: trunk/src/southbridge/intel/i82801cx/cmos_failover.c ============================================================================== --- trunk/src/southbridge/intel/i82801ca/cmos_failover.c Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/southbridge/intel/i82801cx/cmos_failover.c Sat Feb 27 02:50:21 2010 (r5167) @@ -1,6 +1,6 @@ //kind of cmos_err for ich3
-#include "i82801ca.h" +#include "i82801cx.h"
static void check_cmos_failed(void) {
Copied and modified: trunk/src/southbridge/intel/i82801cx/i82801cx.c (from r5166, trunk/src/southbridge/intel/i82801ca/i82801ca.c) ============================================================================== --- trunk/src/southbridge/intel/i82801ca/i82801ca.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801cx/i82801cx.c Sat Feb 27 02:50:21 2010 (r5167) @@ -3,9 +3,9 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <assert.h> -#include "i82801ca.h" +#include "i82801cx.h"
-void i82801ca_enable(device_t dev) +void i82801cx_enable(device_t dev) { unsigned int index = 0; uint8_t bHasDisableBit = 0; @@ -47,7 +47,7 @@ } }
-struct chip_operations southbridge_intel_i82801ca_ops = { - CHIP_NAME("Intel 82801CA Southbridge") - .enable_dev = i82801ca_enable, +struct chip_operations southbridge_intel_i82801cx_ops = { + CHIP_NAME("Intel ICH3 (82801Cx) Series Southbridge") + .enable_dev = i82801cx_enable, };
Copied and modified: trunk/src/southbridge/intel/i82801cx/i82801cx.h (from r5166, trunk/src/southbridge/intel/i82801ca/i82801ca.h) ============================================================================== --- trunk/src/southbridge/intel/i82801ca/i82801ca.h Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801cx/i82801cx.h Sat Feb 27 02:50:21 2010 (r5167) @@ -1,9 +1,9 @@ -#ifndef I82801CA_H -#define I82801CA_H +#ifndef I82801CX_H +#define I82801CX_H
#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) #include "chip.h" -extern void i82801ca_enable(device_t dev); +extern void i82801cx_enable(device_t dev); #endif
@@ -75,4 +75,4 @@ */ #define SMBUS_TIMEOUT (100*1000)
-#endif /* I82801CA_H */ +#endif /* I82801CX_H */
Copied and modified: trunk/src/southbridge/intel/i82801cx/i82801cx_ac97.c (from r5166, trunk/src/southbridge/intel/i82801ca/i82801ca_ac97.c) ============================================================================== --- trunk/src/southbridge/intel/i82801ca/i82801ca_ac97.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801cx/i82801cx_ac97.c Sat Feb 27 02:50:21 2010 (r5167) @@ -6,14 +6,14 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801ca.h" +#include "i82801cx.h"
static struct device_operations ac97audio_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .enable = i82801ca_enable, + .enable = i82801cx_enable, .init = 0, .scan_bus = 0, }; @@ -29,7 +29,7 @@ .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .enable = i82801ca_enable, + .enable = i82801cx_enable, .init = 0, .scan_bus = 0, };
Copied and modified: trunk/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c (from r5166, trunk/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c) ============================================================================== --- trunk/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c Sat Feb 27 02:50:21 2010 (r5167) @@ -1,5 +1,5 @@ #include <device/pci_ids.h> -#include "i82801ca.h" +#include "i82801cx.h"
static void enable_smbus(void) {
Copied and modified: trunk/src/southbridge/intel/i82801cx/i82801cx_ide.c (from r5166, trunk/src/southbridge/intel/i82801ca/i82801ca_ide.c) ============================================================================== --- trunk/src/southbridge/intel/i82801ca/i82801ca_ide.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801cx/i82801cx_ide.c Sat Feb 27 02:50:21 2010 (r5167) @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801ca.h" +#include "i82801cx.h"
static void ide_init(struct device *dev) @@ -38,7 +38,7 @@ .enable_resources = pci_dev_enable_resources, .init = ide_init, .scan_bus = 0, - .enable = i82801ca_enable, + .enable = i82801cx_enable, };
static const struct pci_driver ide_driver __pci_driver = {
Copied and modified: trunk/src/southbridge/intel/i82801cx/i82801cx_lpc.c (from r5166, trunk/src/southbridge/intel/i82801ca/i82801ca_lpc.c) ============================================================================== --- trunk/src/southbridge/intel/i82801ca/i82801ca_lpc.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801cx/i82801cx_lpc.c Sat Feb 27 02:50:21 2010 (r5167) @@ -11,7 +11,7 @@ #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <arch/io.h> -#include "i82801ca.h" +#include "i82801cx.h"
#define NMI_OFF 0
@@ -23,7 +23,7 @@ #define MAINBOARD_POWER_ON 1
-void i82801ca_enable_ioapic( struct device *dev) +void i82801cx_enable_ioapic( struct device *dev) { uint32_t dword; volatile uint32_t* ioapic_index = (volatile uint32_t*)0xfec00000; @@ -54,14 +54,14 @@ }
// This is how interrupts are received from the Super I/O chip -void i82801ca_enable_serial_irqs( struct device *dev) +void i82801cx_enable_serial_irqs( struct device *dev) { // Recognize serial IRQs, continuous mode, frame size 21, 4 clock start frame pulse width pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0)); }
//---------------------------------------------------------------------------------- -// Function: i82801ca_lpc_route_dma +// Function: i82801cx_lpc_route_dma // Parameters: dev // mask - identifies whether each channel should be used for PCI DMA // (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0. @@ -69,7 +69,7 @@ // Return Value: None // Description: Route all DMA channels to either PCI or LPC. // -void i82801ca_lpc_route_dma( struct device *dev, uint8_t mask) +void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask) { uint16_t dmaConfig; int channelIndex; @@ -84,7 +84,7 @@ pci_write_config16(dev, PCI_DMA_CFG, dmaConfig); }
-void i82801ca_rtc_init(struct device *dev) +void i82801cx_rtc_init(struct device *dev) { uint32_t dword; int rtc_failed; @@ -116,7 +116,7 @@ }
-void i82801ca_1f0_misc(struct device *dev) +void i82801cx_1f0_misc(struct device *dev) { // Prevent LPC disabling, enable parity errors, and SERR# (System Error) pci_write_config16(dev, PCI_COMMAND, 0x014f); @@ -161,9 +161,9 @@ int nmi_option;
/* IO APIC initialization */ - i82801ca_enable_ioapic(dev); + i82801cx_enable_ioapic(dev);
- i82801ca_enable_serial_irqs(dev); + i82801cx_enable_serial_irqs(dev); /* power after power fail */ /* FIXME this doesn't work! */ @@ -193,17 +193,17 @@ } /* Initialize the real time clock */ - i82801ca_rtc_init(dev); + i82801cx_rtc_init(dev);
- i82801ca_lpc_route_dma(dev, 0xff); + i82801cx_lpc_route_dma(dev, 0xff);
/* Initialize isa dma */ isa_dma_init();
- i82801ca_1f0_misc(dev); + i82801cx_1f0_misc(dev); }
-static void i82801ca_lpc_read_resources(device_t dev) +static void i82801cx_lpc_read_resources(device_t dev) { struct resource *res;
@@ -229,16 +229,16 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; }
-static void i82801ca_lpc_enable_resources(device_t dev) +static void i82801cx_lpc_enable_resources(device_t dev) { pci_dev_enable_resources(dev); enable_childrens_resources(dev); }
static struct device_operations lpc_ops = { - .read_resources = i82801ca_lpc_read_resources, + .read_resources = i82801cx_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = i82801ca_lpc_enable_resources, + .enable_resources = i82801cx_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, .enable = 0,
Copied and modified: trunk/src/southbridge/intel/i82801cx/i82801cx_nic.c (from r5166, trunk/src/southbridge/intel/i82801ca/i82801ca_nic.c) ============================================================================== --- trunk/src/southbridge/intel/i82801ca/i82801ca_nic.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801cx/i82801cx_nic.c Sat Feb 27 02:50:21 2010 (r5167) @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801ca.h" +#include "i82801cx.h"
static struct device_operations nic_ops = {
Copied and modified: trunk/src/southbridge/intel/i82801cx/i82801cx_pci.c (from r5166, trunk/src/southbridge/intel/i82801ca/i82801ca_pci.c) ============================================================================== --- trunk/src/southbridge/intel/i82801ca/i82801ca_pci.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801cx/i82801cx_pci.c Sat Feb 27 02:50:21 2010 (r5167) @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801ca.h" +#include "i82801cx.h"
static void pci_init(struct device *dev) {
Copied and modified: trunk/src/southbridge/intel/i82801cx/i82801cx_reset.c (from r5166, trunk/src/southbridge/intel/i82801ca/i82801ca_reset.c) ============================================================================== --- trunk/src/southbridge/intel/i82801ca/i82801ca_reset.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801cx/i82801cx_reset.c Sat Feb 27 02:50:21 2010 (r5167) @@ -1,6 +1,6 @@ #include <arch/io.h>
-void i82801ca_hard_reset(void) +void i82801cx_hard_reset(void) { /* Try rebooting through port 0xcf9 */ // Hard reset without power cycle
Copied and modified: trunk/src/southbridge/intel/i82801cx/i82801cx_smbus.c (from r5166, trunk/src/southbridge/intel/i82801ca/i82801ca_smbus.c) ============================================================================== --- trunk/src/southbridge/intel/i82801ca/i82801ca_smbus.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801cx/i82801cx_smbus.c Sat Feb 27 02:50:21 2010 (r5167) @@ -1,7 +1,7 @@ #include <smbus.h> #include <pci.h> #include <arch/io.h> -#include "i82801ca.h" +#include "i82801cx.h"
#define PM_BUS 0 #define PM_DEVFN PCI_DEVFN(0x1f,3)
Copied and modified: trunk/src/southbridge/intel/i82801cx/i82801cx_usb.c (from r5166, trunk/src/southbridge/intel/i82801ca/i82801ca_usb.c) ============================================================================== --- trunk/src/southbridge/intel/i82801ca/i82801ca_usb.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801cx/i82801cx_usb.c Sat Feb 27 02:50:21 2010 (r5167) @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801ca.h" +#include "i82801cx.h"
static void usb_init(struct device *dev) { @@ -28,7 +28,7 @@ .enable_resources = pci_dev_enable_resources, .init = usb_init, .scan_bus = 0, - .enable = i82801ca_enable, + .enable = i82801cx_enable, };
static const struct pci_driver usb_driver_1 __pci_driver = {
Modified: trunk/src/southbridge/intel/i82801dx/Kconfig ============================================================================== --- trunk/src/southbridge/intel/i82801dbm/Kconfig Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/southbridge/intel/i82801dx/Kconfig Sat Feb 27 02:50:21 2010 (r5167) @@ -1,2 +1,2 @@ -config SOUTHBRIDGE_INTEL_I82801DBM +config SOUTHBRIDGE_INTEL_I82801DX bool
Modified: trunk/src/southbridge/intel/i82801dx/Makefile.inc ============================================================================== --- trunk/src/southbridge/intel/i82801dbm/Makefile.inc Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/southbridge/intel/i82801dx/Makefile.inc Sat Feb 27 02:50:21 2010 (r5167) @@ -1,9 +1,9 @@ -driver-y += i82801dbm.o -driver-y += i82801dbm_usb.o -driver-y += i82801dbm_lpc.o -driver-y += i82801dbm_ide.o -driver-y += i82801dbm_usb2.o -driver-y += i82801dbm_ac97.o -#driver-y += i82801dbm_nic.o -#driver-y += i82801dbm_pci.o -obj-y += i82801dbm_reset.o +driver-y += i82801dx.o +driver-y += i82801dx_usb.o +driver-y += i82801dx_lpc.o +driver-y += i82801dx_ide.o +driver-y += i82801dx_usb2.o +driver-y += i82801dx_ac97.o +#driver-y += i82801dx_nic.o +#driver-y += i82801dx_pci.o +obj-y += i82801dx_reset.o
Modified: trunk/src/southbridge/intel/i82801dx/chip.h ============================================================================== --- trunk/src/southbridge/intel/i82801dbm/chip.h Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/southbridge/intel/i82801dx/chip.h Sat Feb 27 02:50:21 2010 (r5167) @@ -1,12 +1,27 @@ -#ifndef I82801DBM_CHIP_H -#define I82801DBM_CHIP_H +#ifndef I82801DX_CHIP_H +#define I82801DX_CHIP_H
-struct southbridge_intel_i82801dbm_config +struct southbridge_intel_i82801dx_config { int enable_usb; int enable_native_ide; + /** + * Interrupt Routing configuration + * If bit7 is 1, the interrupt is disabled. + */ + uint8_t pirqa_routing; + uint8_t pirqb_routing; + uint8_t pirqc_routing; + uint8_t pirqd_routing; + uint8_t pirqe_routing; + uint8_t pirqf_routing; + uint8_t pirqg_routing; + uint8_t pirqh_routing; + + uint8_t ide0_enable; + uint8_t ide1_enable; }; -struct chip_operations; -extern struct chip_operations southbridge_intel_i82801dbm_ops; + +extern struct chip_operations southbridge_intel_i82801dx_ops;
#endif /* I82801DBM_CHIP_H */
Copied and modified: trunk/src/southbridge/intel/i82801dx/i82801dx.c (from r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm.c) ============================================================================== --- trunk/src/southbridge/intel/i82801dbm/i82801dbm.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801dx/i82801dx.c Sat Feb 27 02:50:21 2010 (r5167) @@ -2,9 +2,9 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "i82801dbm.h" +#include "i82801dx.h"
-void i82801dbm_enable(device_t dev) +void i82801dx_enable(device_t dev) { unsigned int index = 0; uint8_t bHasDisableBit = 0; @@ -59,7 +59,7 @@ } }
-struct chip_operations southbridge_intel_i82801dbm_ops = { - CHIP_NAME("Intel 82801DBM Southbridge") - .enable_dev = i82801dbm_enable, +struct chip_operations southbridge_intel_i82801dx_ops = { + CHIP_NAME("Intel ICH4/ICH4-M (82801Dx) Series Southbridge") + .enable_dev = i82801dx_enable, };
Copied and modified: trunk/src/southbridge/intel/i82801dx/i82801dx.h (from r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm.h) ============================================================================== --- trunk/src/southbridge/intel/i82801dbm/i82801dbm.h Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801dx/i82801dx.h Sat Feb 27 02:50:21 2010 (r5167) @@ -6,11 +6,21 @@ * db stuff in fb1, and made sure it was right. */
-#ifndef I82801DBM_H -#define I82801DBM_H +#ifndef I82801DX_H +#define I82801DX_H
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) #include "chip.h" -extern void i82801dbm_enable(device_t dev); +extern void i82801dx_enable(device_t dev); +#endif + +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 +#define MAINBOARD_POWER_KEEP 2 + +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON +#endif
/* 000 = Non-combined. P0 is primary master. P1 is secondary master. @@ -32,6 +42,7 @@
#define PCICMD 0x04 #define PMBASE 0x40 +#define PMBASE_ADDR 0x0400 #define ACPI_CNTL 0x44 #define BIOS_CNTL 0x4E #define GPIO_BASE 0x58 @@ -78,4 +89,75 @@ */ #define SMBUS_TIMEOUT (100*1000)
-#endif /* I82801DBM_H */ +#define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) +#define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) +#define PM1_CNT 0x04 +#define SLP_EN (1 << 13) +#define SLP_TYP (7 << 10) +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) +#define PM1_TMR 0x08 +#define PROC_CNT 0x10 +#define LV2 0x14 +#define LV3 0x15 +#define LV4 0x16 +#define PM2_CNT 0x20 // mobile only +#define GPE0_STS 0x28 +#define PME_B0_STS (1 << 13) +#define USB3_STS (1 << 12) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define GST_STS (1 << 9) +#define RI_STS (1 << 8) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define AC97_STS (1 << 5) +#define USB2_STS (1 << 4) +#define USB1_STS (1 << 3) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) +#define THRM_STS (1 << 0) +#define GPE0_EN 0x2c +#define PME_B0_EN (1 << 13) +#define PME_EN (1 << 11) +#define SMI_EN 0x30 +#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology +#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic +#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic +#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS +#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) +#define MCSMI_EN (1 << 11) // Trap microcontroller range access +#define BIOS_RLS (1 << 7) // asserts SCI on bit set +#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set +#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# +#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# +#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic +#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit +#define EOS (1 << 1) // End of SMI (deassert SMI#) +#define GBL_SMI_EN (1 << 0) // SMI# generation at all? +#define SMI_STS 0x34 +#define ALT_GP_SMI_EN 0x38 +#define ALT_GP_SMI_STS 0x3a +#define GPE_CNTL 0x42 +#define DEVACT_STS 0x44 +#define SS_CNT 0x50 +#define C3_RES 0x54 + +#define TCOBASE 0x60 /* TCO Base Address Register */ +#define TCO1_CNT 0x08 /* TCO1 Control Register */ + +#endif /* I82801DX_H */
Copied and modified: trunk/src/southbridge/intel/i82801dx/i82801dx_ac97.c (from r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm_ac97.c) ============================================================================== --- trunk/src/southbridge/intel/i82801dbm/i82801dbm_ac97.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_ac97.c Sat Feb 27 02:50:21 2010 (r5167) @@ -6,14 +6,14 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801dbm.h" +#include "i82801dx.h"
static struct device_operations ac97audio_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .enable = i82801dbm_enable, + .enable = i82801dx_enable, .init = 0, .scan_bus = 0, }; @@ -29,7 +29,7 @@ .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .enable = i82801dbm_enable, + .enable = i82801dx_enable, .init = 0, .scan_bus = 0, };
Copied and modified: trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c (from r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c) ============================================================================== --- trunk/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c Sat Feb 27 02:50:21 2010 (r5167) @@ -1,6 +1,6 @@
//#define SMBUS_IO_BASE 0x1000 -#define SMBUS_IO_BASE 0x0f00 +//#define SMBUS_IO_BASE 0x0f00
#define SMBHSTSTAT 0x0 #define SMBHSTCTL 0x2 @@ -17,7 +17,7 @@ /* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. */ -#define SMBUS_TIMEOUT (100*1000*10) +//#define SMBUS_TIMEOUT (100*1000*10)
static void enable_smbus(void) {
Copied and modified: trunk/src/southbridge/intel/i82801dx/i82801dx_ide.c (from r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm_ide.c) ============================================================================== --- trunk/src/southbridge/intel/i82801dbm/i82801dbm_ide.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_ide.c Sat Feb 27 02:50:21 2010 (r5167) @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801dbm.h" +#include "i82801dx.h"
static void ide_init(struct device *dev) @@ -42,7 +42,7 @@ .enable_resources = pci_dev_enable_resources, .init = ide_init, .scan_bus = 0, - .enable = i82801dbm_enable, + .enable = i82801dx_enable, };
static const struct pci_driver ide_driver __pci_driver = {
Copied and modified: trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c (from r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c) ============================================================================== --- trunk/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Sat Feb 27 02:50:21 2010 (r5167) @@ -10,13 +10,13 @@ #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <arch/io.h> -#include "i82801dbm.h" +#include "i82801dx.h"
#define NMI_OFF 0
-void i82801dbm_enable_ioapic( struct device *dev) +void i82801dx_enable_ioapic( struct device *dev) { uint32_t dword; volatile uint32_t *ioapic_sba = (volatile uint32_t *)0xfec00000; @@ -46,11 +46,11 @@
} -void i82801dbm_enable_serial_irqs( struct device *dev) +void i82801dx_enable_serial_irqs( struct device *dev) { pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0)); } -void i82801dbm_lpc_route_dma( struct device *dev, uint8_t mask) +void i82801dx_lpc_route_dma( struct device *dev, uint8_t mask) { uint16_t word; int i; @@ -63,7 +63,7 @@ } pci_write_config16(dev, PCI_DMA_CFG, word); } -void i82801dbm_rtc_init(struct device *dev) +void i82801dx_rtc_init(struct device *dev) { uint8_t byte; uint32_t dword; @@ -80,7 +80,7 @@ }
-void i82801dbm_1f0_misc(struct device *dev) +void i82801dx_1f0_misc(struct device *dev) { pci_write_config16(dev, PCICMD, 0x014f); pci_write_config32(dev, PMBASE, 0x00001001); @@ -122,9 +122,9 @@ int nmi_option;
/* IO APIC initialization */ - i82801dbm_enable_ioapic(dev); + i82801dx_enable_ioapic(dev);
- i82801dbm_enable_serial_irqs(dev); + i82801dx_enable_serial_irqs(dev);
#ifdef SUSPICIOUS_LOOKING_CODE // The ICH-4 datasheet does not mention this configuration register. @@ -166,19 +166,19 @@ } /* Initialize the real time clock */ - i82801dbm_rtc_init(dev); + i82801dx_rtc_init(dev);
- i82801dbm_lpc_route_dma(dev, 0xff); + i82801dx_lpc_route_dma(dev, 0xff);
/* Initialize isa dma */ isa_dma_init();
- i82801dbm_1f0_misc(dev); + i82801dx_1f0_misc(dev); /* Initialize the High Precision Event Timers */ enable_hpet(dev); }
-static void i82801dbm_lpc_read_resources(device_t dev) +static void i82801dx_lpc_read_resources(device_t dev) { struct resource *res;
@@ -204,19 +204,19 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; }
-static void i82801dbm_lpc_enable_resources(device_t dev) +static void i82801dx_lpc_enable_resources(device_t dev) { pci_dev_enable_resources(dev); enable_childrens_resources(dev); }
static struct device_operations lpc_ops = { - .read_resources = i82801dbm_lpc_read_resources, + .read_resources = i82801dx_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = i82801dbm_lpc_enable_resources, + .enable_resources = i82801dx_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, - .enable = i82801dbm_enable, + .enable = i82801dx_enable, };
static const struct pci_driver lpc_driver __pci_driver = {
Copied and modified: trunk/src/southbridge/intel/i82801dx/i82801dx_nic.c (from r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm_nic.c) ============================================================================== --- trunk/src/southbridge/intel/i82801dbm/i82801dbm_nic.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_nic.c Sat Feb 27 02:50:21 2010 (r5167) @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801dbm.h" +#include "i82801dx.h"
static struct device_operations nic_ops = {
Copied and modified: trunk/src/southbridge/intel/i82801dx/i82801dx_pci.c (from r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm_pci.c) ============================================================================== --- trunk/src/southbridge/intel/i82801dbm/i82801dbm_pci.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_pci.c Sat Feb 27 02:50:21 2010 (r5167) @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801dbm.h" +#include "i82801dx.h"
static void pci_init(struct device *dev) {
Copied: trunk/src/southbridge/intel/i82801dx/i82801dx_reset.c (from r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm_reset.c) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_reset.c Sat Feb 27 02:50:21 2010 (r5167, copy of r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm_reset.c) @@ -0,0 +1,7 @@ +#include <arch/io.h> + +void hard_reset(void) +{ + /* Try rebooting through port 0xcf9 */ + outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); +}
Copied and modified: trunk/src/southbridge/intel/i82801dx/i82801dx_sata.c (from r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm_sata.c) ============================================================================== --- trunk/src/southbridge/intel/i82801dbm/i82801dbm_sata.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_sata.c Sat Feb 27 02:50:21 2010 (r5167) @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801dbm.h" +#include "i82801dx.h"
static void sata_init(struct device *dev) { @@ -64,7 +64,7 @@ .enable_resources = pci_dev_enable_resources, .init = sata_init, .scan_bus = 0, - .enable = i82801dbm_enable, + .enable = i82801dx_enable, };
static const struct pci_driver stat_driver __pci_driver = {
Copied and modified: trunk/src/southbridge/intel/i82801dx/i82801dx_smbus.c (from r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm_smbus.c) ============================================================================== --- trunk/src/southbridge/intel/i82801dbm/i82801dbm_smbus.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_smbus.c Sat Feb 27 02:50:21 2010 (r5167) @@ -1,3 +1,4 @@ +#include "i82801dx.h" #include <smbus.h> #include <pci.h> #include <arch/io.h> @@ -5,6 +6,7 @@ #define PM_BUS 0 #define PM_DEVFN PCI_DEVFN(0x1f,3)
+#if 0 #define SMBUS_IO_BASE 0x1000 #define SMBHSTSTAT 0 #define SMBHSTCTL 2 @@ -13,6 +15,7 @@ #define SMBHSTDAT0 5 #define SMBHSTDAT1 6 #define SMBBLKDAT 7 +#endif
void smbus_enable(void) {
Copied and modified: trunk/src/southbridge/intel/i82801dx/i82801dx_usb.c (from r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm_usb.c) ============================================================================== --- trunk/src/southbridge/intel/i82801dbm/i82801dbm_usb.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_usb.c Sat Feb 27 02:50:21 2010 (r5167) @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801dbm.h" +#include "i82801dx.h"
static void usb_init(struct device *dev) { @@ -29,7 +29,7 @@ .enable_resources = pci_dev_enable_resources, .init = usb_init, .scan_bus = 0, - .enable = i82801dbm_enable, + .enable = i82801dx_enable, };
static const struct pci_driver usb_driver_1 __pci_driver = {
Copied and modified: trunk/src/southbridge/intel/i82801dx/i82801dx_usb2.c (from r5166, trunk/src/southbridge/intel/i82801dbm/i82801dbm_usb2.c) ============================================================================== --- trunk/src/southbridge/intel/i82801dbm/i82801dbm_usb2.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_usb2.c Sat Feb 27 02:50:21 2010 (r5167) @@ -5,7 +5,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801dbm.h" +#include "i82801dx.h"
static void usb2_init(struct device *dev) { @@ -30,7 +30,7 @@ .enable_resources = pci_dev_enable_resources, .init = usb2_init, .scan_bus = 0, - .enable = i82801dbm_enable, + .enable = i82801dx_enable, };
static const struct pci_driver usb2_driver __pci_driver = {
Modified: trunk/src/southbridge/intel/i82801ex/Kconfig ============================================================================== --- trunk/src/southbridge/intel/i82801er/Kconfig Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/southbridge/intel/i82801ex/Kconfig Sat Feb 27 02:50:21 2010 (r5167) @@ -1,3 +1,3 @@ -config SOUTHBRIDGE_INTEL_I82801ER +config SOUTHBRIDGE_INTEL_I82801EX bool select IOAPIC
Modified: trunk/src/southbridge/intel/i82801ex/Makefile.inc ============================================================================== --- trunk/src/southbridge/intel/i82801er/Makefile.inc Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/southbridge/intel/i82801ex/Makefile.inc Sat Feb 27 02:50:21 2010 (r5167) @@ -1,11 +1,11 @@ -driver-y += i82801er.o -driver-y += i82801er_uhci.o -driver-y += i82801er_lpc.o -driver-y += i82801er_ide.o -driver-y += i82801er_sata.o -driver-y += i82801er_ehci.o -driver-y += i82801er_smbus.o -driver-y += i82801er_pci.o -driver-y += i82801er_ac97.o -obj-y += i82801er_watchdog.o -obj-y += i82801er_reset.o +driver-y += i82801ex.o +driver-y += i82801ex_uhci.o +driver-y += i82801ex_lpc.o +driver-y += i82801ex_ide.o +driver-y += i82801ex_sata.o +driver-y += i82801ex_ehci.o +driver-y += i82801ex_smbus.o +driver-y += i82801ex_pci.o +driver-y += i82801ex_ac97.o +obj-y += i82801ex_watchdog.o +obj-y += i82801ex_reset.o
Modified: trunk/src/southbridge/intel/i82801ex/chip.h ============================================================================== --- trunk/src/southbridge/intel/i82801er/chip.h Fri Feb 26 21:32:08 2010 (r5166) +++ trunk/src/southbridge/intel/i82801ex/chip.h Sat Feb 27 02:50:21 2010 (r5167) @@ -1,7 +1,7 @@ -#ifndef I82801ER_CHIP_H -#define I82801ER_CHIP_H +#ifndef I82801EX_CHIP_H +#define I82801EX_CHIP_H
-struct southbridge_intel_i82801er_config +struct southbridge_intel_i82801ex_config {
#define ICH5R_GPIO_USE_MASK 0x03 @@ -30,7 +30,7 @@ unsigned int pirq_a_d; unsigned int pirq_e_h; }; -extern struct chip_operations southbridge_intel_i82801er_ops; +extern struct chip_operations southbridge_intel_i82801ex_ops;
-#endif /* I82801ER_CHIP_H */ +#endif /* I82801EX_CHIP_H */
Copied and modified: trunk/src/southbridge/intel/i82801ex/i82801ex.c (from r5166, trunk/src/southbridge/intel/i82801er/i82801er.c) ============================================================================== --- trunk/src/southbridge/intel/i82801er/i82801er.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801ex/i82801ex.c Sat Feb 27 02:50:21 2010 (r5167) @@ -2,15 +2,15 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "i82801er.h" +#include "i82801ex.h"
-void i82801er_enable(device_t dev) +void i82801ex_enable(device_t dev) { device_t lpc_dev; unsigned index = 0; uint16_t reg_old, reg;
- /* See if we are behind the i82801er pci bridge */ + /* See if we are behind the i82801ex pci bridge */ lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0)); if((dev->path.pci.devfn &0xf8)== 0xf8) { index = dev->path.pci.devfn & 7; @@ -42,7 +42,7 @@ }
-struct chip_operations southbridge_intel_i82801er_ops = { - CHIP_NAME("Intel 82801ER Southbridge") - .enable_dev = i82801er_enable, +struct chip_operations southbridge_intel_i82801ex_ops = { + CHIP_NAME("Intel ICH5 (82801Ex) Series Southbridge") + .enable_dev = i82801ex_enable, };
Copied and modified: trunk/src/southbridge/intel/i82801ex/i82801ex.h (from r5166, trunk/src/southbridge/intel/i82801er/i82801er.h) ============================================================================== --- trunk/src/southbridge/intel/i82801er/i82801er.h Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801ex/i82801ex.h Sat Feb 27 02:50:21 2010 (r5167) @@ -1,9 +1,9 @@ -#ifndef I82801ER_H -#define I82801ER_H +#ifndef I82801EX_H +#define I82801EX_H
#include "chip.h"
-extern void i82801er_enable(device_t dev); +extern void i82801ex_enable(device_t dev);
#define PCI_DMA_CFG 0x90 #define SERIRQ_CNTL 0x64 @@ -12,4 +12,4 @@ #define RTC_CONF 0xd8 #define GEN_PMCON_3 0xa4
-#endif /* I82801ER_H */ +#endif /* I82801EX_H */
Copied and modified: trunk/src/southbridge/intel/i82801ex/i82801ex_ac97.c (from r5166, trunk/src/southbridge/intel/i82801er/i82801er_ac97.c) ============================================================================== --- trunk/src/southbridge/intel/i82801er/i82801er_ac97.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801ex/i82801ex_ac97.c Sat Feb 27 02:50:21 2010 (r5167) @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801er.h" +#include "i82801ex.h"
static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device) { @@ -21,7 +21,7 @@ .enable_resources = pci_dev_enable_resources, .init = 0, .scan_bus = 0, - .enable = i82801er_enable, + .enable = i82801ex_enable, .ops_pci = &lops_pci, };
Copied and modified: trunk/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c (from r5166, trunk/src/southbridge/intel/i82801er/i82801er_early_smbus.c) ============================================================================== --- trunk/src/southbridge/intel/i82801er/i82801er_early_smbus.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c Sat Feb 27 02:50:21 2010 (r5167) @@ -1,4 +1,4 @@ -#include "i82801er_smbus.h" +#include "i82801ex_smbus.h"
#define SMBUS_IO_BASE 0x0f00
Copied and modified: trunk/src/southbridge/intel/i82801ex/i82801ex_ehci.c (from r5166, trunk/src/southbridge/intel/i82801er/i82801er_ehci.c) ============================================================================== --- trunk/src/southbridge/intel/i82801er/i82801er_ehci.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801ex/i82801ex_ehci.c Sat Feb 27 02:50:21 2010 (r5167) @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801er.h" +#include "i82801ex.h"
static void ehci_init(struct device *dev) { @@ -39,7 +39,7 @@ .enable_resources = pci_dev_enable_resources, .init = ehci_init, .scan_bus = 0, - .enable = i82801er_enable, + .enable = i82801ex_enable, .ops_pci = &lops_pci, };
Copied and modified: trunk/src/southbridge/intel/i82801ex/i82801ex_ide.c (from r5166, trunk/src/southbridge/intel/i82801er/i82801er_ide.c) ============================================================================== --- trunk/src/southbridge/intel/i82801er/i82801er_ide.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801ex/i82801ex_ide.c Sat Feb 27 02:50:21 2010 (r5167) @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801er.h" +#include "i82801ex.h"
static void ide_init(struct device *dev) { @@ -16,7 +16,7 @@ printk_debug("IDE Enabled\n"); }
-static void i82801er_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void i82801ex_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device) { /* This value is also visible in uchi[0-2] and smbus functions */ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -24,7 +24,7 @@ }
static struct pci_operations lops_pci = { - .set_subsystem = i82801er_ide_set_subsystem, + .set_subsystem = i82801ex_ide_set_subsystem, }; static struct device_operations ide_ops = { .read_resources = pci_dev_read_resources,
Copied and modified: trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c (from r5166, trunk/src/southbridge/intel/i82801er/i82801er_lpc.c) ============================================================================== --- trunk/src/southbridge/intel/i82801er/i82801er_lpc.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c Sat Feb 27 02:50:21 2010 (r5167) @@ -10,7 +10,7 @@ #include <pc80/isa-dma.h> #include <arch/io.h> #include <arch/ioapic.h> -#include "i82801er.h" +#include "i82801ex.h"
#define ACPI_BAR 0x40 #define GPIO_BAR 0x58 @@ -24,7 +24,7 @@ #endif
#define SERIRQ_CNTL 0x64 -static void i82801er_enable_serial_irqs(device_t dev) +static void i82801ex_enable_serial_irqs(device_t dev) { /* set packet length and toggle silent mode bit */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0)); @@ -32,22 +32,22 @@ }
#define PCI_DMA_CFG 0x90 -static void i82801er_pci_dma_cfg(device_t dev) +static void i82801ex_pci_dma_cfg(device_t dev) { /* Set PCI DMA CFG to lpc I/F DMA */ pci_write_config16(dev, PCI_DMA_CFG, 0xfcff); }
#define LPC_EN 0xe6 -static void i82801er_enable_lpc(device_t dev) +static void i82801ex_enable_lpc(device_t dev) { /* lpc i/f enable */ pci_write_config8(dev, LPC_EN, 0x0d); }
-typedef struct southbridge_intel_i82801er_config config_t; +typedef struct southbridge_intel_i82801ex_config config_t;
-static void set_i82801er_gpio_use_sel( +static void set_i82801ex_gpio_use_sel( device_t dev, struct resource *res, config_t *config) { uint32_t gpio_use_sel, gpio_use_sel2; @@ -76,7 +76,7 @@ outl(gpio_use_sel2, res->base + 0x30); }
-static void set_i82801er_gpio_direction( +static void set_i82801ex_gpio_direction( device_t dev, struct resource *res, config_t *config) { uint32_t gpio_io_sel, gpio_io_sel2; @@ -105,7 +105,7 @@ outl(gpio_io_sel2, res->base + 0x34); }
-static void set_i82801er_gpio_level( +static void set_i82801ex_gpio_level( device_t dev, struct resource *res, config_t *config) { uint32_t gpio_lvl, gpio_lvl2; @@ -140,7 +140,7 @@ outl(gpio_lvl2, res->base + 0x38); }
-static void set_i82801er_gpio_inv( +static void set_i82801ex_gpio_inv( device_t dev, struct resource *res, config_t *config) { uint32_t gpio_inv; @@ -161,7 +161,7 @@ outl(gpio_inv, res->base + 0x2c); }
-static void i82801er_pirq_init(device_t dev) +static void i82801ex_pirq_init(device_t dev) { config_t *config;
@@ -177,7 +177,7 @@ }
-static void i82801er_gpio_init(device_t dev) +static void i82801ex_gpio_init(device_t dev) { struct resource *res; config_t *config; @@ -199,16 +199,16 @@ }
/* Set the use selects */ - set_i82801er_gpio_use_sel(dev, res, config); + set_i82801ex_gpio_use_sel(dev, res, config);
/* Set the IO direction */ - set_i82801er_gpio_direction(dev, res, config); + set_i82801ex_gpio_direction(dev, res, config);
/* Setup the input inverters */ - set_i82801er_gpio_inv(dev, res, config); + set_i82801ex_gpio_inv(dev, res, config);
/* Set the value on the GPIO output pins */ - set_i82801er_gpio_level(dev, res, config); + set_i82801ex_gpio_level(dev, res, config);
}
@@ -250,11 +250,11 @@ pci_write_config32(dev, 0xd4, value); setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IO APIC ID.
- i82801er_enable_serial_irqs(dev); + i82801ex_enable_serial_irqs(dev);
- i82801er_pci_dma_cfg(dev); + i82801ex_pci_dma_cfg(dev);
- i82801er_enable_lpc(dev); + i82801ex_enable_lpc(dev);
/* Clear SATA to non raid */ pci_write_config8(dev, 0xae, 0x00); @@ -269,10 +269,10 @@ printk_info("set power %s after power fail\n", pwr_on?"on":"off");
/* Set up the PIRQ */ - i82801er_pirq_init(dev); + i82801ex_pirq_init(dev); /* Set the state of the gpio lines */ - i82801er_gpio_init(dev); + i82801ex_gpio_init(dev);
/* Initialize the real time clock */ rtc_init(0); @@ -286,7 +286,7 @@ enable_hpet(dev); }
-static void i82801er_lpc_read_resources(device_t dev) +static void i82801ex_lpc_read_resources(device_t dev) { struct resource *res;
@@ -318,7 +318,7 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; }
-static void i82801er_lpc_enable_resources(device_t dev) +static void i82801ex_lpc_enable_resources(device_t dev) { uint8_t acpi_cntl, gpio_cntl;
@@ -343,12 +343,12 @@ };
static struct device_operations lpc_ops = { - .read_resources = i82801er_lpc_read_resources, + .read_resources = i82801ex_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = i82801er_lpc_enable_resources, + .enable_resources = i82801ex_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, - .enable = i82801er_enable, + .enable = i82801ex_enable, .ops_pci = &lops_pci, };
Copied and modified: trunk/src/southbridge/intel/i82801ex/i82801ex_pci.c (from r5166, trunk/src/southbridge/intel/i82801er/i82801er_pci.c) ============================================================================== --- trunk/src/southbridge/intel/i82801er/i82801er_pci.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801ex/i82801ex_pci.c Sat Feb 27 02:50:21 2010 (r5167) @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801er.h" +#include "i82801ex.h"
static void pci_init(struct device *dev) {
Copied and modified: trunk/src/southbridge/intel/i82801ex/i82801ex_reset.c (from r5166, trunk/src/southbridge/intel/i82801er/i82801er_reset.c) ============================================================================== --- trunk/src/southbridge/intel/i82801er/i82801er_reset.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801ex/i82801ex_reset.c Sat Feb 27 02:50:21 2010 (r5167) @@ -1,6 +1,6 @@ #include <arch/io.h>
-void i82801er_hard_reset(void) +void i82801ex_hard_reset(void) { /* Try rebooting through port 0xcf9 */ outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
Copied and modified: trunk/src/southbridge/intel/i82801ex/i82801ex_sata.c (from r5166, trunk/src/southbridge/intel/i82801er/i82801er_sata.c) ============================================================================== --- trunk/src/southbridge/intel/i82801er/i82801er_sata.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801ex/i82801ex_sata.c Sat Feb 27 02:50:21 2010 (r5167) @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801er.h" +#include "i82801ex.h"
static void sata_init(struct device *dev) {
Copied and modified: trunk/src/southbridge/intel/i82801ex/i82801ex_smbus.c (from r5166, trunk/src/southbridge/intel/i82801er/i82801er_smbus.c) ============================================================================== --- trunk/src/southbridge/intel/i82801er/i82801er_smbus.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801ex/i82801ex_smbus.c Sat Feb 27 02:50:21 2010 (r5167) @@ -5,8 +5,8 @@ #include <device/pci_ops.h> #include <device/smbus.h> #include <arch/io.h> -#include "i82801er.h" -#include "i82801er_smbus.h" +#include "i82801ex.h" +#include "i82801ex_smbus.h"
static int lsmbus_read_byte(struct bus *bus, device_t dev, uint8_t address) { @@ -32,7 +32,7 @@ .enable_resources = pci_dev_enable_resources, .init = 0, .scan_bus = scan_static_bus, - .enable = i82801er_enable, + .enable = i82801ex_enable, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, };
Copied: trunk/src/southbridge/intel/i82801ex/i82801ex_smbus.h (from r5166, trunk/src/southbridge/intel/i82801er/i82801er_smbus.h) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/intel/i82801ex/i82801ex_smbus.h Sat Feb 27 02:50:21 2010 (r5167, copy of r5166, trunk/src/southbridge/intel/i82801er/i82801er_smbus.h) @@ -0,0 +1,105 @@ +#include <device/smbus_def.h> + +#define SMBHSTSTAT 0x0 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBBLKDAT 0x7 +#define SMBTRNSADD 0x9 +#define SMBSLVDATA 0xa +#define SMLINK_PIN_CTL 0xe +#define SMBUS_PIN_CTL 0xf + +#define SMBUS_TIMEOUT (100*1000*10) + + +static void smbus_delay(void) +{ + outb(0x80, 0x80); +} + +static int smbus_wait_until_ready(unsigned smbus_io_base) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(smbus_io_base + SMBHSTSTAT); + } while(byte & 1); + return loops?0:-1; +} + +static int smbus_wait_until_done(unsigned smbus_io_base) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(smbus_io_base + SMBHSTSTAT); + } while((byte & 1) || (byte & ~((1<<6)|(1<<0))) == 0); + return loops?0:-1; +} + +static int smbus_wait_until_blk_done(unsigned smbus_io_base) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(smbus_io_base + SMBHSTSTAT); + } while((byte&(1<<7)) == 0); + return loops?0:-1; +} + +static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) +{ + unsigned char global_status_register; + unsigned char byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } + /* setup transaction */ + /* disable interrupts */ + outb(inb(smbus_io_base + SMBHSTCTL) & (~1), smbus_io_base + SMBHSTCTL); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); + /* set the command/address... */ + outb(address & 0xFF, smbus_io_base + SMBHSTCMD); + /* set up for a byte data read */ + outb((inb(smbus_io_base + SMBHSTCTL) & 0xE3) | (0x2 << 2), smbus_io_base + SMBHSTCTL); + /* clear any lingering errors, so the transaction will run */ + outb(inb(smbus_io_base + SMBHSTSTAT), smbus_io_base + SMBHSTSTAT); + + /* clear the data byte...*/ + outb(0, smbus_io_base + SMBHSTDAT0); + + /* start the command */ + outb((inb(smbus_io_base + SMBHSTCTL) | 0x40), smbus_io_base + SMBHSTCTL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + } + + global_status_register = inb(smbus_io_base + SMBHSTSTAT); + + /* Ignore the In Use Status... */ + global_status_register &= ~(3 << 5); + + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTDAT0); + if (global_status_register != (1 << 1)) { + return SMBUS_ERROR; + } + return byte; +} +
Copied and modified: trunk/src/southbridge/intel/i82801ex/i82801ex_uhci.c (from r5166, trunk/src/southbridge/intel/i82801er/i82801er_uhci.c) ============================================================================== --- trunk/src/southbridge/intel/i82801er/i82801er_uhci.c Fri Feb 26 21:32:08 2010 (r5166, copy source) +++ trunk/src/southbridge/intel/i82801ex/i82801ex_uhci.c Sat Feb 27 02:50:21 2010 (r5167) @@ -3,7 +3,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "i82801er.h" +#include "i82801ex.h"
static void uhci_init(struct device *dev) { @@ -32,7 +32,7 @@ .enable_resources = pci_dev_enable_resources, .init = uhci_init, .scan_bus = 0, - .enable = i82801er_enable, + .enable = i82801ex_enable, .ops_pci = &lops_pci, };
Copied: trunk/src/southbridge/intel/i82801ex/i82801ex_watchdog.c (from r5166, trunk/src/southbridge/intel/i82801er/i82801er_watchdog.c) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/intel/i82801ex/i82801ex_watchdog.c Sat Feb 27 02:50:21 2010 (r5167, copy of r5166, trunk/src/southbridge/intel/i82801er/i82801er_watchdog.c) @@ -0,0 +1,28 @@ +#include <console/console.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> + +void watchdog_off(void) +{ + device_t dev; + unsigned long value,base; + + /* turn off the ICH5 watchdog */ + dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + /* Enable I/O space */ + value = pci_read_config16(dev, 0x04); + value |= (1 << 10); + pci_write_config16(dev, 0x04, value); + /* Get TCO base */ + base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; + /* Disable the watchdog timer */ + value = inw(base + 0x08); + value |= 1 << 11; + outw(value, base + 0x08); + /* Clear TCO timeout status */ + outw(0x0008, base + 0x04); + outw(0x0002, base + 0x06); + printk_debug("Watchdog ICH5 disabled\r\n"); +} +
-
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