RE: PCI IRQ tables

[YhLu]

It's the same if you enable io apic.

In the irq-table.

Add 
Entry Bus 1 for 8111 and 8131
Other 8131 bus may be discovered by Kernel.

Regards

YH

-----Original Message-----
From: Liu Tao [mailto:[e-mail]] 
Sent: Monday, October 18, 2004 2:50 AM
To: YhLu
Cc: Dave Aubin; [e-mail]
Subject: Re: PCI IRQ tables

YhLu wrote:
> SMP or single CPU?
>
> If SMP, and io apci is enabled, you may only focus on mptable.c and
> irq-tables.c may only contain device that point to the peer roots bus.
>
> YH

How about single CPU with IO-APIC enabled in linux?

We are designing a new AMD64 mainboard and want to use linuxbios,
the IO architecture is showed in the attached picture. I'm not
sure how to specify the "PCI IRQ Router" in pirq table for this 
architecture. Since each AMD8131 and AMD8111 all provide legacy
PIC mode interrupt controller, I think maybe there isn't a global
legacy PIC mode PCI IRQ router for different NCHT channels?
Maybe APIC is the better choice?

Best Regards,
Liu Tao

PCI IRQ tables

[Liu Tao]

Hello,

Thanks for your answer:)
But I'm still not very clear of the PCI interrupt
routing for legacy PIC mode on AMD64. For example in
s2885 mainboard the pirq table specifys the AMD8111
as the interrupt router (bus1 dev4 fn3), then how
does the interrupt from the PCIX devices on AMD8131
routed to CPU?

Or does the interrupt router in pirq table only
responses of legacy 32bitPCI/ISA devices, and Linux
handles all the AMD8131?

Another question is, if use IO-APIC, does linuxbios
specify the bus/devfn in mptable and let linux
do the real job of setting the IO-APIC registers?

Best Regards,
Liu Tao

YhLu wrote:
> It's the same if you enable io apic.
>
> In the irq-table.
>
> Add
> Entry Bus 1 for 8111 and 8131
> Other 8131 bus may be discovered by Kernel.

PCI IRQ tables

On Tue, Oct 19, 2004 at 12:12:50PM +0800, Liu Tao wrote:
> Or does the interrupt router in pirq table only
> responses of legacy 32bitPCI/ISA devices, and Linux
> handles all the AMD8131?

Forgive my ignorance, but doesn't the fact that PCI-X is all message
signaled interrupts obviate the need for a PCIIRQ table?

PCI IRQ tables

[Yinghai Lu]

To use PIC in you configuration, you need program 8111 0x56 about int
routing

/* initialize PCI interupts - these assignments
depend
                        on the PCB routing of PINTA-D

PINTA = IRQ5
                        PINTB = IRQ9
                        PINTC = IRQ11
                        PINTD = IRQ10
                        */
                        pci_write_config16(dev, 0x56, 0xab95);

Then you need to program  all device in PCI-X slot with
        printk_info("setting Slot 2\n");
        static const unsigned char slotIrqs_8131_2_1[4] = { 9, 11, 10, 5 };
        pci_assign_irqs(bus_8131_2, 1, slotIrqs_8131_2_1);
that will update the interrupt line for every device in slot.

Please remember you need to make sure your HW connection about INT.

Then you can use NO SMP Kernel with apic disabled.

Regards

YH

-----Original Message-----
From: Liu Tao [mailto:[e-mail]] 
Sent: Monday, October 18, 2004 9:13 PM
To: YhLu
Cc: Dave Aubin; [e-mail]
Subject: Re: PCI IRQ tables

Hello,

Thanks for your answer:)
But I'm still not very clear of the PCI interrupt
routing for legacy PIC mode on AMD64. For example in
s2885 mainboard the pirq table specifys the AMD8111
as the interrupt router (bus1 dev4 fn3), then how
does the interrupt from the PCIX devices on AMD8131
routed to CPU?

Or does the interrupt router in pirq table only
responses of legacy 32bitPCI/ISA devices, and Linux
handles all the AMD8131?

Another question is, if use IO-APIC, does linuxbios
specify the bus/devfn in mptable and let linux
do the real job of setting the IO-APIC registers?

Best Regards,
Liu Tao

YhLu wrote:
> It's the same if you enable io apic.
>
> In the irq-table.
>
> Add
> Entry Bus 1 for 8111 and 8131
> Other 8131 bus may be discovered by Kernel.