Any suggestions? The top block swap in intel's ICH2 helps, but the ICH/ICH0 doesn't have that feature, and that's what the Dell Optiplex GX110 has.
Has anyone run across a prototyping socket for a TSOP?
Jeremy Jackson wrote:
Any suggestions? The top block swap in intel's ICH2 helps, but the ICH/ICH0 doesn't have that feature, and that's what the Dell Optiplex GX110 has.
Has anyone run across a prototyping socket for a TSOP?
How much space do you have for a ZIF TSOP socket?
-Bari
Another thought occurs... what about putting an SBC in the PCI slot? I guess the first issue would be making sure there's only one PCI bus arbiter. In the case of the SBC, is that usually on the backplane or the SBC motherboard?
It would be real slick to pop the SBC into a motherboard with bad code in the soldered in flash chip, and re-flash it.
Bari Ari wrote:
Jeremy Jackson wrote:
Any suggestions? The top block swap in intel's ICH2 helps, but the ICH/ICH0 doesn't have that feature, and that's what the Dell Optiplex GX110 has.
Has anyone run across a prototyping socket for a TSOP?
How much space do you have for a ZIF TSOP socket?
Jeremy Jackson wrote:
Another thought occurs... what about putting an SBC in the PCI slot? I guess the first issue would be making sure there's only one PCI bus arbiter.
Or having a proper PCI bridge in place.
In the case of the SBC, is that usually on the backplane or
the SBC motherboard?
Backplanes and SBC's come however you spec them.
It would be real slick to pop the SBC into a motherboard with bad code in the soldered in flash chip, and re-flash it.
Even if you had the proper PCI bridge setup the SBC would not be able to access the motherboard's flash since the motherboard's BIOS (in your example) is bad so the motherboard's hardware would not be properly initialized to handle the transaction.
-Bari
Bari Ari wrote:
Even if you had the proper PCI bridge setup the SBC would not be able to access the motherboard's flash since the motherboard's BIOS (in your example) is bad so the motherboard's hardware would not be properly initialized to handle the transaction.
Well, at least from the host (CPU) 's prespective, the BIOS is the one thing that must be configured at power on reset.
You're right though, there's no guarantee that a PCI master/bridge could access the BIOS without the host initializing things.
My current thought is to do it the other way around, to have a PCI target on a plugin adapter, that decodes the BIOS region. At least on the i8xx ICH/ICH2, the southbridge powers up in subtractive decode mode. The datasheets describe this specific scenario as being possible.
I haven't seen such a card on google, so i've been giving some thought to the following hacks:
Option A: This wouldn't allow flashing the bios on a dead board, but it would allow getting Linuxbios working 100% before committing to the point of no return (flashing the soldered in part):
Take a PCI NIC with a rom socket. put a switch on the PCI RESET# line. close the switch. boot from vendor bios. flash the NIC boot rom. set the NIC BAR to 0xffff0000. open the switch. reset the system. it will now use the NIC rom as the BIOS rom.
Option B:
As above, but set the BAR with the card in a working system. open the reset switch. keeping the card powered, put it in the dead system, and it should boot from the PCI card. Well there's some fantasy involved in this one :)
Cheers,
Jeremy
On Fri, Sep 03, 2004 at 03:55:42PM -0400, Jeremy Jackson wrote:
Has anyone run across a prototyping socket for a TSOP?
Yes.
Emulation Technology has test sockets for TSOP packages.
http://www.emulation.com/catalog/off-the-shelf_solutions/sockets/tsop/
I got a quote for single pieces at $15 or so a while back from a local distributor here in Sweden.
//Peter
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Bari Ari -
Jeremy Jackson -
Peter Stuge