hi Vadim, i am trying to flashing the gigabyte dual bios at this moment, have you ever tried to boot coreboot from the main bios? i flashed the main bios, but the board always did the checksum failed, the restore the bios to the legacy bios. Have you ever tried that? if flash the backup chip, how to make it boot first?
Qing Pei Wang wrote:
i flashed the main bios, but the board always did the checksum failed,
I believe this happens because coreboot does not perform the special handshake before the patented timer expires.
the restore the bios to the legacy bios. Have you ever tried that? if flash the backup chip, how to make it boot first?
I think it should work if you flash both flash chips with coreboot. Then it will try to start from the first one, expire the timer, then start from the second one.
//Peter
In this context I would really appreciate "unabridged" version of ITE IT8718F-S specification.
If someone could "somehow" share it, it would be terrific.
Andriy Gapon wrote:
In this context I would really appreciate "unabridged" version of ITE IT8718F-S specification.
Maybe you already know this, but I would not expect the superio to be involved very much in the dualbios mechanism - at most an IO pin would be used for the handshake with the patented timer.
//Peter
on 14/07/2010 23:25 Peter Stuge said the following:
Andriy Gapon wrote:
In this context I would really appreciate "unabridged" version of ITE IT8718F-S specification.
Maybe you already know this, but I would not expect the superio to be involved very much in the dualbios mechanism - at most an IO pin would be used for the handshake with the patented timer.
Still I would like to get the spec.
It may also depend on a particular motherboard, chip, etc. Perhaps the "patented timer" is implemented in Super I/O. At least, we see that some undocumented Super I/O register(s) are used to switch between the flash chips and some other related things.
Andriy Gapon wrote:
Maybe you already know this, but I would not expect the superio to be involved very much in the dualbios mechanism - at most an IO pin would be used for the handshake with the patented timer.
Still I would like to get the spec.
Yes, fair enough. :)
It may also depend on a particular motherboard, chip, etc. Perhaps the "patented timer" is implemented in Super I/O.
I doubt this since Gigabyte owns the patent for the dual bios invention, and ITE is unrelated to Gigabyte. The dual bios invention might *use* a timer within the superio though - that's possible.
At least, we see that some undocumented Super I/O register(s) are used to switch between the flash chips and some other related things.
IO pins and timer on the superio could certainly be used.
//Peter
Hi,
On 15.07.2010 16:29, Peter Stuge wrote:
Andriy Gapon wrote:
Maybe you already know this, but I would not expect the superio to be involved very much in the dualbios mechanism - at most an IO pin would be used for the handshake with the patented timer.
Still I would like to get the spec.
Yes, fair enough. :)
It may also depend on a particular motherboard, chip, etc. Perhaps the "patented timer" is implemented in Super I/O.
I doubt this since Gigabyte owns the patent for the dual bios invention, and ITE is unrelated to Gigabyte. The dual bios invention might *use* a timer within the superio though - that's possible.
At least, we see that some undocumented Super I/O register(s) are used to switch between the flash chips and some other related things.
IO pins and timer on the superio could certainly be used.
Did you know that SB700 (and later) has its own Dual BIOS mechanism? If there is interest, I can help with implementing support for that feature in flashrom.
Regards, Carl-Daniel
on 15/07/2010 21:09 Carl-Daniel Hailfinger said the following:
Did you know that SB700 (and later) has its own Dual BIOS mechanism? If there is interest, I can help with implementing support for that feature in flashrom.
Does that mechanism require that flash chips are wired to the south bridge (handled by its SPI controller)? Or is it a more generic mechanism?
i think the spi chips are wired to both south bridge and super I/O. carl: i do not think that SB700 has this mechanism, it must be the time circuit of this patent. i find that before booting bios, there is several seconds delay after powering up.
On Fri, Jul 16, 2010 at 3:17 PM, Andriy Gapon avg@icyb.net.ua wrote:
on 15/07/2010 21:09 Carl-Daniel Hailfinger said the following:
Did you know that SB700 (and later) has its own Dual BIOS mechanism? If there is interest, I can help with implementing support for that feature in flashrom.
Does that mechanism require that flash chips are wired to the south bridge (handled by its SPI controller)? Or is it a more generic mechanism?
-- Andriy Gapon
-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
on 16/07/2010 16:29 Qing Pei Wang said the following:
i think the spi chips are wired to both south bridge and super I/O.
On my mobo they are definitely wired to Super I/O only. That doesn't preclude, of course, Super I/O being wired to SB :-)
Carl-Daniel Hailfinger wrote:
Did you know that SB700 (and later) has its own Dual BIOS mechanism?
I did not. Do you know more details?
//Peter
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Andriy Gapon -
Carl-Daniel Hailfinger -
Peter Stuge -
Qing Pei Wang