Re: [coreboot] installing Coreboot to T60(MX25L1605AM2C flash chip)

[Peter Stuge]

Martin T wrote:
> What is the correct definition of my flash chip in flashchips.c file?
>
> .name           = "MX25L1605D/MX25L1608D",

This one.
> I wasn't able to find the exact data sheet.

Look for MX25L1605D.


//Peter

installing Coreboot to T60(MX25L1605AM2C flash chip)

[The Gluglug]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

.model_id 0x14

.probe probe_spi_res1

.write spi_chip_write_1

On 08/07/14 15:26, Peter Stuge wrote:
> Martin T wrote:
> > What is the correct definition of my flash chip in flashchips.c
> > file?
> >
> > .name           = "MX25L1605D/MX25L1608D",
>
> This one.
> > I wasn't able to find the exact data sheet.
>
> Look for MX25L1605D.
>
> //Peter

-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/

iQEcBAEBAgAGBQJTvAplAAoJEP9Ft0z50c+U+gEH/jnEUD8mxiipwdHAw2hTx8TN
dlnjEzNtRnjCg4zSiFPf7AUmzTyE89H47H00VOZ3nxWwfAmmKtOys5w0uzEV5kCT
34MkMv8Ogyf6dZRqeGPZcVpQOrZ4iAsdy81bSfBOIeHXMvl3q1M+PS+EeKnIgHG8
UNTptn6OAq2yXFKp46jqjJ+Ubp47ICEbOKa9qntzMbdE3MOAvnKYwSLAbt4MYfUH
DVdB8dMPGLYeeSfxjM1Z9t7gDgSUBiyC0PvP5PLDURRq69lnQlFDgFjC+AJISMxq
3ZYkOtUY4V/G7B/y2zDYsCjAcCt7ybVC8W4WW5QE7ABwLyl6gDDnpndisE87LR4=
=tlVy
-----END PGP SIGNATURE-----

installing Coreboot to T60(MX25L1605AM2C flash chip)

[Martin T]

Thanks for the replies! I modified the flashchips.c file accordingly:

root@T60:~/flashrom-0.9.7# grep -A 30 MX25L1605D flashchips.c
                .name           = "MX25L1605D/MX25L1608D",
                .bustype        = BUS_SPI,
                .manufacture_id = MACRONIX_ID,
                .model_id       = 0x14,
                .total_size     = 2048,
                .page_size      = 256,
                .feature_bits   = FEATURE_WRSR_WREN,
                .tested         = TEST_OK_PREW,
                .probe          = probe_spi_res1,
                .probe_timing   = TIMING_ZERO,
                .block_erasers  =
                {
                        {
                                .eraseblocks = { {4 * 1024, 512} },
                                .block_erase = spi_block_erase_20,
                        }, {
                                .eraseblocks = { {64 * 1024, 32} },
                                .block_erase = spi_block_erase_d8,
                        }, {
                                .eraseblocks = { {2 * 1024 * 1024, 1} },
                                .block_erase = spi_block_erase_60,
                        }, {
                                .eraseblocks = { {2 * 1024 * 1024, 1} },
                                .block_erase = spi_block_erase_c7,
                        },
                },
                .printlock      =
spi_prettyprint_status_register_default_bp3, /* bit6: Continously
Program (CP) mode */
                .unlock         = spi_disable_blockprotect,
                .write          = spi_chip_write_1,
                .read           = spi_chip_read, /* Fast read (0x0B),
dual I/O supported */
                .voltage        = {2700, 3600},
root@T60:~/flashrom-0.9.7#


..and then compiled the flashrom. As a next step, I successfully
backed up the factory BIOS, downloaded
coreboot.rom(jenkins-coreboot-1837-1421-ge1163c1) for T60/T60p
platform and saved the last 65536 bytes of coreboot.rom into
top64k.bin file:

root@T60:~/flashrom-0.9.7# dd if=coreboot.rom of=top64k.bin bs=1
skip=$(($(stat -c %s coreboot.rom) - 0x10000)) count=64k
65536+0 records in
65536+0 records out
65536 bytes (66 kB) copied, 0.246173 s, 266 kB/s
root@T60:~/flashrom-0.9.7#

Then I verified that bytes from 1966081 to 2031617 in coreboot.rom are
filled with ones and wrote the content of top64k.bin file into this
area:

root@T60:~/flashrom-0.9.7# dd if=top64k.bin of=coreboot.rom bs=1
seek=$(($(stat -c %s coreboot.rom) - 0x20000)) count=64k conv=notrunc
65536+0 records in
65536+0 records out
65536 bytes (66 kB) copied, 0.170372 s, 385 kB/s
root@T60:~/flashrom-0.9.7#


As a final step I ran the bucts utility:

root@T60:~/bucts-dc27919# ./bucts 1
bucts utility version ''
Using LPC bridge 8086:27b9 at 0000:1f.00
Current BUC.TS=0 - 128kb address range 0xFFFE0000-0xFFFFFFFF is untranslated
Updated BUC.TS=1 - 64kb address ranges at 0xFFFE0000 and 0xFFFF0000 are swapped
root@T60:~/bucts-dc27919#


Am I ready to run "flashrom -p internal -w coreboot.rom" and
power-cycle the laptop? Should I make some adjustments in my GRUB
configuration in order to ensure that laptop boots to OS? At which
stage should I install the SeaBIOS? Is it possible to restore the
factory BIOS later(for example when I sell the laptop)?


regards,
Martin

On Tue, Jul 8, 2014 at 6:12 PM, The Gluglug <[e-mail]> wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
> .model_id 0x14
>
> .probe probe_spi_res1
>
> .write spi_chip_write_1
>
> On 08/07/14 15:26, Peter Stuge wrote:
> > Martin T wrote:
> > > What is the correct definition of my flash chip in flashchips.c
> > > file?
> > >
> > > .name           = "MX25L1605D/MX25L1608D",
> >
> > This one.
> > > I wasn't able to find the exact data sheet.
> >
> > Look for MX25L1605D.
> >
> > //Peter
>
> -----BEGIN PGP SIGNATURE-----
> Version: GnuPG v1.4.11 (GNU/Linux)
> Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/
>
> iQEcBAEBAgAGBQJTvAplAAoJEP9Ft0z50c+U+gEH/jnEUD8mxiipwdHAw2hTx8TN
> dlnjEzNtRnjCg4zSiFPf7AUmzTyE89H47H00VOZ3nxWwfAmmKtOys5w0uzEV5kCT
> 34MkMv8Ogyf6dZRqeGPZcVpQOrZ4iAsdy81bSfBOIeHXMvl3q1M+PS+EeKnIgHG8
> UNTptn6OAq2yXFKp46jqjJ+Ubp47ICEbOKa9qntzMbdE3MOAvnKYwSLAbt4MYfUH
> DVdB8dMPGLYeeSfxjM1Z9t7gDgSUBiyC0PvP5PLDURRq69lnQlFDgFjC+AJISMxq
> 3ZYkOtUY4V/G7B/y2zDYsCjAcCt7ybVC8W4WW5QE7ABwLyl6gDDnpndisE87LR4=
> =tlVy
> -----END PGP SIGNATURE-----