Patch set updated for coreboot: b92ae6b Fixed broken MTRR for >4GB memory on AMD K8 fam 0fh rev <=E

[Oskar Enoksson]

Oskar Enoksson ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/238

-gerrit

commit b92ae6b8fd0dba5ac8472ce91c7a0a2b5f6e774c
Author: Oskar Enoksson 
Date:   Thu Oct 6 18:21:19 2011 +0200

Fixed broken MTRR for >4GB memory on AMD K8 fam 0fh rev <=E

AMD K8 rev F and later implements a bit SYSCFG_MSR_TOM2WB in SYSCFG_MSR to
    mark dram memory above 4GB as WB. However, AMD K8
    rev E and earlier don't implement this bit and therefore need
    MTRR spanning dram memory above 4GB. The current implementation
    of amd_setup_mtrrs never generate MTRR above 4GB.
    This caused memory > 4GB not to be recognized in e.g. Linux on those
    rev E or older platforms. This commit should fix that bug.
    I use the value of CONFIG_K8_REV_F_SUPPORT (I hope I've
    understood it's meaning correctly).

Signed-off-by: Oskar Enoksson 
    Change-Id: Ie568a52a8eb355969c86964d5afc4692e60f69c1
---
 src/cpu/amd/mtrr/amd_mtrr.c |   14 ++++++++++++--
 1 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index 623a344..6066284 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -113,7 +113,6 @@ void amd_setup_mtrrs(void)
    unsigned long i;
    msr_t msr, sys_cfg;

-
    /* Enable the access to AMD RdDram and WrDram extension bits */
    disable_cache();
    sys_cfg = rdmsr(SYSCFG_MSR);
@@ -168,7 +167,10 @@ void amd_setup_mtrrs(void)
    	msr.hi = state.tomk >> 22;
    	msr.lo = state.tomk << 10;
    	wrmsr(TOP_MEM2, msr);
-		sys_cfg.lo |= SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB;
+		sys_cfg.lo |= SYSCFG_MSR_TOM2En;
+#if CONFIG_K8_REV_F_SUPPORT == 1
+		sys_cfg.lo |= SYSCFG_MSR_TOM2WB;
+#endif
    }

/* zero the IORR's before we enable to prevent
@@ -201,5 +203,13 @@ void amd_setup_mtrrs(void)
    /* Now that I have mapped what is memory and what is not
     * Setup the mtrrs so we can cache the memory.
     */
+
+	// Rev. F K8 supports has SYSCFG_MSR_TOM2WB and dont need
+	// variable MTRR to span memory above 4GB
+	// Lower revisions K8 need variable MTRR over 4GB
+#if CONFIG_K8_REV_F_SUPPORT == 1
    x86_setup_var_mtrrs(address_bits, 0);
+#else
+	x86_setup_var_mtrrs(address_bits, 1);
+#endif
 }