My chipset is Intel Core2Due/945/ICH7.
I have 3 questions.
First question: I wonder how PCI memory read cycles can read an instruction from F000:FFF0 right after reset which is the first instruction of BIOS.
Does Coreboot writes into PCI configuration space of Device 31 of ICH7-south bridge(LPC controller)? before initializing the configuration space of Device 0 of 82945(which is memory controller)?
I mean the hardware immediately accesses BIOS chip after reset but at some point all memory read/write cycles are claimed by 945 and memory controller?
Second question: What is the code flow of Coreboot? Where does it start? and how it contines?
Third question: Inside src/mainboard/kontron/986lcd- m/acpi we have some asl files. What language they have been written in? Like superio.asl
On 7/7/10 6:42 AM, ali hagigat wrote:
My chipset is Intel Core2Due/945/ICH7.
I have 3 questions.
First question: I wonder how PCI memory read cycles can read an instruction from F000:FFF0 right after reset which is the first instruction of BIOS.
x86 CPUs are designed like that. Go read the Intel®64 and IA-32 Architectures Software Developer's Manuals: http://www.intel.com/products/processor/manuals/
Does Coreboot writes into PCI configuration space of Device 31 of ICH7-south bridge(LPC controller)? before initializing the configuration space of Device 0 of 82945(which is memory controller)?
What do you mean by "initializing the configuration space of Device 0 of 82945" ?
Generally, a lot of work happens before RAM is initialized. Go read the source code for further details.
I mean the hardware immediately accesses BIOS chip after reset but at some point all memory read/write cycles are claimed by 945 and memory controller?
No, that assumption is not true.
Second question: What is the code flow of Coreboot? Where does it start? and how it contines?
It starts with the reset vector, which is in the "bootblock". That bootblock loads further modules.
Third question: Inside src/mainboard/kontron/986lcd- m/acpi we have some asl files. What language they have been written in? Like superio.asl
The language is called ACPI Control Message Source Language (short: ASL). Go read http://www.acpi.info/DOWNLOADS/ACPIspec40a.pdf and http://acpica.org/documentation/
Stefan
Stefan,
BIOS chip is not connected to CPU directly after reset!!
It is connected to the south bridge and it is on the PCI bus.
When CPU gets ready to read from F000:FFF0, this request travels to BIOS chip.
I mean the hardware immediately accesses BIOS chip after reset but at
some point all memory read/write cycles are claimed by 945 and memory controller? No, that assumption is not true.
If not so what happens? CPU does not have address/data buses directly attached to the BIOS chip.
Thank you to answer the questions.
On Wed, Jul 7, 2010 at 2:16 PM, Stefan Reinauer < stefan.reinauer@coresystems.de> wrote:
On 7/7/10 6:42 AM, ali hagigat wrote:
My chipset is Intel Core2Due/945/ICH7.
I have 3 questions.
First question: I wonder how PCI memory read cycles can read an instruction from F000:FFF0 right after reset which is the first instruction of BIOS.
x86 CPUs are designed like that. Go read the Intel®64 and IA-32 Architectures Software Developer's Manuals: http://www.intel.com/products/processor/manuals/
Does Coreboot writes into PCI configuration space of Device 31 of ICH7-south bridge(LPC controller)? before initializing the configuration space of Device 0 of 82945(which is memory controller)?
What do you mean by "initializing the configuration space of Device 0 of 82945" ?
Generally, a lot of work happens before RAM is initialized. Go read the source code for further details.
I mean the hardware immediately accesses BIOS chip after reset but at some point all memory read/write cycles are claimed by 945 and memory controller?
No, that assumption is not true.
Second question: What is the code flow of Coreboot? Where does it start? and how it contines?
It starts with the reset vector, which is in the "bootblock". That bootblock loads further modules.
Third question: Inside src/mainboard/kontron/986lcd- m/acpi we have some asl files. What language they have been written in? Like superio.asl
The language is called ACPI Control Message Source Language (short: ASL). Go read http://www.acpi.info/DOWNLOADS/ACPIspec40a.pdf and http://acpica.org/documentation/
Stefan
-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
On 7/7/10 12:44 PM, ali hagigat wrote:
Stefan,
BIOS chip is not connected to CPU directly after reset!!
It's never connected directly, anyways, but through some kind of bridge. Usually the southbridge.
> I mean the hardware immediately accesses BIOS chip after reset but at > some point all memory read/write cycles are claimed by 945 and memory > controller? > No, that assumption is not true.If not so what happens? CPU does not have address/data buses directly attached to the BIOS chip.
The address cycles are claimed by whatever components live in any given address space.
Stefan
ali hagigat wrote:
BIOS chip is not connected to CPU directly after reset!!
See http://stuge.se/pc2010.png for a sketch of the components in a contemporary PC. The boot flash is very far away from the CPU.
When CPU gets ready to read from F000:FFF0, this request travels to BIOS chip.
Yes. It works because all components along the way are hardwired to decode accesses to the flash chip when they come out of reset.
//Peter
Peter Stuge wrote:
See http://stuge.se/pc2010.png for a sketch of the components in a contemporary PC.
Great drawing, Peter.
ali, I would like to add some detail.
The picture mentioned by Peter show an architecture that is closer to the AMD ones, in which memory controller is integrated into the CPU.
The 945 architecture has memory controller in the northbridge.
The bridge chips have logic deciding if the coming address access should be responsed by it, or should be routed to somewhere else. As in 945, when an address comes from CPU, the northbridge decides whether the address access means a memory access, a configuration to the chip itself, or to other devices that connects to it. In the case of first instruction address, the northbridge will pass that request to southbridge.
Read the chipset manual for more information. Some effort is is needed to extract what you want from the text.
By the way, since my knowledge is still of the single core age and I know little about architectures other than Intel x86, my explanation may not be accurate. I think someone in the list will correct me if that was the case.
yn
Ok, thank you all for the replies, links and diagrams. But there are still some ambiguities in memory read/write after reset which is done by BIOS chip and then the memory controller !!
Immediately after reset all memory read/write cycles are claimed by BIOS chip ultimately. The first question is that: Is memory controller enabled after reset before writing to its configuration space? If it is enabled, how it does not claim for memory addresses after reset?
If it is not enabled and we enable the memory controller by writing to its configuration registers how we introduce the memory address range used by BIOS chip here? Because the memory controller should not claim the memory address range of the BIOS chip. I had a general look at the configuration registers of the memory controller, there is no register or registers to set this range of address!! Besides there is no enable bit or something similar!!
These questions are repeated for BIOS chip and the PCI device connected to it. Do we have to write to their configuration registers to specify a specific range of address? Otherwise both memory controller and the PCI device connected to the BIOS chip will claim for that address!! Because they are being situated at the same PCI bus.
On 7/7/10, FENG Yu Ning fengyuning1984@gmail.com wrote:
Peter Stuge wrote:
See http://stuge.se/pc2010.png for a sketch of the components in a contemporary PC.
Great drawing, Peter.
ali, I would like to add some detail.
The picture mentioned by Peter show an architecture that is closer to the AMD ones, in which memory controller is integrated into the CPU.
The 945 architecture has memory controller in the northbridge.
The bridge chips have logic deciding if the coming address access should be responsed by it, or should be routed to somewhere else. As in 945, when an address comes from CPU, the northbridge decides whether the address access means a memory access, a configuration to the chip itself, or to other devices that connects to it. In the case of first instruction address, the northbridge will pass that request to southbridge.
Read the chipset manual for more information. Some effort is is needed to extract what you want from the text.
By the way, since my knowledge is still of the single core age and I know little about architectures other than Intel x86, my explanation may not be accurate. I think someone in the list will correct me if that was the case.
yn
-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
ali hagigat hagigatali@gmail.com writes:
Ok, thank you all for the replies, links and diagrams. But there are still some ambiguities in memory read/write after reset which is done by BIOS chip and then the memory controller !!
Immediately after reset all memory read/write cycles are claimed by BIOS chip ultimately. The first question is that: Is memory controller enabled after reset before writing to its configuration space? If it is enabled, how it does not claim for memory addresses after reset?
If it is not enabled and we enable the memory controller by writing to its configuration registers how we introduce the memory address range used by BIOS chip here? Because the memory controller should not claim the memory address range of the BIOS chip. I had a general look at the configuration registers of the memory controller, there is no register or registers to set this range of address!! Besides there is no enable bit or something similar!!
These questions are repeated for BIOS chip and the PCI device connected to it. Do we have to write to their configuration registers to specify a specific range of address? Otherwise both memory controller and the PCI device connected to the BIOS chip will claim for that address!! Because they are being situated at the same PCI bus.
If you really want to understand this I recommend picking a board that has a good coreboot port and getting the manuals of all of the parts and following the code through.
Making things work in coreboot tends to be like attaching the mains to the breaker box, turn the power on at the breaker, and the flipping the light switch all to turn on a little light. It is very rarely as simple as going to the destination devices and looking at it.
Eric
-
ali hagigat -
ebiederm＠xmission.com -
FENG Yu Ning -
Peter Stuge -
Stefan Reinauer