What is the BIOS RAM in AMD SB7XX used for?
Is it to buffer the BIOS contents from SPI flash chip prior to execution of the very first instruction? I recall that it's impossible to execute code directly in an SPI chip.
or am I missing something?
On Tue, Oct 27, 2009 at 6:06 AM, Darmawan Salihun < darmawan.salihun@gmail.com> wrote:
What is the BIOS RAM in AMD SB7XX used for?
Looks like scratchpad memory to me. From the public dochttp://developer.amd.com/assets/43366_sb7xx_bdg_pub_1.00.pdf :
3.3 BIOS RAM The SB700 has 256 bytes of BIOS RAM. Data in this RAM is preserved until RSMRST# or S5 is asserted, or until power is lost. This RAM is accessed using index and data registers at CD4h/CD5h.
Might it be enough to act as a very, very small cache-as-RAM substitute until CAR can be set up?
On Tue, Oct 27, 2009 at 6:06 AM, Darmawan Salihun < darmawan.salihun@gmail.com> wrote:
Is it to buffer the BIOS contents from SPI flash chip prior to execution of the very first instruction? I recall that it's impossible to execute code directly in an SPI chip.
That's correct, afaik.
On Tue, Oct 27, 2009 at 4:51 PM, David Hendricks dhendrix@google.com wrote:
On Tue, Oct 27, 2009 at 6:06 AM, Darmawan Salihun darmawan.salihun@gmail.com wrote:
What is the BIOS RAM in AMD SB7XX used for?
Looks like scratchpad memory to me. From the public doc:
3.3 BIOS RAM The SB700 has 256 bytes of BIOS RAM. Data in this RAM is preserved until RSMRST# or S5 is asserted, or until power is lost. This RAM is accessed using index and data registers at CD4h/CD5h.
Might it be enough to act as a very, very small cache-as-RAM substitute until CAR can be set up?
On Tue, Oct 27, 2009 at 6:06 AM, Darmawan Salihun darmawan.salihun@gmail.com wrote:
Is it to buffer the BIOS contents from SPI flash chip prior to execution of the very first instruction? I recall that it's impossible to execute code directly in an SPI chip.
That's correct, afaik.
David Hendricks (dhendrix) Systems Software Engineer, Google Inc.
-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Hello! This is well and good David. Thank you! And as it happens Google Mail goofed on its spam scanning, and even mistook this one for a phishing scheme. According to other folk at Google they themselves obviously use the Google Mail service internally, so I do not see why this would have happened.
----- Gregg C Levine gregg.drwho8@gmail.com "This signature was once found posting rude messages in English in the Moscow subway."
On Tue, Oct 27, 2009 at 2:04 PM, Gregg Levine gregg.drwho8@gmail.comwrote:
On Tue, Oct 27, 2009 at 4:51 PM, David Hendricks dhendrix@google.com wrote:
On Tue, Oct 27, 2009 at 6:06 AM, Darmawan Salihun darmawan.salihun@gmail.com wrote:
What is the BIOS RAM in AMD SB7XX used for?
Looks like scratchpad memory to me. From the public doc:
3.3 BIOS RAM The SB700 has 256 bytes of BIOS RAM. Data in this RAM is preserved until RSMRST# or S5 is asserted, or until power is lost. This RAM is accessed using index and data registers at CD4h/CD5h.
Might it be enough to act as a very, very small cache-as-RAM substitute until CAR can be set up?
On Tue, Oct 27, 2009 at 6:06 AM, Darmawan Salihun darmawan.salihun@gmail.com wrote:
Is it to buffer the BIOS contents from SPI flash chip prior to execution of the very first instruction? I recall that it's impossible to execute code directly in an SPI chip.
That's correct, afaik.
David Hendricks (dhendrix) Systems Software Engineer, Google Inc.
-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Hello! This is well and good David. Thank you! And as it happens Google Mail goofed on its spam scanning, and even mistook this one for a phishing scheme. According to other folk at Google they themselves obviously use the Google Mail service internally, so I do not see why this would have happened.
Weird! Maybe it's because of the external website link in my post. Thanks for catching that, Gregg.
For reference, the public doc I referenced is available from AMD's main developer manual site: http://developer.amd.com/DOCUMENTATION/GUIDES/Pages/default.aspx
The doc I referred to is here: http://developer.amd.com/assets/43366_sb7xx_bdg_pub_1.00.pdf . It's pretty vague, though. The register reference guide ( http://developer.amd.com/assets/43009_sb7xx_rrg_pub_1.00.pdf ) has some additional information on how to enable and utilize the BIOS RAM area for those curious.
On 27.10.2009 21:51, David Hendricks wrote:
On Tue, Oct 27, 2009 at 6:06 AM, Darmawan Salihun wrote
What is the BIOS RAM in AMD SB7XX used for?
Looks like scratchpad memory to me. From the public dochttp://developer.amd.com/assets/43366_sb7xx_bdg_pub_1.00.pdf :
3.3 BIOS RAM The SB700 has 256 bytes of BIOS RAM. Data in this RAM is preserved until RSMRST# or S5 is asserted, or until power is lost. This RAM is accessed using index and data registers at CD4h/CD5h.
Might it be enough to act as a very, very small cache-as-RAM substitute until CAR can be set up?
Given that it is not memory mapped and needs indexed access, it is unusable for cache-as-RAM (unless you just want to outsource some storage manually). Since CAR works fine on all AMD processors, the point is moot anyway. It would serve nicely as persistent storage for S3, though.
Regards, Carl-Daniel
On 27.10.2009 14:06, Darmawan Salihun wrote:
What is the BIOS RAM in AMD SB7XX used for?
Is it to buffer the BIOS contents from SPI flash chip prior to execution of the very first instruction?
No.
I recall that it's impossible to execute code directly in an SPI chip.
Yes, but the chipset takes care of the SPI command interface and presents the contents of the SPI chip nicely memory mapped to the CPU, so the CPU can execute the ROM contents directly.
Regards, Carl-Daniel
On 10/28/09, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
On 27.10.2009 14:06, Darmawan Salihun wrote:
What is the BIOS RAM in AMD SB7XX used for?
Is it to buffer the BIOS contents from SPI flash chip prior to execution of the very first instruction?
No.
I recall that it's impossible to execute code directly in an SPI chip.
Yes, but the chipset takes care of the SPI command interface and presents the contents of the SPI chip nicely memory mapped to the CPU, so the CPU can execute the ROM contents directly.
I see. So, there must be some sort of independent microcontroller/microprocessor in the southbridge that "fetches" the contents of the SPI chip and "present" it in a "memory-mapped way" to the CPU. Probably this is how the BIOS RAM is used by the internal microcontroller/microprocessor in the southbridge.
I suspect this because an ex-intel engineer that I spoke to, told me that back then he was using ARM7TDMI to do the job of "presenting the BIOS contents in a memory-mapped way" to the CPU. These days, the function must've been integrated in the southbridge as you said. I suspect AMD do the same.
Regards,
Darmawan Salihun -------------------------------------------------------------------- -= Human knowledge belongs to the world =-
on 28/10/2009 06:55 Darmawan Salihun said the following:
On 10/28/09, Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net wrote:
On 27.10.2009 14:06, Darmawan Salihun wrote:
What is the BIOS RAM in AMD SB7XX used for?
Is it to buffer the BIOS contents from SPI flash chip prior to execution of the very first instruction?
No.
I recall that it's impossible to execute code directly in an SPI chip.
Yes, but the chipset takes care of the SPI command interface and presents the contents of the SPI chip nicely memory mapped to the CPU, so the CPU can execute the ROM contents directly.
I see. So, there must be some sort of independent microcontroller/microprocessor in the southbridge that "fetches" the contents of the SPI chip and "present" it in a "memory-mapped way" to the CPU. Probably this is how the BIOS RAM is used by the internal microcontroller/microprocessor in the southbridge.
No, I think. "BIOS RAM" is some sort of scratch-pad memory for arbitrary use by software.
I suspect this because an ex-intel engineer that I spoke to, told me that back then he was using ARM7TDMI to do the job of "presenting the BIOS contents in a memory-mapped way" to the CPU. These days, the function must've been integrated in the southbridge as you said. I suspect AMD do the same.
Yes, most probably. But BIOS RAM has nothing to do with this. Chipset directs memory access for certain range(s) to embedded SPI controller which in turn translates them into appropriate SPI commands.
Darmawan Salihun wrote:
What is the BIOS RAM in AMD SB7XX used for?
It will for example be used to store RAM configuration parameters when the system is suspended.
Is it to buffer the BIOS contents from SPI flash chip prior to execution of the very first instruction?
No.
I recall that it's impossible to execute code directly in an SPI chip.
It is not only possible but quickly becoming the most common flash chip interface.
I see. So, there must be some sort of independent microcontroller/microprocessor in the southbridge that "fetches" the contents of the SPI chip and "present" it in a "memory-mapped way" to the CPU.
A microcontroller is too slow. An SPI master is just a simple state machine. SPI is a very simple protocol. Typically you will find that southbridge or worst case superio has an SPI master which subtractively decodes the BIOS memory range onto SPI. Accesses come from the CPU to chipset usually then to LPC and finally to SPI. All these bridges are transparent to the CPU.
Andriy Gapon wrote:
No, I think. "BIOS RAM" is some sort of scratch-pad memory for arbitrary use by software.
Correct.
//Peter
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Andriy Gapon -
Carl-Daniel Hailfinger -
Darmawan Salihun -
David Hendricks -
David Hendricks -
Gregg Levine -
Peter Stuge