Patch set updated for coreboot: b02c5e6 Persimmon DSDT: Add secondary bus range to PCI0

[Mike Loptien]

Mike Loptien ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2592

-gerrit

commit b02c5e684fc5ec0aeafb0b23a3e0ffa3c1689d6f
Author: Mike Loptien 
Date:   Tue Mar 5 14:21:28 2013 -0700

Persimmon DSDT: Add secondary bus range to PCI0

Adding the 'WordBusNumber' macro to the PCI0
    CRES ResourceTemplate in the Persimmon DSDT.
    This sets up the bus number for the PCI0 device
    and the secondary bus number in the CRS method.
    This change came in response to a 'dmesg' error
    which states:
    '[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS'

By adding the 'WordBusNumber' macro, ACPI can set
    up a valid range for the PCIe downstream busses,
    thereby relieving the Linux kernel from "guessing"
    the valid range based off _BBN or assuming [0-0xFF].
    The Linux kernel code that checks this bus range is
    in `drivers/acpi/pci_root.c`.  PCI busses can have
    up to 256 secondary busses connected to them via
    a PCI-PCI bridge.  However, these busses do not
    have to be sequentially numbered, so leaving out a
    section of the range (eg. allowing [0-0x7F]) will
    unnecessarily restrict the downstream busses.

This change will apply to other AMD mainboards and
    will be in a different commit.

Change-Id: I44f22bc03a0dcbcd2594d4291508826cc2146860
    Signed-off-by: Mike Loptien 
---
 src/mainboard/amd/persimmon/dsdt.asl | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl
index 582ab7f..148d7b0 100644
--- a/src/mainboard/amd/persimmon/dsdt.asl
+++ b/src/mainboard/amd/persimmon/dsdt.asl
@@ -1477,6 +1477,22 @@ DefinitionBlock (
    		} /* end Ac97modem */

Name(CRES, ResourceTemplate() {
+				/* Set the Bus number and Secondary Bus number for the PCI0 device
+				 * The Secondary bus range for PCI0 lets the system
+				 * know what bus values are allowed on the downstream
+				 * side of this PCI bus if there is a PCI-PCI bridge.
+				 * PCI busses can have 256 secondary busses which
+				 * range from [0-0xFF] but they do not need to be
+				 * sequential.
+				 */
+				WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+					0x0000,		/* address granularity */
+					0x0000,		/* range minimum */
+					0x00FF,		/* range maximum */
+					0x0000,		/* translation */
+					0x0100,		/* length */
+					,, PSB0)	/* ResourceSourceIndex, ResourceSource, DescriptorName */
+
    			IO(Decode16, 0x0CF8, 0x0CF8, 1,	8)

WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,