[LinuxBIOS] starting ACPI implementation for m57sli

Hi everybody! Following http://linuxbios.org/ACPI_in_LinuxBIOS I tried to implement some basic ACPI functionality for the ga-m57sli. It compiles now, but linux doesn't boot anymore, I guess there is some irq routing wrong (I took all from the a8v-e_se; thanks to Rudolf Marek). I'm an absolute newcomer to the field, so please do not expect to much from the patch. Perhaps someone else can be motivated, and/or use it as starting point for a thorough implementation. (Or, of course, give a hint what's going wrong). Thanks, Andi

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, The guide is not finished yet :) But please try booting with: pci=routeirq Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.6 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFHXxcn3J9wPJqZRNURAqPXAKDTpDQXSr7B5Hh19ZEToaXcUNImbwCgjhta jURoyajcCaPSDskAyxNpeRs= =FyG6 -----END PGP SIGNATURE-----

Hi Andreas, thanks, this is pretty cool. But we can not check in if it is not signed off: http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure Stefan * Andreas B. Mundt <andi.mundt@web.de> [071210 19:26]:
Hi everybody!
Following http://linuxbios.org/ACPI_in_LinuxBIOS I tried to implement some basic ACPI functionality for the ga-m57sli.
It compiles now, but linux doesn't boot anymore, I guess there is some irq routing wrong (I took all from the a8v-e_se; thanks to Rudolf Marek).
I'm an absolute newcomer to the field, so please do not expect to much from the patch. Perhaps someone else can be motivated, and/or use it as starting point for a thorough implementation. (Or, of course, give a hint what's going wrong).
Thanks,
Andi
Index: src/mainboard/gigabyte/m57sli/fadt.c =================================================================== --- src/mainboard/gigabyte/m57sli/fadt.c (revision 0) +++ src/mainboard/gigabyte/m57sli/fadt.c (revision 0) @@ -0,0 +1,154 @@ +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + * (C) Copyright 2004 Nick Barker <nick.barker9@btinternet.com> + * (C) Copyright 2007 Rudolf Marek <r.marek@assembler.cz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <string.h> +#include <arch/acpi.h> +//#include <../../../southbridge/nvidia/mcp55/mcp55.h> + +#define MCP55_ACPI_IO_BASE 0x1000 + + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 244; + header->revision = 1; + memcpy(header->oem_id, "LXBIOS", 6); + memcpy(header->oem_table_id, "LXBACPI ", 8); + memcpy(header->asl_compiler_id, "IASL", 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = facs; + fadt->dsdt = dsdt; + fadt->preferred_pm_profile = 0; + fadt->sci_int = 9; + fadt->smi_cmd = 0; + fadt->acpi_enable = 0; + fadt->acpi_disable = 0; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0x0; + + fadt->pm1a_evt_blk = MCP55_ACPI_IO_BASE; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = MCP55_ACPI_IO_BASE + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = 0x0; + fadt->pm_tmr_blk = MCP55_ACPI_IO_BASE + 0x8; + fadt->gpe0_blk = MCP55_ACPI_IO_BASE + 0x20; + fadt->gpe1_blk = 0x0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 0; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 4; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 90; + fadt->p_lvl3_lat = 900; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 0; + fadt->duty_width = 1; //?? + fadt->day_alrm = 0x7d; + fadt->mon_alrm = 0x7e; + fadt->century = 0x32; + /* fixme 5 - 10 */ + fadt->iapc_boot_arch = 0x1; + /* fixme */ + fadt->flags = 0x4a5; + + fadt->reset_reg.space_id = 0; + fadt->reset_reg.bit_width = 0; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0x0; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 0; + fadt->x_firmware_ctl_l = facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 4; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = MCP55_ACPI_IO_BASE; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 2; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = MCP55_ACPI_IO_BASE + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = 0x0; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 4; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = MCP55_ACPI_IO_BASE + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 0; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = MCP55_ACPI_IO_BASE + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); +} Index: src/mainboard/gigabyte/m57sli/Config.lb =================================================================== --- src/mainboard/gigabyte/m57sli/Config.lb (revision 3003) +++ src/mainboard/gigabyte/m57sli/Config.lb (working copy) @@ -77,6 +77,17 @@ #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o
+if HAVE_ACPI_TABLES + object acpi_tables.o + object fadt.o + makerule dsdt.c + depends "$(MAINBOARD)/dsdt.asl" + action "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.asl" + action "mv dsdt.hex dsdt.c" + end + object ./dsdt.o +end + if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o Index: src/mainboard/gigabyte/m57sli/Options.lb =================================================================== --- src/mainboard/gigabyte/m57sli/Options.lb (revision 3003) +++ src/mainboard/gigabyte/m57sli/Options.lb (working copy) @@ -163,7 +163,7 @@ default HAVE_MP_TABLE=1
## ACPI tables will be included -default HAVE_ACPI_TABLES=0 +default HAVE_ACPI_TABLES=1
## ## Build code to export a CMOS option table @@ -192,6 +192,9 @@ default APIC_ID_OFFSET=0x10 default LIFT_BSP_APIC_ID=1
+#acpi +default HAVE_ACPI_TABLES=1 + #CHIP_NAME ? default CONFIG_CHIP_NAME=1
Index: src/mainboard/gigabyte/m57sli/acpi_tables.c =================================================================== --- src/mainboard/gigabyte/m57sli/acpi_tables.c (revision 0) +++ src/mainboard/gigabyte/m57sli/acpi_tables.c (revision 0) @@ -0,0 +1,172 @@ +/* + * This file is part of the LinuxBIOS project. + * written by Stefan Reinauer <stepan@openbios.org> + * ACPI FADT, FACS, and DSDT table support added by + * + * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org> + * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com> + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci_ids.h> + +#include <../../../southbridge/nvidia/mcp55/mcp55.h> + +#define MCP55_APIC_BASE 0xfecc0000 +#define MCP55_APIC_ID 0x3 + +extern unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + struct resource *res; + dev = dev_find_device(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP55_PCI, 0); + if (!dev) + return current; + + /* res = find_resource(dev, K8T890_MMCONFIG_MBAR); + if (res) { + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) + current, res->base, 0x0, 0x0, 0xff); + }*/ + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + //unsigned int gsi_base = 0x18; + unsigned int gsi_base = 0x10; + + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB IOAPIC */ + current += + acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, MCP55_APIC_ID, + MCP55_APIC_BASE, 0); + + /* Write NB IOAPIC + current += + acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, K8T890_APIC_ID, + K8T890_APIC_BASE, gsi_base); + /* IRQ9 ACPI active low */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + + /* IRQ0 -> APIC IRQ2 */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0x0); + + /* create all subtables for processors */ + current = + acpi_create_madt_lapic_nmis(current, + MP_IRQ_TRIGGER_EDGE | + MP_IRQ_POLARITY_HIGH, 1); + + return current; +} + + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_mcfg_t *mcfg; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16byte */ + start = (start + 0x0f) & -0x10; + current = start; + + printk_info("ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt); + acpi_write_rsdt(rsdt); + + /* + * We explicitly add these tables later on: + */ + printk_debug("ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + dsdt = (acpi_header_t *) current; + current += ((acpi_header_t *) AmlCode)->length; + memcpy((void *) dsdt, (void *) AmlCode, + ((acpi_header_t *) AmlCode)->length); + dsdt->checksum = 0; // don't trust intel iasl compiler to get this right + dsdt->checksum = acpi_checksum(dsdt, dsdt->length); + printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, + dsdt->length); + printk_debug("ACPI: * FADT\n"); + + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdt, fadt); + + printk_debug("ACPI: * HPET\n"); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdt, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk_debug("ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdt, madt); + + printk_debug("ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + acpi_add_table(rsdt, mcfg); + + /* SRAT */ + printk_debug("ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdt, srat); + + printk_info("ACPI: done.\n"); + return current; +} Index: src/mainboard/gigabyte/m57sli/dsdt.asl =================================================================== --- src/mainboard/gigabyte/m57sli/dsdt.asl (revision 0) +++ src/mainboard/gigabyte/m57sli/dsdt.asl (revision 0) @@ -0,0 +1,249 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Minimalist ACPI DSDT table for EPIA-M / MII + * (C) Copyright 2004 Nick Barker <Nick.Barker9@btinternet.com> + * + * (C) Copyright 2007 Rudolf Marek <r.marek@assembler.cz> + * + * ISA portions taken from QEMU acpi-dsdt.dsl + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) +{ + + + + + /* + * Define the main processor + */ + Scope (\_PR) + { + Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {} + Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {} + } + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * any others would involve declaring the wake up methods + */ + Name (\_S0, Package () {0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () {0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* top PCI device */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + /* PCI Routing Table */ + //aaa + Name (_PRT, Package () { + Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x14 } + }) + +// Name (_PRT, Package () { +// Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, //slot 0xB +// Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, +// Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, +// Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 }, +// Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, //Slot 0xC +// Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 }, +// Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 }, +// Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 }, +// Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, //Slot 0xD +// Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, +// Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, +// Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, +// Package (0x04) { 0x000F0000, 0x01, 0x00, 0x14 }, //0xf SATA IRQ 20 +// Package (0x04) { 0x000F0001, 0x00, 0x00, 0x14 }, //0xf NAtive IDE IRQ 20 +// Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, //USB routing +// Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, +// Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, +// Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, +// Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, //AC97 MC97 +// Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, //PCIE16 bridge IRQ27 +// Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, +// Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, +// Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, +// Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, //PCIE bridge IRQ31 +// Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, //IRQ36 +// Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, //IRQ39 +// Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } //IRQ43 +// }) +// + + Device (PEGG) + { + Name (_ADR, 0x00020000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, //PCIE IRQ24-IRQ27 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, + }) + } //end of PCIEG + + Device (PEX0) + { + Name (_ADR, 0x00030000) + Name (_UID, 0x00) + Name (_BBN, 0x03) + + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, //PCIE IRQ28-IRQ31 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, + }) + } //end of PEX0 + + Device (PEX1) + { + Name (_ADR, 0x00030001) + Name (_UID, 0x00) + Name (_BBN, 0x04) + + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, //PCIE IRQ32-IRQ35 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, + }) + } //end f PEX1 + + Device (PEX2) + { + Name (_ADR, 0x00030002) + Name (_UID, 0x00) + Name (_BBN, 0x05) + + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, //PCIE IRQ36-IRQ39 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, + }) + } //end f PEX2 + + Device (PEX3) + { + Name (_ADR, 0x00030003) + Name (_UID, 0x00) + Name (_BBN, 0x06) + + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, //PCIE IRQ40-IRQ43 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, + }) + } //end f PEX3 + + Device (ISA) { + Name (_ADR, 0x00110000) + + /* Keyboard seems to be important for WinXP install */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () + { + IO (Decode16, + 0x0060, // Address Range Minimum + 0x0060, // Address Range Maximum + 0x01, // Address Alignment + 0x01, // Address Length + ) + IO (Decode16, + 0x0064, // Address Range Minimum + 0x0064, // Address Range Maximum + 0x01, // Address Alignment + 0x01, // Address Length + ) + IRQNoFlags () + {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () + { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* PS/2 floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } //FD END + + } //ISA END + + } // End of PCI0 + + + } // End of _SB + +} // End of Definition Block +
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On Wed, Feb 20, 2008 at 05:43:58PM +0100, Stefan Reinauer wrote:
Following http://linuxbios.org/ACPI_in_LinuxBIOS I tried to implement some basic ACPI functionality for the ga-m57sli.
It compiles now, but linux doesn't boot anymore,
thanks, this is pretty cool. But we can not check in if it is not signed off:
I will NAK until Linux actually does boot also with the patch. //Peter

On Thu, Feb 21, 2008 at 02:32:43AM +0100, Peter Stuge wrote:
On Wed, Feb 20, 2008 at 05:43:58PM +0100, Stefan Reinauer wrote:
Following http://linuxbios.org/ACPI_in_LinuxBIOS I tried to implement some basic ACPI functionality for the ga-m57sli.
It compiles now, but linux doesn't boot anymore,
thanks, this is pretty cool. But we can not check in if it is not signed off:
I will NAK until Linux actually does boot also with the patch.
Seconded. Thanks, Ward. -- Ward Vandewege <ward@fsf.org> Free Software Foundation - Senior System Administrator

On Thursday 21 February 2008, Ward Vandewege wrote:
On Thu, Feb 21, 2008 at 02:32:43AM +0100, Peter Stuge wrote:
On Wed, Feb 20, 2008 at 05:43:58PM +0100, Stefan Reinauer wrote:
Following http://linuxbios.org/ACPI_in_LinuxBIOS I tried to implement some basic ACPI functionality for the ga-m57sli.
It compiles now, but linux doesn't boot anymore,
thanks, this is pretty cool. But we can not check in if it is not signed off:
I will NAK until Linux actually does boot also with the patch.
Seconded.
Could this be merged with mptable.c, and ideally also made consistent with the configurable interrupts? (see the "CK804 interrupt steering - SATA fix" thread) Torsten

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1
Could this be merged with mptable.c, and ideally also made consistent with the configurable interrupts? (see the "CK804 interrupt steering - SATA fix" thread)
You can create the ACPI AML code that will generate the table on the fly with regards of the interrupt steering setup in chipset registers. Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.6 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFHwdKe3J9wPJqZRNURAsyEAKCrUQZ7D6UsKELOZsQRoIGfqJumkQCfYFvj I9Um4F6jLnXUrokLpFz2L7w= =us88 -----END PGP SIGNATURE-----

Hi Stefan, the patch is meant as starting point for developers with better background in the field, not for checking it in as it is currently. Unfortunately I do not have the time to work on it and learn all the skills needed to go on. I'll have to wait for the experts. :-) Thanks, Andi On Wed, Feb 20, 2008 at 05:43:58PM +0100, Stefan Reinauer wrote:
Hi Andreas,
thanks, this is pretty cool. But we can not check in if it is not signed off: http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure
Stefan
* Andreas B. Mundt <andi.mundt@web.de> [071210 19:26]:
Hi everybody!
Following http://linuxbios.org/ACPI_in_LinuxBIOS I tried to implement some basic ACPI functionality for the ga-m57sli.
It compiles now, but linux doesn't boot anymore, I guess there is some irq routing wrong (I took all from the a8v-e_se; thanks to Rudolf Marek).
I'm an absolute newcomer to the field, so please do not expect to much from the patch. Perhaps someone else can be motivated, and/or use it as starting point for a thorough implementation. (Or, of course, give a hint what's going wrong).
Thanks,
Andi
Index: src/mainboard/gigabyte/m57sli/fadt.c =================================================================== --- src/mainboard/gigabyte/m57sli/fadt.c (revision 0) +++ src/mainboard/gigabyte/m57sli/fadt.c (revision 0) @@ -0,0 +1,154 @@ +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + * (C) Copyright 2004 Nick Barker <nick.barker9@btinternet.com> + * (C) Copyright 2007 Rudolf Marek <r.marek@assembler.cz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <string.h> +#include <arch/acpi.h> +//#include <../../../southbridge/nvidia/mcp55/mcp55.h> + +#define MCP55_ACPI_IO_BASE 0x1000 + + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 244; + header->revision = 1; + memcpy(header->oem_id, "LXBIOS", 6); + memcpy(header->oem_table_id, "LXBACPI ", 8); + memcpy(header->asl_compiler_id, "IASL", 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = facs; + fadt->dsdt = dsdt; + fadt->preferred_pm_profile = 0; + fadt->sci_int = 9; + fadt->smi_cmd = 0; + fadt->acpi_enable = 0; + fadt->acpi_disable = 0; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0x0; + + fadt->pm1a_evt_blk = MCP55_ACPI_IO_BASE; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = MCP55_ACPI_IO_BASE + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = 0x0; + fadt->pm_tmr_blk = MCP55_ACPI_IO_BASE + 0x8; + fadt->gpe0_blk = MCP55_ACPI_IO_BASE + 0x20; + fadt->gpe1_blk = 0x0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 0; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 4; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 90; + fadt->p_lvl3_lat = 900; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 0; + fadt->duty_width = 1; //?? + fadt->day_alrm = 0x7d; + fadt->mon_alrm = 0x7e; + fadt->century = 0x32; + /* fixme 5 - 10 */ + fadt->iapc_boot_arch = 0x1; + /* fixme */ + fadt->flags = 0x4a5; + + fadt->reset_reg.space_id = 0; + fadt->reset_reg.bit_width = 0; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0x0; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 0; + fadt->x_firmware_ctl_l = facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 4; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = MCP55_ACPI_IO_BASE; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 2; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = MCP55_ACPI_IO_BASE + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = 0x0; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 4; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = MCP55_ACPI_IO_BASE + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 0; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = MCP55_ACPI_IO_BASE + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); +} Index: src/mainboard/gigabyte/m57sli/Config.lb =================================================================== --- src/mainboard/gigabyte/m57sli/Config.lb (revision 3003) +++ src/mainboard/gigabyte/m57sli/Config.lb (working copy) @@ -77,6 +77,17 @@ #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o
+if HAVE_ACPI_TABLES + object acpi_tables.o + object fadt.o + makerule dsdt.c + depends "$(MAINBOARD)/dsdt.asl" + action "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.asl" + action "mv dsdt.hex dsdt.c" + end + object ./dsdt.o +end + if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o Index: src/mainboard/gigabyte/m57sli/Options.lb =================================================================== --- src/mainboard/gigabyte/m57sli/Options.lb (revision 3003) +++ src/mainboard/gigabyte/m57sli/Options.lb (working copy) @@ -163,7 +163,7 @@ default HAVE_MP_TABLE=1
## ACPI tables will be included -default HAVE_ACPI_TABLES=0 +default HAVE_ACPI_TABLES=1
## ## Build code to export a CMOS option table @@ -192,6 +192,9 @@ default APIC_ID_OFFSET=0x10 default LIFT_BSP_APIC_ID=1
+#acpi +default HAVE_ACPI_TABLES=1 + #CHIP_NAME ? default CONFIG_CHIP_NAME=1
Index: src/mainboard/gigabyte/m57sli/acpi_tables.c =================================================================== --- src/mainboard/gigabyte/m57sli/acpi_tables.c (revision 0) +++ src/mainboard/gigabyte/m57sli/acpi_tables.c (revision 0) @@ -0,0 +1,172 @@ +/* + * This file is part of the LinuxBIOS project. + * written by Stefan Reinauer <stepan@openbios.org> + * ACPI FADT, FACS, and DSDT table support added by + * + * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org> + * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com> + * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci_ids.h> + +#include <../../../southbridge/nvidia/mcp55/mcp55.h> + +#define MCP55_APIC_BASE 0xfecc0000 +#define MCP55_APIC_ID 0x3 + +extern unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + struct resource *res; + dev = dev_find_device(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP55_PCI, 0); + if (!dev) + return current; + + /* res = find_resource(dev, K8T890_MMCONFIG_MBAR); + if (res) { + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) + current, res->base, 0x0, 0x0, 0xff); + }*/ + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + //unsigned int gsi_base = 0x18; + unsigned int gsi_base = 0x10; + + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB IOAPIC */ + current += + acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, MCP55_APIC_ID, + MCP55_APIC_BASE, 0); + + /* Write NB IOAPIC + current += + acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, K8T890_APIC_ID, + K8T890_APIC_BASE, gsi_base); + /* IRQ9 ACPI active low */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + + /* IRQ0 -> APIC IRQ2 */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0x0); + + /* create all subtables for processors */ + current = + acpi_create_madt_lapic_nmis(current, + MP_IRQ_TRIGGER_EDGE | + MP_IRQ_POLARITY_HIGH, 1); + + return current; +} + + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_mcfg_t *mcfg; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16byte */ + start = (start + 0x0f) & -0x10; + current = start; + + printk_info("ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt); + acpi_write_rsdt(rsdt); + + /* + * We explicitly add these tables later on: + */ + printk_debug("ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + dsdt = (acpi_header_t *) current; + current += ((acpi_header_t *) AmlCode)->length; + memcpy((void *) dsdt, (void *) AmlCode, + ((acpi_header_t *) AmlCode)->length); + dsdt->checksum = 0; // don't trust intel iasl compiler to get this right + dsdt->checksum = acpi_checksum(dsdt, dsdt->length); + printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, + dsdt->length); + printk_debug("ACPI: * FADT\n"); + + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdt, fadt); + + printk_debug("ACPI: * HPET\n"); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdt, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk_debug("ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdt, madt); + + printk_debug("ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + acpi_add_table(rsdt, mcfg); + + /* SRAT */ + printk_debug("ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdt, srat); + + printk_info("ACPI: done.\n"); + return current; +} Index: src/mainboard/gigabyte/m57sli/dsdt.asl =================================================================== --- src/mainboard/gigabyte/m57sli/dsdt.asl (revision 0) +++ src/mainboard/gigabyte/m57sli/dsdt.asl (revision 0) @@ -0,0 +1,249 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Minimalist ACPI DSDT table for EPIA-M / MII + * (C) Copyright 2004 Nick Barker <Nick.Barker9@btinternet.com> + * + * (C) Copyright 2007 Rudolf Marek <r.marek@assembler.cz> + * + * ISA portions taken from QEMU acpi-dsdt.dsl + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) +{ + + + + + /* + * Define the main processor + */ + Scope (\_PR) + { + Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {} + Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {} + } + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * any others would involve declaring the wake up methods + */ + Name (\_S0, Package () {0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () {0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* top PCI device */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + /* PCI Routing Table */ + //aaa + Name (_PRT, Package () { + Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x14 } + }) + +// Name (_PRT, Package () { +// Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, //slot 0xB +// Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, +// Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, +// Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 }, +// Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, //Slot 0xC +// Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 }, +// Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 }, +// Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 }, +// Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, //Slot 0xD +// Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, +// Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, +// Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, +// Package (0x04) { 0x000F0000, 0x01, 0x00, 0x14 }, //0xf SATA IRQ 20 +// Package (0x04) { 0x000F0001, 0x00, 0x00, 0x14 }, //0xf NAtive IDE IRQ 20 +// Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, //USB routing +// Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, +// Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, +// Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, +// Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, //AC97 MC97 +// Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, //PCIE16 bridge IRQ27 +// Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, +// Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, +// Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, +// Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, //PCIE bridge IRQ31 +// Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, //IRQ36 +// Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, //IRQ39 +// Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } //IRQ43 +// }) +// + + Device (PEGG) + { + Name (_ADR, 0x00020000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, //PCIE IRQ24-IRQ27 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, + }) + } //end of PCIEG + + Device (PEX0) + { + Name (_ADR, 0x00030000) + Name (_UID, 0x00) + Name (_BBN, 0x03) + + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, //PCIE IRQ28-IRQ31 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, + }) + } //end of PEX0 + + Device (PEX1) + { + Name (_ADR, 0x00030001) + Name (_UID, 0x00) + Name (_BBN, 0x04) + + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, //PCIE IRQ32-IRQ35 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, + }) + } //end f PEX1 + + Device (PEX2) + { + Name (_ADR, 0x00030002) + Name (_UID, 0x00) + Name (_BBN, 0x05) + + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, //PCIE IRQ36-IRQ39 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, + }) + } //end f PEX2 + + Device (PEX3) + { + Name (_ADR, 0x00030003) + Name (_UID, 0x00) + Name (_BBN, 0x06) + + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, //PCIE IRQ40-IRQ43 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, + }) + } //end f PEX3 + + Device (ISA) { + Name (_ADR, 0x00110000) + + /* Keyboard seems to be important for WinXP install */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () + { + IO (Decode16, + 0x0060, // Address Range Minimum + 0x0060, // Address Range Maximum + 0x01, // Address Alignment + 0x01, // Address Length + ) + IO (Decode16, + 0x0064, // Address Range Minimum + 0x0064, // Address Range Maximum + 0x01, // Address Alignment + 0x01, // Address Length + ) + IRQNoFlags () + {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () + { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* PS/2 floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } //FD END + + } //ISA END + + } // End of PCI0 + + + } // End of _SB + +} // End of Definition Block +
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participants (6)
-
Andreas B. Mundt
-
Peter Stuge
-
Rudolf Marek
-
Stefan Reinauer
-
Torsten Duwe
-
Ward Vandewege