Patch set updated for coreboot: 2c75a5c haswell: don't add a 0-sized memory range resource

[Stefan Reinauer]

Stefan Reinauer ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2691

-gerrit

commit 2c75a5c3a8fc5b3a999c882b8614c7f2ad3b39a8
Author: Aaron Durbin 
Date:   Tue Jan 8 10:10:33 2013 -0600

haswell: don't add a 0-sized memory range resource

It's possible that TOUUD can be 4GiB in a small physical memory
    configuration. Therefore, don't add a 0-size memory range resouce
    in that case.

Change-Id: I016616a9d9d615417038e9c847c354db7d872819
    Signed-off-by: Aaron Durbin 
---
 src/northbridge/intel/haswell/northbridge.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index 55c9c6b..90c47a7 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -410,7 +410,8 @@ static void mc_add_dram_resources(device_t dev)
    /* 4GiB -> TOUUD */
    base_k = 4096 * 1024; /* 4GiB */
    size_k = (unsigned long)(mc_values[TOUUD_REG] >> 10) - base_k;
-	ram_resource(dev, index++, base_k, size_k);
+	if (size_k > 0)
+		ram_resource(dev, index++, base_k, size_k);

mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k);
 #if CONFIG_CHROMEOS_RAMOOPS