[v2] r4042 - in trunk/coreboot-v2/src: config cpu/amd/socket_754 cpu/amd/socket_939 cpu/amd/socket_940 cpu/amd/socket_AM2 cpu/amd/socket_F cpu/amd/socket_F_1207 cpu/amd/socket_S1G1 cpu/intel/socket_mPGA604_533Mhz drivers/generic/debug drivers/pci/onboard include/device mainboard/amd/dbm690t mainboard/amd/pistachio mainboard/amd/serengeti_cheetah mainboard/amd/serengeti_cheetah_fam10 mainboard/asus/a8n_e mainboard/asus/a8v-e_se mainboard/asus/m2v-mx_se mainboard/bcom/winnetp680 mainboard/broadcom/
Author: stepan Date: 2009-04-01 15:43:21 +0200 (Wed, 01 Apr 2009) New Revision: 4042
Modified: trunk/coreboot-v2/src/config/Options.lb trunk/coreboot-v2/src/cpu/amd/socket_754/Config.lb trunk/coreboot-v2/src/cpu/amd/socket_939/Config.lb trunk/coreboot-v2/src/cpu/amd/socket_940/Config.lb trunk/coreboot-v2/src/cpu/amd/socket_AM2/Config.lb trunk/coreboot-v2/src/cpu/amd/socket_F/Config.lb trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Config.lb trunk/coreboot-v2/src/cpu/amd/socket_S1G1/Config.lb trunk/coreboot-v2/src/cpu/intel/socket_mPGA604_533Mhz/Config.lb trunk/coreboot-v2/src/drivers/generic/debug/debug_dev.c trunk/coreboot-v2/src/drivers/pci/onboard/onboard.c trunk/coreboot-v2/src/include/device/device.h trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/mainboard.c trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb trunk/coreboot-v2/src/mainboard/asus/a8n_e/mainboard.c trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/mainboard.c trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mainboard.c trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb trunk/coreboot-v2/src/mainboard/broadcom/blast/mainboard.c trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/mainboard.c trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/mainboard.c trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/mainboard.c trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms7135/Config.lb trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms7135/mainboard.c trunk/coreboot-v2/src/mainboard/msi/ms7260/Config.lb trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms7260/mainboard.c trunk/coreboot-v2/src/mainboard/msi/ms9185/Config.lb trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms9185/mainboard.c trunk/coreboot-v2/src/mainboard/msi/ms9282/Config.lb trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms9282/mainboard.c trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/mainboard.c trunk/coreboot-v2/src/mainboard/sunw/ultra40/Config.lb trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb trunk/coreboot-v2/src/mainboard/sunw/ultra40/mainboard.c trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/h8dme/mainboard.c trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/mainboard.c trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2735/mainboard.c trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2850/mainboard.c trunk/coreboot-v2/src/mainboard/tyan/s2875/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2875/mainboard.c trunk/coreboot-v2/src/mainboard/tyan/s2880/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2880/mainboard.c trunk/coreboot-v2/src/mainboard/tyan/s2881/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2881/mainboard.c trunk/coreboot-v2/src/mainboard/tyan/s2882/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2882/mainboard.c trunk/coreboot-v2/src/mainboard/tyan/s2885/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2885/mainboard.c trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2891/mainboard.c trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2892/mainboard.c trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2895/mainboard.c trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2912/mainboard.c trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/mainboard.c trunk/coreboot-v2/src/mainboard/tyan/s4880/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s4880/mainboard.c trunk/coreboot-v2/src/mainboard/tyan/s4882/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s4882/mainboard.c trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb trunk/coreboot-v2/src/mainboard/via/epia/Options.lb trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb trunk/coreboot-v2/src/northbridge/amd/amdfam10/Config.lb trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c trunk/coreboot-v2/src/northbridge/amd/amdk8/Config.lb trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c Log: Drop CONFIG_CHIP_NAME. Those config statements in Config.lb should be used unconditionally, and the names don't hurt.
Signed-off-by: Stefan Reinauer stepan@coresystems.de Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/config/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -854,12 +854,6 @@ # Misc options ###############################################
-define CONFIG_CHIP_NAME - default 0 - export always - comment "Compile in the chip name" -end - define CONFIG_GDB_STUB default 0 export used
Modified: trunk/coreboot-v2/src/cpu/amd/socket_754/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_754/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/cpu/amd/socket_754/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -1,7 +1,4 @@ -uses CONFIG_CHIP_NAME
-if CONFIG_CHIP_NAME - config chip.h -end +config chip.h object socket_754.o dir /cpu/amd/model_fxx
Modified: trunk/coreboot-v2/src/cpu/amd/socket_939/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_939/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/cpu/amd/socket_939/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -1,9 +1,5 @@ -uses CONFIG_CHIP_NAME +config chip.h
-if CONFIG_CHIP_NAME - config chip.h -end - object socket_939.o
dir /cpu/amd/model_fxx
Modified: trunk/coreboot-v2/src/cpu/amd/socket_940/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_940/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/cpu/amd/socket_940/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -1,9 +1,5 @@ -uses CONFIG_CHIP_NAME +config chip.h
-if CONFIG_CHIP_NAME - config chip.h -end - object socket_940.o
dir /cpu/amd/model_fxx
Modified: trunk/coreboot-v2/src/cpu/amd/socket_AM2/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_AM2/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/cpu/amd/socket_AM2/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -1,12 +1,9 @@ -uses CONFIG_CHIP_NAME uses K8_REV_F_SUPPORT uses K8_HT_FREQ_1G_SUPPORT uses DIMM_SUPPORT uses CPU_SOCKET_TYPE
-if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
default K8_REV_F_SUPPORT=1 #Opteron K8 1G HT Support
Modified: trunk/coreboot-v2/src/cpu/amd/socket_F/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_F/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/cpu/amd/socket_F/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -1,12 +1,9 @@ -uses CONFIG_CHIP_NAME uses K8_REV_F_SUPPORT uses K8_HT_FREQ_1G_SUPPORT uses DIMM_SUPPORT uses CPU_SOCKET_TYPE
-if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
default K8_REV_F_SUPPORT=1 #Opteron K8 1G HT Support
Modified: trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -17,7 +17,6 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA #
-uses CONFIG_CHIP_NAME uses PCI_IO_CFG_EXT uses MMCONF_SUPPORT uses HT3_SUPPORT @@ -30,9 +29,7 @@ uses PCI_BUS_SEGN_BITS uses CAR_FAM10
-if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
default PCI_IO_CFG_EXT=1
Modified: trunk/coreboot-v2/src/cpu/amd/socket_S1G1/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_S1G1/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/cpu/amd/socket_S1G1/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -1,12 +1,9 @@ -uses CONFIG_CHIP_NAME uses K8_REV_F_SUPPORT uses K8_HT_FREQ_1G_SUPPORT uses DIMM_SUPPORT uses CPU_SOCKET_TYPE
-if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
default K8_REV_F_SUPPORT=1 #Opteron K8 1G HT Support
Modified: trunk/coreboot-v2/src/cpu/intel/socket_mPGA604_533Mhz/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mPGA604_533Mhz/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA604_533Mhz/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -1,6 +1,3 @@ -uses CONFIG_CHIP_NAME -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h object socket_mPGA604_533Mhz.o dir /cpu/intel/model_f2x
Modified: trunk/coreboot-v2/src/drivers/generic/debug/debug_dev.c =================================================================== --- trunk/coreboot-v2/src/drivers/generic/debug/debug_dev.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/drivers/generic/debug/debug_dev.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -231,13 +231,11 @@
static void debug_init(device_t dev) { -#if CONFIG_CHIP_NAME device_t parent; -#endif + if (!dev->enabled) return; switch(dev->path.pnp.device) { -#if CONFIG_CHIP_NAME case 0: parent = dev->bus->dev; printk_debug("DEBUG: %s", dev_path(parent)); @@ -247,7 +245,6 @@ printk_debug("\n"); } break; -#endif case 1: print_pci_regs_all();
Modified: trunk/coreboot-v2/src/drivers/pci/onboard/onboard.c =================================================================== --- trunk/coreboot-v2/src/drivers/pci/onboard/onboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/drivers/pci/onboard/onboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -73,8 +73,6 @@ }
struct chip_operations drivers_pci_onboard_ops = { -#if CONFIG_CHIP_NAME == 1 CHIP_NAME("Onboard PCI") -#endif .enable_dev = onboard_enable, };
Modified: trunk/coreboot-v2/src/include/device/device.h =================================================================== --- trunk/coreboot-v2/src/include/device/device.h 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/include/device/device.h 2009-04-01 13:43:21 UTC (rev 4042) @@ -15,16 +15,10 @@ /* Chip operations */ struct chip_operations { void (*enable_dev)(struct device *dev); -#if CONFIG_CHIP_NAME == 1 char *name; -#endif };
-#if CONFIG_CHIP_NAME == 1 #define CHIP_NAME(X) .name = X, -#else -#define CHIP_NAME(X) -#endif
struct bus;
Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -178,9 +178,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
#The variables belong to mainboard are defined here.
Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -73,7 +73,6 @@ uses CC uses HOSTCC uses OBJCOPY -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK @@ -157,9 +156,6 @@ default CONFIG_MAX_PHYSICAL_CPUS=1 default CONFIG_LOGICAL_CPUS=1
-#CHIP_NAME ? -default CONFIG_CHIP_NAME=1 - #1G memory hole default HW_MEM_HOLE_SIZEK=0x100000
Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -263,9 +263,6 @@ #endif }
-/* -* CONFIG_CHIP_NAME defined in Option.lb. -*/ struct chip_operations mainboard_ops = { CHIP_NAME("AMD DBM690T Mainboard") .enable_dev = dbm690t_enable,
Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -178,9 +178,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
#The variables belong to mainboard are defined here.
Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -73,7 +73,6 @@ uses CC uses HOSTCC uses OBJCOPY -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK @@ -157,9 +156,6 @@ default CONFIG_MAX_PHYSICAL_CPUS=1 default CONFIG_LOGICAL_CPUS=1
-#CHIP_NAME ? -default CONFIG_CHIP_NAME=1 - #1G memory hole default HW_MEM_HOLE_SIZEK=0x100000
Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -335,9 +335,6 @@ #endif }
-/* -* CONFIG_CHIP_NAME defined in Option.lb. -*/ struct chip_operations mainboard_ops = { CHIP_NAME("AMD Pistachio Mainboard") .enable_dev = pistachio_enable,
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -253,9 +253,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
# sample config for amd/serengeti_cheetah chip northbridge/amd/amdk8/root_complex
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -57,7 +57,6 @@ uses CC uses HOSTCC uses OBJCOPY -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK @@ -171,9 +170,6 @@ default APIC_ID_OFFSET=0x8 default LIFT_BSP_APIC_ID=1
-#CHIP_NAME ? -default CONFIG_CHIP_NAME=1 - #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G #default HW_MEM_HOLE_SIZEK=0x200000
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -1,9 +1,7 @@ #include <device/device.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("AMD Serengeti Cheetah Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -263,9 +263,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
dir /southbridge/amd/amd8151
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -76,7 +76,6 @@ uses CC uses HOSTCC uses OBJCOPY -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK @@ -197,9 +196,6 @@ default APIC_ID_OFFSET=0x00 default LIFT_BSP_APIC_ID=1
-#CHIP_NAME ? -default CONFIG_CHIP_NAME=1 - #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G #default HW_MEM_HOLE_SIZEK=0x200000
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -25,8 +25,6 @@ #include <device/pci_ops.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("AMD family 10 Cheetah mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -146,9 +146,7 @@ mainboardinit ./auto.inc end end -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
chip northbridge/amd/amdk8/root_complex # Root complex device apic_cluster 0 on # APIC cluster
Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -77,7 +77,6 @@ uses CONFIG_CONSOLE_BTEXT uses HAVE_INIT_TIMER uses CONFIG_GDB_STUB -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK
Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -22,8 +22,6 @@ #include <device/device.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("ASUS A8N-E Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -112,9 +112,7 @@ end end
-if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
chip northbridge/amd/amdk8/root_complex # Root complex device apic_cluster 0 on # APIC cluster
Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -71,7 +71,6 @@ uses CONFIG_CONSOLE_SERIAL8250 uses HAVE_INIT_TIMER uses CONFIG_GDB_STUB -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN # bx_b001- uses K8_HW_MEM_HOLE_SIZEK @@ -111,7 +110,6 @@ default CONFIG_MAX_PHYSICAL_CPUS = 1 default CONFIG_LOGICAL_CPUS = 1 default HAVE_ACPI_TABLES = 1 -# default CONFIG_CHIP_NAME = 1
# 1G memory hole # bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000
Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -23,8 +23,6 @@ #include <device/pci_ids.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("ASUS A8V-E SE Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -115,9 +115,7 @@ end end
-if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
chip northbridge/amd/amdk8/root_complex # Root complex device apic_cluster 0 on # APIC cluster
Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -74,7 +74,6 @@ uses CONFIG_CONSOLE_SERIAL8250 uses HAVE_INIT_TIMER uses CONFIG_GDB_STUB -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN # bx_b001- uses K8_HW_MEM_HOLE_SIZEK @@ -118,8 +117,6 @@ default HAVE_HIGH_TABLES = 1 default HAVE_LOW_TABLES = 0
-# default CONFIG_CHIP_NAME = 1 - # 1G memory hole # bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000
Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -37,8 +37,6 @@ return 0; }
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("ASUS M2V-MX SE Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -64,7 +64,6 @@ uses CONFIG_PCI_ROM_RUN uses CONFIG_CONSOLE_VGA uses CONFIG_MAX_PCI_BUSES -uses CONFIG_CHIP_NAME uses CONFIG_VIDEO_MB uses CONFIG_IOAPIC
@@ -74,7 +73,6 @@ default CONFIG_CONSOLE_SERIAL8250 = 1 default CONFIG_PCI_ROM_RUN = 0 default CONFIG_CONSOLE_VGA = 0 -default CONFIG_CHIP_NAME = 1 default HAVE_FALLBACK_BOOT = 1 default HAVE_MP_TABLE = 0 default CONFIG_UDELAY_TSC = 1
Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -145,9 +145,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
# sample config for broadcom/blast chip northbridge/amd/amdk8/root_complex
Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -53,7 +53,6 @@ uses CC uses HOSTCC uses OBJCOPY -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK @@ -128,9 +127,6 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1
-#CHIP_NAME ? -default CONFIG_CHIP_NAME=1 - #1G memory hole default HW_MEM_HOLE_SIZEK=0x100000
Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/broadcom/blast/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/broadcom/blast/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -1,9 +1,7 @@ #include <device/device.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("Broadcom Blast Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -223,9 +223,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -81,7 +81,6 @@ uses CC uses HOSTCC uses OBJCOPY -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_USBDEBUG_DIRECT uses CONFIG_PCI_ROM_RUN @@ -195,9 +194,6 @@ default APIC_ID_OFFSET=0x10 default LIFT_BSP_APIC_ID=1
-#CHIP_NAME ? -default CONFIG_CHIP_NAME=1 - #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G #default HW_MEM_HOLE_SIZEK=0x200000
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -26,8 +26,6 @@ #include <device/pci_ops.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("GIGABYTE GA-2761GXDK Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -225,9 +225,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -79,7 +79,6 @@ uses CC uses HOSTCC uses OBJCOPY -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_USBDEBUG_DIRECT uses CONFIG_PCI_ROM_RUN @@ -199,9 +198,6 @@ default APIC_ID_OFFSET=0x10 default LIFT_BSP_APIC_ID=1
-#CHIP_NAME ? -default CONFIG_CHIP_NAME=1 - #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G #default HW_MEM_HOLE_SIZEK=0x200000
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -26,8 +26,6 @@ #include <device/pci_ops.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("GIGABYTE GA-M57SLI Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -142,9 +142,7 @@ ## dir /pc80
-if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
# based on sample config for tyan/s2735 chip northbridge/intel/e7501
Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -40,7 +40,6 @@ uses CC uses HOSTCC uses OBJCOPY -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses DEBUG @@ -238,7 +237,6 @@
default DEBUG=1 # default CPU_OPT="-g" -default CONFIG_CHIP_NAME=1
### End Options.lb #
Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -1,9 +1,7 @@ #include <device/device.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("Intel Xeon E7501 DevKit Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -261,9 +261,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
dir /southbridge/amd/amd8132
Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -57,7 +57,6 @@ uses CC uses HOSTCC uses OBJCOPY -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK @@ -171,9 +170,6 @@ default APIC_ID_OFFSET=0x10 default LIFT_BSP_APIC_ID=1
-#CHIP_NAME ? -default CONFIG_CHIP_NAME=1 - #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G #default HW_MEM_HOLE_SIZEK=0x200000
Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -1,9 +1,6 @@ #include <device/device.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("IWILL DK8-HTX Mainboard") }; -#endif -
Modified: trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -65,7 +65,6 @@ uses CONFIG_CONSOLE_VGA uses CONFIG_MAX_PCI_BUSES uses TTYS0_BAUD -uses CONFIG_CHIP_NAME uses CONFIG_VIDEO_MB uses CONFIG_IOAPIC
@@ -75,7 +74,6 @@ default CONFIG_CONSOLE_SERIAL8250 = 1 default CONFIG_PCI_ROM_RUN = 0 default CONFIG_CONSOLE_VGA = 0 -default CONFIG_CHIP_NAME = 1 default HAVE_FALLBACK_BOOT = 1 default HAVE_MP_TABLE = 0 default CONFIG_UDELAY_TSC = 1
Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -58,7 +58,6 @@ uses _ROMBASE uses STACK_SIZE uses HEAP_SIZE -uses CONFIG_CHIP_NAME uses USE_DCACHE_RAM uses DCACHE_RAM_BASE uses DCACHE_RAM_SIZE @@ -324,11 +323,6 @@ ## Select power on after power fail setting default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-## -## chip name -## -default CONFIG_CHIP_NAME=1 - # # ROMFS #
Modified: trunk/coreboot-v2/src/mainboard/msi/ms7135/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -223,9 +223,7 @@ ## ## Include the secondary configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
chip northbridge/amd/amdk8/root_complex # Root complex device apic_cluster 0 on # APIC cluster
Modified: trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -77,7 +77,6 @@ uses CONFIG_CONSOLE_BTEXT uses HAVE_INIT_TIMER uses CONFIG_GDB_STUB -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK
Modified: trunk/coreboot-v2/src/mainboard/msi/ms7135/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -21,8 +21,6 @@ #include <device/device.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("MSI MS7135 Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7260/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/msi/ms7260/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -164,9 +164,7 @@ end end
-if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
chip northbridge/amd/amdk8/root_complex # Root complex device apic_cluster 0 on # APIC cluster
Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -74,7 +74,6 @@ uses CC uses HOSTCC uses OBJCOPY -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_USBDEBUG_DIRECT @@ -120,7 +119,6 @@ default ENABLE_APIC_EXT_ID = 0 default APIC_ID_OFFSET = 0x10 default LIFT_BSP_APIC_ID = 1 -default CONFIG_CHIP_NAME = 1
# Move the default coreboot CMOS range off of AMD RTC registers. default LB_CKS_RANGE_START = 49
Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7260/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/msi/ms7260/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -21,8 +21,6 @@ #include <device/device.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("MSI K9N Neo (MS-7260) Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9185/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/msi/ms9185/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -172,9 +172,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
# sample config for amd/serengeti_cheetah chip northbridge/amd/amdk8/root_complex
Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -78,7 +78,6 @@ uses CC uses HOSTCC uses OBJCOPY -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK @@ -180,9 +179,6 @@ default APIC_ID_OFFSET=0x8 default LIFT_BSP_APIC_ID=1
-#CHIP_NAME ? -default CONFIG_CHIP_NAME=1 - #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G #default HW_MEM_HOLE_SIZEK=0x200000
Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9185/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/msi/ms9185/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -26,8 +26,6 @@ #include <device/pci_ops.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("MSI MS-9185 Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9282/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/msi/ms9282/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -222,9 +222,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
# sample config for msi/ms9282
Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -74,7 +74,6 @@ uses CONFIG_CONSOLE_SERIAL8250 uses HAVE_INIT_TIMER uses CONFIG_GDB_STUB -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN #bx_b001- uses K8_HW_MEM_HOLE_SIZEK @@ -164,9 +163,6 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1
-#CHIP_NAME ? -#default CONFIG_CHIP_NAME=1 - #1G memory hole #bx_b001- default K8_HW_MEM_HOLE_SIZEK=0x100000
Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9282/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/msi/ms9282/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -26,8 +26,6 @@ #include <device/pci_ops.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("MSI MS-9282 Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -51,7 +51,6 @@ uses CC uses HOSTCC uses OBJCOPY -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK @@ -121,9 +120,6 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1
-#CHIP_NAME ? -default CONFIG_CHIP_NAME=1 - #1G memory hole default HW_MEM_HOLE_SIZEK=0x100000
Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -252,9 +252,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on
Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -79,7 +79,6 @@ uses CC uses HOSTCC uses OBJCOPY -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_USBDEBUG_DIRECT uses CONFIG_PCI_ROM_RUN @@ -193,9 +192,6 @@ default APIC_ID_OFFSET=0x10 default LIFT_BSP_APIC_ID=1
-#CHIP_NAME ? -default CONFIG_CHIP_NAME=1 - #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G #default HW_MEM_HOLE_SIZEK=0x200000
Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -26,8 +26,6 @@ #include <device/pci_ops.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("NVIDIA l1_2pvv Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/sunw/ultra40/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -188,9 +188,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
# sample config for tyan/s2895 chip northbridge/amd/amdk8/root_complex
Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -52,7 +52,6 @@ uses CONFIG_CONSOLE_SERIAL8250 uses HAVE_INIT_TIMER uses CONFIG_GDB_STUB -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK @@ -134,9 +133,6 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1
-#CHIP_NAME ? -#default CONFIG_CHIP_NAME=1 - #1G memory hole default HW_MEM_HOLE_SIZEK=0x100000
Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/sunw/ultra40/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -1,9 +1,7 @@ #include <device/device.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("Sun Ultra 40 Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -218,9 +218,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on
Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -79,7 +79,6 @@ uses CC uses HOSTCC uses OBJCOPY -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK @@ -192,9 +191,6 @@ default APIC_ID_OFFSET=0x10 default LIFT_BSP_APIC_ID=1
-#CHIP_NAME ? -default CONFIG_CHIP_NAME=1 - #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G #default HW_MEM_HOLE_SIZEK=0x200000
Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -23,8 +23,6 @@ #include <device/pci_ops.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("Supermicro H8DME Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -221,9 +221,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on
Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -79,7 +79,6 @@ uses CC uses HOSTCC uses OBJCOPY -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK @@ -192,9 +191,6 @@ default APIC_ID_OFFSET=0x10 default LIFT_BSP_APIC_ID=1
-#CHIP_NAME ? -default CONFIG_CHIP_NAME=1 - #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G #default HW_MEM_HOLE_SIZEK=0x200000
Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -26,8 +26,6 @@ #include <device/pci_ops.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("Supermicro H8DMR Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -39,7 +39,6 @@ uses TTYS0_BAUD uses TTYS0_BASE uses TTYS0_LCS -uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_SERIAL8250 @@ -137,10 +136,6 @@ default CC="$(CROSS_COMPILE)gcc -m32" default HOSTCC="gcc"
-default CONFIG_CHIP_NAME = 1 - - - # # ROMFS #
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -175,11 +175,8 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
- # sample config for tyan/s2735 chip northbridge/intel/e7501 device pci_domain 0 on
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -56,7 +56,6 @@ uses CONFIG_CONSOLE_BTEXT uses HAVE_INIT_TIMER uses CONFIG_GDB_STUB -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2735/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2735/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -1,9 +1,7 @@ #include <device/device.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2735 Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -185,9 +185,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
# sample config for tyan/s2850 chip northbridge/amd/amdk8/root_complex
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -52,7 +52,6 @@ uses CC uses HOSTCC uses OBJCOPY -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK @@ -122,9 +121,6 @@ default CONFIG_MAX_PHYSICAL_CPUS=1 default CONFIG_LOGICAL_CPUS=1
-#CHIP_NAME ? -default CONFIG_CHIP_NAME=1 - #1G memory hole default HW_MEM_HOLE_SIZEK=0x100000
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2850/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2850/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -1,9 +1,7 @@ #include <device/device.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2850 Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2875/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2875/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -185,9 +185,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
# sample config for tyan/s2875 chip northbridge/amd/amdk8/root_complex
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -52,7 +52,6 @@ uses CC uses HOSTCC uses OBJCOPY -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK @@ -123,9 +122,6 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1
-#CHIP_NAME ? -default CONFIG_CHIP_NAME=1 - #1G memory hole default HW_MEM_HOLE_SIZEK=0x100000
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2875/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2875/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -1,9 +1,7 @@ #include <device/device.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2875 Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2880/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2880/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2880/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -185,9 +185,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
# sample config for tyan/s2880 chip northbridge/amd/amdk8/root_complex
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -52,7 +52,6 @@ uses CC uses HOSTCC uses OBJCOPY -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK @@ -122,9 +121,6 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=0
-#CHIP_NAME ? -default CONFIG_CHIP_NAME=1 - #1G memory hole default HW_MEM_HOLE_SIZEK=0x100000
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2880/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2880/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2880/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -1,9 +1,7 @@ #include <device/device.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2880 Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2881/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2881/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -185,9 +185,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
# sample config for tyan/s2881 chip northbridge/amd/amdk8/root_complex
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -52,7 +52,6 @@ uses CC uses HOSTCC uses OBJCOPY -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK @@ -127,9 +126,6 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1
-#CHIP_NAME ? -default CONFIG_CHIP_NAME=1 - ##HT Unit ID offset, default is 1, the typical one default HT_CHAIN_UNITID_BASE=0x0a
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2881/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2881/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -158,9 +158,7 @@ dev->ops = &mainboard_operations; }
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2881 Mainboard") .enable_dev = enable_dev, }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2882/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2882/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -185,9 +185,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
# sample config for tyan/s2882 chip northbridge/amd/amdk8/root_complex
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -52,7 +52,6 @@ uses CC uses HOSTCC uses OBJCOPY -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK @@ -122,9 +121,6 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1
-#CHIP_NAME ? -default CONFIG_CHIP_NAME=1 - #1G memory hole default HW_MEM_HOLE_SIZEK=0x100000
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2882/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2882/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -1,9 +1,7 @@ #include <device/device.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2882 Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2885/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2885/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -185,9 +185,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
# sample config for tyan/s2885 chip northbridge/amd/amdk8/root_complex
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -52,7 +52,6 @@ uses CC uses HOSTCC uses OBJCOPY -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK @@ -133,9 +132,6 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1
-#CHIP_NAME ? -default CONFIG_CHIP_NAME=1 - ##HT Unit ID offset, default is 1, the typical one default HT_CHAIN_UNITID_BASE=0x0a
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2885/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2885/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -1,9 +1,7 @@ #include <device/device.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2885 Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -205,9 +205,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
# sample config for tyan/s2891 chip northbridge/amd/amdk8/root_complex
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -59,7 +59,6 @@ uses CONFIG_CONSOLE_BTEXT uses HAVE_INIT_TIMER uses CONFIG_GDB_STUB -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_VGA_ROM_RUN uses CONFIG_PCI_ROM_RUN
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -17,9 +17,7 @@ }
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2891 Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -206,9 +206,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
# sample config for tyan/s2892 chip northbridge/amd/amdk8/root_complex
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -59,7 +59,6 @@ uses CONFIG_CONSOLE_BTEXT uses HAVE_INIT_TIMER uses CONFIG_GDB_STUB -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_VGA_ROM_RUN uses CONFIG_PCI_ROM_RUN
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -17,9 +17,7 @@ }
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2892 Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -242,9 +242,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
# sample config for tyan/s2895 chip northbridge/amd/amdk8/root_complex
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -61,7 +61,6 @@ uses CONFIG_CONSOLE_SERIAL8250 uses HAVE_INIT_TIMER uses CONFIG_GDB_STUB -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_VGA_ROM_RUN uses CONFIG_PCI_ROM_RUN @@ -169,9 +168,6 @@
default SERIAL_CPU_INIT=0
-#CHIP_NAME ? -#default CONFIG_CHIP_NAME=1 - #1G memory hole default HW_MEM_HOLE_SIZEK=0x100000
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -17,9 +17,7 @@ }
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2895 Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -222,9 +222,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -79,7 +79,6 @@ uses CC uses HOSTCC uses OBJCOPY -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_USBDEBUG_DIRECT uses CONFIG_PCI_ROM_RUN @@ -195,9 +194,6 @@ default APIC_ID_OFFSET=0x10 default LIFT_BSP_APIC_ID=1
-#CHIP_NAME ? -default CONFIG_CHIP_NAME=1 - #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G #default HW_MEM_HOLE_SIZEK=0x200000
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -26,8 +26,6 @@ #include <device/pci_ops.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2912 Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -223,9 +223,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
dir /southbridge/nvidia/mcp55
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -78,7 +78,6 @@ uses CC uses HOSTCC uses OBJCOPY -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_USBDEBUG_DIRECT uses CONFIG_PCI_ROM_RUN @@ -197,9 +196,6 @@ default APIC_ID_OFFSET=0x00 default LIFT_BSP_APIC_ID=1
-#CHIP_NAME ? -default CONFIG_CHIP_NAME=1 - #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G #default HW_MEM_HOLE_SIZEK=0x200000
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -26,8 +26,6 @@ #include <device/pci_ops.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2912 Mainboard (Family 10)") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4880/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s4880/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -186,9 +186,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
# sample config for tyan/s4880 chip northbridge/amd/amdk8/root_complex
Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -52,7 +52,6 @@ uses CC uses HOSTCC uses OBJCOPY -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK @@ -126,9 +125,6 @@ default CONFIG_MAX_PHYSICAL_CPUS=4 default CONFIG_LOGICAL_CPUS=1
-#CHIP_NAME ? -default CONFIG_CHIP_NAME=1 - #1G memory hole default HW_MEM_HOLE_SIZEK=0x100000
Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4880/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s4880/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -1,9 +1,7 @@ #include <device/device.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S4880 Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4882/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s4882/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -186,9 +186,7 @@ ## ## Include the secondary Configuration files ## -if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
# sample config for tyan/s4882 chip northbridge/amd/amdk8/root_complex
Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -52,7 +52,6 @@ uses CC uses HOSTCC uses OBJCOPY -uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK @@ -126,9 +125,6 @@ default CONFIG_MAX_PHYSICAL_CPUS=4 default CONFIG_LOGICAL_CPUS=1
-#CHIP_NAME ? -default CONFIG_CHIP_NAME=1 - #1G memory hole default HW_MEM_HOLE_SIZEK=0x100000
Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4882/mainboard.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/tyan/s4882/mainboard.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -1,9 +1,7 @@ #include <device/device.h> #include "chip.h"
-#if CONFIG_CHIP_NAME == 1 struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S4882 Mainboard") }; -#endif
Modified: trunk/coreboot-v2/src/mainboard/via/epia/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/via/epia/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -5,7 +5,6 @@ uses TTYS0_BAUD uses TTYS0_BASE uses TTYS0_LCS -uses CONFIG_CHIP_NAME uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE @@ -64,7 +63,6 @@ # This defaults to 8 data bits, 1 stop bit, and no parity default TTYS0_LCS=0x3
-default CONFIG_CHIP_NAME=1 ## ROM_SIZE is the size of boot ROM that this board will use. default ROM_SIZE = 256*1024
Modified: trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -65,7 +65,6 @@ uses CONFIG_CONSOLE_VGA uses CONFIG_MAX_PCI_BUSES uses TTYS0_BAUD -uses CONFIG_CHIP_NAME uses CONFIG_VIDEO_MB uses CONFIG_IOAPIC
@@ -75,7 +74,6 @@ default CONFIG_CONSOLE_SERIAL8250 = 1 default CONFIG_PCI_ROM_RUN = 0 default CONFIG_CONSOLE_VGA = 0 -default CONFIG_CHIP_NAME = 1 default HAVE_FALLBACK_BOOT = 1 default HAVE_MP_TABLE = 0 default CONFIG_UDELAY_TSC = 1
Modified: trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -68,7 +68,6 @@ uses TTYS0_BAUD uses TTYS0_BASE uses TTYS0_LCS -uses CONFIG_CHIP_NAME uses CONFIG_VIDEO_MB uses CONFIG_IOAPIC
@@ -80,7 +79,6 @@ default CONFIG_CONSOLE_SERIAL8250 = 1 default CONFIG_PCI_ROM_RUN = 0 default CONFIG_CONSOLE_VGA = 0 -default CONFIG_CHIP_NAME = 1 default HAVE_FALLBACK_BOOT = 1 default CONFIG_SMP = 1 default HAVE_MP_TABLE = 1
Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -17,15 +17,12 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA #
-uses CONFIG_CHIP_NAME uses AGP_APERTURE_SIZE uses HAVE_ACPI_TABLES
default AGP_APERTURE_SIZE=0x4000000
-if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
driver northbridge.o driver misc_control.o
Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -652,15 +652,11 @@ .device = 0x1200, };
-#if CONFIG_CHIP_NAME == 1 - struct chip_operations northbridge_amd_amdfam10_ops = { CHIP_NAME("AMD FAM10 Northbridge") .enable_dev = 0, };
-#endif - static void pci_domain_read_resources(device_t dev) { struct resource *resource;
Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/Config.lb 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/Config.lb 2009-04-01 13:43:21 UTC (rev 4042) @@ -1,12 +1,9 @@ -uses CONFIG_CHIP_NAME uses AGP_APERTURE_SIZE uses HAVE_ACPI_TABLES
default AGP_APERTURE_SIZE=0x4000000
-if CONFIG_CHIP_NAME - config chip.h -end +config chip.h
driver northbridge.o driver misc_control.o
Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c 2009-04-01 11:37:39 UTC (rev 4041) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c 2009-04-01 13:43:21 UTC (rev 4042) @@ -629,15 +629,11 @@ .device = 0x1100, };
-#if CONFIG_CHIP_NAME == 1 - struct chip_operations northbridge_amd_amdk8_ops = { CHIP_NAME("AMD K8 Northbridge") .enable_dev = 0, };
-#endif - static void pci_domain_read_resources(device_t dev) { struct resource *resource;
-
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