I'm trying to figure out how to reroute i/o amd memory space from the pci space to the LBC Bridge. Anyone out there know which registers to touch in the SSI550. I have the SIS register programming but it doesn't describe which registers have to be touched to accomplish this.
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On Mon, 2004-03-22 at 15:32, Frank wrote:
I'm trying to figure out how to reroute i/o amd memory space from the pci space to the LBC Bridge. Anyone out there know which registers to touch in the SSI550. I have the SIS register programming but it doesn't describe which registers have to be touched to accomplish this.
What do you mean by mapping PCI IO/MEM space to LPC bridge ? LPC bridge bridges ISA devices which have different address space than PCI.
Ollie
You just answered my question, I think. So you're saying if I access i/o port 0x3f8 (com1) or the lpt port the access will be forworded to the LPC bus? I thought the LPC was just another bridge on the PCI bus and you had to setup the I/O and Memory base address regitsters just like any other PCI bridge device. Sorry for asking what appears to be a stupid question, but I come from the MIPS and PPC part of the world. I haven't done any P.C. programming in 15 years...
--- Li-Ta Lo ollie@lanl.gov wrote:
On Mon, 2004-03-22 at 15:32, Frank wrote:
I'm trying to figure out how to reroute i/o amd memory space from the pci space to the LBC Bridge. Anyone out there know which registers to touch in the SSI550. I have the SIS
register
programming but it doesn't describe which registers have to
be
touched to accomplish this.
What do you mean by mapping PCI IO/MEM space to LPC bridge ? LPC bridge bridges ISA devices which have different address space than PCI.
Ollie
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I have Intel's LPC Hardware Specification but it doesn't go in detail from a software point of view. Do you know where I can get a software specification... --- Li-Ta Lo ollie@lanl.gov wrote:
On Mon, 2004-03-22 at 15:32, Frank wrote:
I'm trying to figure out how to reroute i/o amd memory space from the pci space to the LBC Bridge. Anyone out there know which registers to touch in the SSI550. I have the SIS
register
programming but it doesn't describe which registers have to
be
touched to accomplish this.
What do you mean by mapping PCI IO/MEM space to LPC bridge ? LPC bridge bridges ISA devices which have different address space than PCI.
Ollie
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On Tue, 2004-03-23 at 09:49, Frank wrote:
I have Intel's LPC Hardware Specification but it doesn't go in detail from a software point of view. Do you know where I can get a software specification...
You have to find out the LPC superio chip docs. AFIAK, 550 an its own LPC embedded. Did you get the full doc from SiS ?
Ollie
Yes, we signed an NDA and have all of the documentation. But the manual is very poorly written and it is ver difficult to find anything. I have read the register programming manual a hundred times and cannot figure out where you set the BAR registers for the LPC bridge.:-( It has registers to set the base address for the ACPI and other devices hanging off of the LPC but I cannot find the register that say "map this i/o or memory address space and define the size of the address space". I have a feeling they gave us an incomplete manual.:-(
--- Li-Ta Lo ollie@lanl.gov wrote:
On Tue, 2004-03-23 at 09:49, Frank wrote:
I have Intel's LPC Hardware Specification but it doesn't go
in
detail from a software point of view. Do you know where I
can
get a software specification...
You have to find out the LPC superio chip docs. AFIAK, 550 an its own LPC embedded. Did you get the full doc from SiS ?
Ollie
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On Tue, 2004-03-23 at 10:12, Frank wrote:
Yes, we signed an NDA and have all of the documentation. But the manual is very poorly written and it is ver difficult to find anything. I have read the register programming manual a hundred times and cannot figure out where you set the BAR registers for the LPC bridge.:-( It has registers to set the base address for the ACPI and other devices hanging off of the LPC but I cannot find the register that say "map this i/o or memory address space and define the size of the address space". I have a feeling they gave us an incomplete manual.:-(
Believe me, that's the best they can offer ;-). Those LPC devices are legacy which have "well know" fixe address.
Ollie
Ok, Just to confirm what I think you are saying: If I access I/O port 0x3f8 (COM1) it automagically goes to the LPC bus??
--- Li-Ta Lo ollie@lanl.gov wrote:
On Tue, 2004-03-23 at 10:12, Frank wrote:
Yes, we signed an NDA and have all of the documentation. But
the
manual is very poorly written and it is ver difficult to
find
anything. I have read the register programming manual a
hundred
times and cannot figure out where you set the BAR registers
for
the LPC bridge.:-( It has registers to set the base address for the ACPI and
other
devices hanging off of the LPC but I cannot find the
register
that say "map this i/o or memory address space and define
the
size of the address space". I have a feeling they gave us an incomplete manual.:-(
Believe me, that's the best they can offer ;-). Those LPC devices are legacy which have "well know" fixe address.
Ollie
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On Tue, 2004-03-23 at 10:31, Frank wrote:
Ok, Just to confirm what I think you are saying: If I access I/O port 0x3f8 (COM1) it automagically goes to the LPC bus??
It depends on what you mean by "goes to the LPC bus". It will go to the COM1 device "via" the LPC bus. If you want to access other device, you need to access some other magic io ports.
Ollie
That's exactly what I was getting at: accessing all legacy devices by referencing their address space causes an LBC bus transaction. Thanks for clearing that up. Like I said I have been doing mostly MIPS and PPC development (The Gods have been kind) and haven't done any PC embedded programming for the past 15 years...
--- Li-Ta Lo ollie@lanl.gov wrote:
On Tue, 2004-03-23 at 10:31, Frank wrote:
Ok, Just to confirm what I think you are saying: If I access I/O port 0x3f8 (COM1) it automagically goes to
the
LPC bus??
It depends on what you mean by "goes to the LPC bus". It will go to the COM1 device "via" the LPC bus. If you want to access other device, you need to access some other magic io ports.
Ollie
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-
Frank -
Li-Ta Lo